serial: msm_serial_hs: Add snapshot of serial highspeed driver
This change adds a snapshot of the BLSP based HSUART driver
from kernel-4.14 baseline.
This is snapshot of the BLSP based HSUART driver as of
msm-4.14 'commit 78bed541dbf8950be ("Merge "msm:
camera: hyp: To fix Stack overflow"")'.
Change-Id: I39b47c672d8f38a55989d747fbd6ebdcbe9af68b
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
Signed-off-by: Chetan C R <cchinnad@codeaurora.org>
This commit is contained in:
Mukesh Kumar Savaliya
committed by
Chetan C R
Chetan C R
parent
b3a442afca
commit
f9d858bf84
@@ -1013,6 +1013,18 @@ config SERIAL_MSM_GENI_HALF_SAMPLING
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As earlycon can't have HW version awareness, decision is taken
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based on the configuration.
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config SERIAL_MSM_HS
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tristate "MSM UART High Speed: Serial Driver"
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depends on ARCH_QCOM
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select SERIAL_CORE
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help
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If you have a machine based on MSM family of SoCs, you
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can enable its onboard high speed serial port by enabling
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this option.
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Choose M here to compile it as a module. The module will be
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called msm_serial_hs.
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config SERIAL_VT8500
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bool "VIA VT8500 on-chip serial port support"
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depends on ARCH_VT8500
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@@ -59,6 +59,7 @@ obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
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obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
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obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
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obj-$(CONFIG_SERIAL_MSM_GENI) += msm_geni_serial.o
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obj-$(CONFIG_SERIAL_MSM_HS) += msm_serial_hs.o
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obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
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obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
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obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
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3790
drivers/tty/serial/msm_serial_hs.c
Normal file
3790
drivers/tty/serial/msm_serial_hs.c
Normal file
File diff suppressed because it is too large
Load Diff
269
drivers/tty/serial/msm_serial_hs_hwreg.h
Normal file
269
drivers/tty/serial/msm_serial_hs_hwreg.h
Normal file
@@ -0,0 +1,269 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* drivers/serial/msm_serial_hs_hwreg.h
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*
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* Copyright (c) 2007-2009, 2012-2018, 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef MSM_SERIAL_HS_HWREG_H
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#define MSM_SERIAL_HS_HWREG_H
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#define GSBI_CONTROL_ADDR 0x0
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#define GSBI_PROTOCOL_CODE_MASK 0x30
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#define GSBI_PROTOCOL_I2C_UART 0x60
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#define GSBI_PROTOCOL_UART 0x40
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#define GSBI_PROTOCOL_IDLE 0x0
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#define TCSR_ADM_1_A_CRCI_MUX_SEL 0x78
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#define TCSR_ADM_1_B_CRCI_MUX_SEL 0x7C
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#define ADM1_CRCI_GSBI6_RX_SEL 0x800
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#define ADM1_CRCI_GSBI6_TX_SEL 0x400
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#define MSM_ENABLE_UART_CLOCK TIOCPMGET
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#define MSM_DISABLE_UART_CLOCK TIOCPMPUT
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#define MSM_GET_UART_CLOCK_STATUS TIOCPMACT
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enum msm_hsl_regs {
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UARTDM_MR1,
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UARTDM_MR2,
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UARTDM_IMR,
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UARTDM_SR,
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UARTDM_CR,
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UARTDM_CSR,
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UARTDM_IPR,
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UARTDM_ISR,
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UARTDM_RX_TOTAL_SNAP,
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UARTDM_RFWR,
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UARTDM_TFWR,
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UARTDM_RF,
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UARTDM_TF,
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UARTDM_MISR,
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UARTDM_DMRX,
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UARTDM_NCF_TX,
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UARTDM_DMEN,
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UARTDM_BCR,
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UARTDM_TXFS,
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UARTDM_RXFS,
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UARTDM_LAST,
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};
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enum msm_hs_regs {
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UART_DM_MR1 = 0x0,
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UART_DM_MR2 = 0x4,
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UART_DM_IMR = 0xb0,
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UART_DM_SR = 0xa4,
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UART_DM_CR = 0xa8,
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UART_DM_CSR = 0xa0,
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UART_DM_IPR = 0x18,
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UART_DM_ISR = 0xb4,
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UART_DM_RX_TOTAL_SNAP = 0xbc,
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UART_DM_TFWR = 0x1c,
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UART_DM_RFWR = 0x20,
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UART_DM_RF = 0x140,
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UART_DM_TF = 0x100,
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UART_DM_MISR = 0xac,
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UART_DM_DMRX = 0x34,
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UART_DM_NCF_TX = 0x40,
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UART_DM_DMEN = 0x3c,
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UART_DM_TXFS = 0x4c,
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UART_DM_RXFS = 0x50,
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UART_DM_RX_TRANS_CTRL = 0xcc,
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UART_DM_BCR = 0xc8,
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};
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#define UARTDM_MR1_ADDR 0x0
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#define UARTDM_MR2_ADDR 0x4
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/* Backward Compatibility Register for UARTDM Core v1.4 */
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#define UARTDM_BCR_ADDR 0xc8
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/*
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* UARTDM Core v1.4 STALE_IRQ_EMPTY bit defination
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* Stale interrupt will fire if bit is set when RX-FIFO is empty
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*/
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#define UARTDM_BCR_TX_BREAK_DISABLE 0x1
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#define UARTDM_BCR_STALE_IRQ_EMPTY 0x2
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#define UARTDM_BCR_RX_DMRX_LOW_EN 0x4
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#define UARTDM_BCR_RX_STAL_IRQ_DMRX_EQL 0x10
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#define UARTDM_BCR_RX_DMRX_1BYTE_RES_EN 0x20
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/* TRANSFER_CONTROL Register for UARTDM Core v1.4 */
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#define UARTDM_RX_TRANS_CTRL_ADDR 0xcc
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/* TRANSFER_CONTROL Register bits */
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#define RX_STALE_AUTO_RE_EN 0x1
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#define RX_TRANS_AUTO_RE_ACTIVATE 0x2
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#define RX_DMRX_CYCLIC_EN 0x4
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/* write only register */
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#define UARTDM_CSR_115200 0xFF
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#define UARTDM_CSR_57600 0xEE
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#define UARTDM_CSR_38400 0xDD
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#define UARTDM_CSR_28800 0xCC
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#define UARTDM_CSR_19200 0xBB
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#define UARTDM_CSR_14400 0xAA
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#define UARTDM_CSR_9600 0x99
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#define UARTDM_CSR_7200 0x88
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#define UARTDM_CSR_4800 0x77
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#define UARTDM_CSR_3600 0x66
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#define UARTDM_CSR_2400 0x55
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#define UARTDM_CSR_1200 0x44
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#define UARTDM_CSR_600 0x33
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#define UARTDM_CSR_300 0x22
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#define UARTDM_CSR_150 0x11
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#define UARTDM_CSR_75 0x00
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/* write only register */
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#define UARTDM_IPR_ADDR 0x18
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#define UARTDM_TFWR_ADDR 0x1c
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#define UARTDM_RFWR_ADDR 0x20
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#define UARTDM_HCR_ADDR 0x24
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#define UARTDM_DMRX_ADDR 0x34
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#define UARTDM_DMEN_ADDR 0x3c
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/* UART_DM_NO_CHARS_FOR_TX */
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#define UARTDM_NCF_TX_ADDR 0x40
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#define UARTDM_BADR_ADDR 0x44
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#define UARTDM_SIM_CFG_ADDR 0x80
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/* Read Only register */
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#define UARTDM_TXFS_ADDR 0x4C
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#define UARTDM_RXFS_ADDR 0x50
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/* Register field Mask Mapping */
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#define UARTDM_SR_RX_BREAK_BMSK BIT(6)
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#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
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#define UARTDM_SR_OVERRUN_BMSK BIT(4)
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#define UARTDM_SR_TXEMT_BMSK BIT(3)
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#define UARTDM_SR_TXRDY_BMSK BIT(2)
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#define UARTDM_SR_RXRDY_BMSK BIT(0)
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#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
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#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
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#define UARTDM_CR_TX_EN_BMSK BIT(2)
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#define UARTDM_CR_RX_EN_BMSK BIT(0)
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/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
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#define RESET_RX 0x10
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#define RESET_TX 0x20
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#define RESET_ERROR_STATUS 0x30
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#define RESET_BREAK_INT 0x40
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#define START_BREAK 0x50
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#define STOP_BREAK 0x60
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#define RESET_CTS 0x70
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#define RESET_STALE_INT 0x80
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#define RFR_LOW 0xD0
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#define RFR_HIGH 0xE0
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#define CR_PROTECTION_EN 0x100
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#define STALE_EVENT_ENABLE 0x500
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#define STALE_EVENT_DISABLE 0x600
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#define FORCE_STALE_EVENT 0x400
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#define CLEAR_TX_READY 0x300
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#define RESET_TX_ERROR 0x800
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#define RESET_TX_DONE 0x810
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/*
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* UARTDM_CR BAM IFC comman bit value
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* for UARTDM Core v1.4
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*/
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#define START_RX_BAM_IFC 0x850
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#define START_TX_BAM_IFC 0x860
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#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
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#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
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#define UARTDM_MR1_CTS_CTL_BMSK 0x40
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#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
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/*
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* UARTDM Core v1.4 MR2_RFR_CTS_LOOP bitmask
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* Enables internal loopback between RFR_N of
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* RX channel and CTS_N of TX channel.
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*/
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#define UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK 0x400
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#define UARTDM_MR2_LOOP_MODE_BMSK 0x80
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#define UARTDM_MR2_ERROR_MODE_BMSK 0x40
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#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
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#define UARTDM_MR2_RX_ZERO_CHAR_OFF 0x100
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#define UARTDM_MR2_RX_ERROR_CHAR_OFF 0x200
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#define UARTDM_MR2_RX_BREAK_ZERO_CHAR_OFF 0x100
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#define UARTDM_MR2_BITS_PER_CHAR_8 (0x3 << 4)
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/* bits per character configuration */
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#define FIVE_BPC (0 << 4)
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#define SIX_BPC (1 << 4)
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#define SEVEN_BPC (2 << 4)
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#define EIGHT_BPC (3 << 4)
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#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
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#define STOP_BIT_ONE (1 << 2)
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#define STOP_BIT_TWO (3 << 2)
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#define UARTDM_MR2_PARITY_MODE_BMSK 0x3
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/* Parity configuration */
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#define NO_PARITY 0x0
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#define EVEN_PARITY 0x2
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#define ODD_PARITY 0x1
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#define SPACE_PARITY 0x3
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#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
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#define UARTDM_IPR_STALE_LSB_BMSK 0x1f
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/* These can be used for both ISR and IMR register */
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#define UARTDM_ISR_TX_READY_BMSK BIT(7)
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#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
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#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
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#define UARTDM_ISR_RXLEV_BMSK BIT(4)
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#define UARTDM_ISR_RXSTALE_BMSK BIT(3)
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#define UARTDM_ISR_RXBREAK_BMSK BIT(2)
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#define UARTDM_ISR_RXHUNT_BMSK BIT(1)
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#define UARTDM_ISR_TXLEV_BMSK BIT(0)
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/* Field definitions for UART_DM_DMEN*/
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#define UARTDM_TX_DM_EN_BMSK 0x1
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#define UARTDM_RX_DM_EN_BMSK 0x2
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/*
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* UARTDM Core v1.4 bitmask
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* Bitmasks for enabling Rx and Tx BAM Interface
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*/
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#define UARTDM_TX_BAM_ENABLE_BMSK 0x4
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#define UARTDM_RX_BAM_ENABLE_BMSK 0x8
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/* Register offsets for UART Core v13 */
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/* write only register */
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#define UARTDM_CSR_ADDR 0x8
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/* write only register */
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#define UARTDM_TF_ADDR 0x70
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#define UARTDM_TF2_ADDR 0x74
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#define UARTDM_TF3_ADDR 0x78
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#define UARTDM_TF4_ADDR 0x7c
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/* write only register */
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#define UARTDM_CR_ADDR 0x10
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/* write only register */
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#define UARTDM_IMR_ADDR 0x14
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#define UARTDM_IRDA_ADDR 0x38
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/* Read Only register */
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#define UARTDM_SR_ADDR 0x8
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/* Read Only register */
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#define UARTDM_RF_ADDR 0x70
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#define UARTDM_RF2_ADDR 0x74
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#define UARTDM_RF3_ADDR 0x78
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#define UARTDM_RF4_ADDR 0x7c
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/* Read Only register */
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#define UARTDM_MISR_ADDR 0x10
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/* Read Only register */
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#define UARTDM_ISR_ADDR 0x14
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#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
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#endif /* MSM_SERIAL_HS_HWREG_H */
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55
include/linux/platform_data/msm_serial_hs.h
Normal file
55
include/linux/platform_data/msm_serial_hs.h
Normal file
@@ -0,0 +1,55 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2008 Google, Inc.
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* Copyright (C) 2010-2018, 2020, The Linux Foundation. All rights reserved.
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* Author: Nick Pelly <npelly@google.com>
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*/
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#ifndef __ASM_ARCH_MSM_SERIAL_HS_H
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#define __ASM_ARCH_MSM_SERIAL_HS_H
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#include <linux/serial_core.h>
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/**
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* struct msm_serial_hs_platform_data - platform device data
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* for msm hsuart device
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* @wakeup_irq : IRQ line to be configured as Wakeup source.
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* @inject_rx_on_wakeup : Set 1 if specific character to be inserted on wakeup
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* @rx_to_inject : Character to be inserted on wakeup
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* @gpio_config : Configure gpios that are used for uart communication
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* @userid : User-defined number to be used to enumerate device as tty<userid>
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* @uart_tx_gpio: GPIO number for UART Tx Line.
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* @uart_rx_gpio: GPIO number for UART Rx Line.
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* @uart_cts_gpio: GPIO number for UART CTS Line.
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* @uart_rfr_gpio: GPIO number for UART RFR Line.
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* @bam_tx_ep_pipe_index : BAM TX Endpoint Pipe Index for HSUART
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* @bam_tx_ep_pipe_index : BAM RX Endpoint Pipe Index for HSUART
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* @no_suspend_delay : Flag used to make system go to suspend
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* immediately or not
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* @obs: Flag to enable out of band sleep feature support
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*/
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struct msm_serial_hs_platform_data {
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int wakeup_irq; /* wakeup irq */
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bool inject_rx_on_wakeup;
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u8 rx_to_inject;
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int (*gpio_config)(int gpio_config);
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int userid;
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int uart_tx_gpio;
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int uart_rx_gpio;
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int uart_cts_gpio;
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int uart_rfr_gpio;
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unsigned int bam_tx_ep_pipe_index;
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unsigned int bam_rx_ep_pipe_index;
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bool no_suspend_delay;
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bool obs;
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};
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/* return true when tx is empty */
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unsigned int msm_hs_tx_empty(struct uart_port *uport);
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int msm_hs_request_clock_off(struct uart_port *uport);
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int msm_hs_request_clock_on(struct uart_port *uport);
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struct uart_port *msm_hs_get_uart_port(int port_index);
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void msm_hs_set_mctrl(struct uart_port *uport,
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unsigned int mctrl);
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#endif
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