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Merge "defconfig: enable SMBLITE charger driver"

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This commit is contained in:
qctecmdr
2020-03-24 18:09:46 -07:00
committed by Gerrit - the friendly Code Review server
parent 6ddcea248f 976d7b7b6c
commit d631cf7ddd
10 changed files with 6026 additions and 0 deletions
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1
arch/arm/configs/vendor/bengal-perf_defconfig vendored
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@@ -336,6 +336,7 @@ CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_SMBLITE=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y

1
arch/arm/configs/vendor/bengal_defconfig vendored
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@@ -365,6 +365,7 @@ CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_SMBLITE=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y

1
arch/arm64/configs/vendor/bengal-perf_defconfig vendored
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@@ -384,6 +384,7 @@ CONFIG_POWER_RESET_QCOM=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_SMBLITE=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y

1
arch/arm64/configs/vendor/bengal_defconfig vendored
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@@ -397,6 +397,7 @@ CONFIG_POWER_RESET_QCOM=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_QPNP_SMB5=y
CONFIG_QPNP_SMBLITE=y
CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_QG=y
CONFIG_THERMAL=y

12
drivers/power/supply/qcom/Kconfig
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@@ -15,6 +15,18 @@ config QPNP_SMB5
VBUS and VCONN regulators are registered for supporting OTG,
and powered Type-C cables respectively.
config QPNP_SMBLITE
tristate "SMBLITE Battery Charger"
depends on MFD_SPMI_PMIC
help
Say Y to enables support for the SMBLITE charging peripheral.
The QPNP SMBLITE charger driver supports the charger peripheral
present in the chip.
The power supply framework is used to communicate battery and
usb properties to userspace and other driver consumers such
as fuel gauge and USB.
VBUS regulator is registered for supporting OTG.
config SMB1390_CHARGE_PUMP_PSY
tristate "SMB1390 power supply framework based driver"
depends on MFD_I2C_PMIC

1
drivers/power/supply/qcom/Makefile
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@@ -8,3 +8,4 @@ obj-$(CONFIG_QPNP_FG_GEN4) += qpnp-fg-gen4.o fg-memif.o fg-util.o fg-alg.o pmic
obj-$(CONFIG_QPNP_QG) += qpnp-qg.o pmic-voter.o qg-util.o qg-soc.o qg-sdam.o qg-battery-profile.o qg-profile-lib.o fg-alg.o
obj-$(CONFIG_HL6111R) += hl6111r.o
obj-$(CONFIG_SMB1398_CHARGER) += smb1398-charger.o pmic-voter.o
obj-$(CONFIG_QPNP_SMBLITE) += step-chg-jeita.o battery.o qpnp-smblite.o smblite-lib.o pmic-voter.o storm-watch.o schgm-flash.o

1979
drivers/power/supply/qcom/qpnp-smblite.c Normal file
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File diff suppressed because it is too large Load Diff

3249
drivers/power/supply/qcom/smblite-lib.c Normal file
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File diff suppressed because it is too large Load Diff

469
drivers/power/supply/qcom/smblite-lib.h Normal file
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@@ -0,0 +1,469 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __SMBLITE_LIB_H
#define __SMBLITE_LIB_H
#include <linux/alarmtimer.h>
#include <linux/ktime.h>
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/consumer.h>
#include <linux/extcon-provider.h>
#include <linux/usb/typec.h>
#include "storm-watch.h"
#include "battery.h"
enum print_reason {
PR_INTERRUPT = BIT(0),
PR_REGISTER = BIT(1),
PR_MISC = BIT(2),
PR_PARALLEL = BIT(3),
PR_OTG = BIT(4),
};
#define DEFAULT_VOTER "DEFAULT_VOTER"
#define USER_VOTER "USER_VOTER"
#define USB_PSY_VOTER "USB_PSY_VOTER"
#define USBIN_V_VOTER "USBIN_V_VOTER"
#define THERMAL_DAEMON_VOTER "THERMAL_DAEMON_VOTER"
#define BOOST_BACK_VOTER "BOOST_BACK_VOTER"
#define DEBUG_BOARD_VOTER "DEBUG_BOARD_VOTER"
#define PL_DELAY_VOTER "PL_DELAY_VOTER"
#define SW_ICL_MAX_VOTER "SW_ICL_MAX_VOTER"
#define BATT_PROFILE_VOTER "BATT_PROFILE_VOTER"
#define USBIN_I_VOTER "USBIN_I_VOTER"
#define WEAK_CHARGER_VOTER "WEAK_CHARGER_VOTER"
#define HW_LIMIT_VOTER "HW_LIMIT_VOTER"
#define FORCE_RECHARGE_VOTER "FORCE_RECHARGE_VOTER"
#define FCC_STEPPER_VOTER "FCC_STEPPER_VOTER"
#define SW_THERM_REGULATION_VOTER "SW_THERM_REGULATION_VOTER"
#define JEITA_ARB_VOTER "JEITA_ARB_VOTER"
#define AICL_THRESHOLD_VOTER "AICL_THRESHOLD_VOTER"
#define USB_SUSPEND_VOTER "USB_SUSPEND_VOTER"
#define DETACH_DETECT_VOTER "DETACH_DETECT_VOTER"
#define ICL_CHANGE_VOTER "ICL_CHANGE_VOTER"
#define TYPEC_SWAP_VOTER "TYPEC_SWAP_VOTER"
#define BOOST_BACK_STORM_COUNT 3
#define WEAK_CHG_STORM_COUNT 8
#define VBAT_TO_VRAW_ADC(v) div_u64((u64)v * 1000000UL, 194637UL)
#define ITERM_LIMITS_MA 10000
#define ADC_CHG_ITERM_MASK 32767
#define USBIN_25UA 25000
#define USBIN_100UA 100000
#define USBIN_150UA 150000
#define USBIN_500UA 500000
#define USBIN_900UA 900000
#define CDP_CURRENT_UA 1500000
#define DCP_CURRENT_UA 1500000
#define TYPEC_DEFAULT_CURRENT_UA 900000
#define TYPEC_MEDIUM_CURRENT_UA 1500000
#define TYPEC_HIGH_CURRENT_UA 3000000
#define ROLE_REVERSAL_DELAY_MS 500
enum smb_mode {
PARALLEL_MASTER = 0,
PARALLEL_SLAVE,
NUM_MODES,
};
enum sink_src_mode {
SINK_MODE,
SRC_MODE,
AUDIO_ACCESS_MODE,
UNATTACHED_MODE,
};
enum {
BOOST_BACK_WA = BIT(0),
WEAK_ADAPTER_WA = BIT(1),
};
enum jeita_cfg_stat {
JEITA_CFG_NONE = 0,
JEITA_CFG_FAILURE,
JEITA_CFG_COMPLETE,
};
enum {
RERUN_AICL = 0,
RESTART_AICL,
};
enum smb_irq_index {
/* CHGR */
CHG_STATE_CHANGE_IRQ = 0,
CHGR_ERROR_IRQ,
BUCK_OC_IRQ,
VPH_OV_IRQ,
/* DCDC */
OTG_FAIL_IRQ,
OTG_FAULT_IRQ,
SKIP_MODE_IRQ,
INPUT_CURRENT_LIMITING_IRQ,
SWITCHER_POWER_OK_IRQ,
/* BATIF */
BAT_TEMP_IRQ,
BAT_THERM_OR_ID_MISSING_IRQ,
BAT_LOW_IRQ,
BAT_OV_IRQ,
BSM_ACTIVE_IRQ,
/* USB */
USBIN_PLUGIN_IRQ,
USBIN_COLLAPSE_IRQ,
USBIN_UV_IRQ,
USBIN_OV_IRQ,
USBIN_GT_VT_IRQ,
USBIN_ICL_CHANGE_IRQ,
/* TYPEC */
TYPEC_OR_RID_DETECTION_CHANGE_IRQ,
TYPEC_VPD_DETECT_IRQ,
TYPEC_CC_STATE_CHANGE_IRQ,
TYPEC_VBUS_CHANGE_IRQ,
TYPEC_ATTACH_DETACH_IRQ,
TYPEC_LEGACY_CABLE_DETECT_IRQ,
TYPEC_TRY_SNK_SRC_DETECT_IRQ,
/* MISC */
WDOG_SNARL_IRQ,
WDOG_BARK_IRQ,
AICL_FAIL_IRQ,
AICL_DONE_IRQ,
IMP_TRIGGER_IRQ,
ALL_CHNL_CONV_DONE_IRQ,
TEMP_CHANGE_IRQ,
/* FLASH */
VREG_OK_IRQ,
ILIM_S2_IRQ,
ILIM_S1_IRQ,
VOUT_DOWN_IRQ,
VOUT_UP_IRQ,
FLASH_STATE_CHANGE_IRQ,
TORCH_REQ_IRQ,
FLASH_EN_IRQ,
SDAM_STS_IRQ,
/* END */
SMB_IRQ_MAX,
};
enum chg_term_config_src {
ITERM_SRC_UNSPECIFIED,
ITERM_SRC_ADC,
ITERM_SRC_ANALOG
};
struct smb_irq_info {
const char *name;
const irq_handler_t handler;
const bool wake;
const struct storm_watch storm_data;
struct smb_irq_data *irq_data;
int irq;
bool enabled;
};
static const unsigned int smblite_lib_extcon_cable[] = {
EXTCON_USB,
EXTCON_USB_HOST,
EXTCON_NONE,
};
enum icl_override_mode {
/* APSD/Type-C/QC auto */
HW_AUTO_MODE,
/* 100/150/500/900mA */
SW_OVERRIDE_USB51_MODE,
/* ICL other than USB51 */
SW_OVERRIDE_HC_MODE,
};
/* EXTCON_USB and EXTCON_USB_HOST are mutually exclusive */
static const u32 smblite_lib_extcon_exclusive[] = {0x3, 0};
struct smb_irq_data {
void *parent_data;
const char *name;
struct storm_watch storm_data;
};
struct smb_chg_param {
const char *name;
u16 reg;
int min_u;
int max_u;
int step_u;
int (*get_proc)(struct smb_chg_param *param,
u8 val_raw);
int (*set_proc)(struct smb_chg_param *param,
int val_u,
u8 *val_raw);
};
struct smb_params {
struct smb_chg_param fcc;
struct smb_chg_param fv;
struct smb_chg_param usb_icl;
struct smb_chg_param icl_max_stat;
struct smb_chg_param icl_stat;
struct smb_chg_param aicl_5v_threshold;
};
struct parallel_params {
struct power_supply *psy;
};
struct smb_iio {
struct iio_channel *temp_chan;
struct iio_channel *usbin_v_chan;
};
struct smb_charger {
struct device *dev;
char *name;
struct regmap *regmap;
struct smb_irq_info *irq_info;
struct smb_params param;
struct smb_iio iio;
int *debug_mask;
enum smb_mode mode;
int weak_chg_icl_ua;
/* locks */
struct mutex typec_lock;
/* power supplies */
struct power_supply *batt_psy;
struct power_supply *usb_psy;
struct power_supply *bms_psy;
struct power_supply *usb_main_psy;
enum power_supply_type real_charger_type;
/* notifiers */
struct notifier_block nb;
/* parallel charging */
struct parallel_params pl;
/* typec */
struct typec_port *typec_port;
struct typec_capability typec_caps;
struct typec_partner *typec_partner;
struct typec_partner_desc typec_partner_desc;
/* votables */
struct votable *fcc_votable;
struct votable *fcc_main_votable;
struct votable *fv_votable;
struct votable *usb_icl_votable;
struct votable *awake_votable;
struct votable *pl_disable_votable;
struct votable *chg_disable_votable;
struct votable *pl_enable_votable_indirect;
struct votable *icl_irq_disable_votable;
/* work */
struct work_struct bms_update_work;
struct work_struct pl_update_work;
struct work_struct jeita_update_work;
struct delayed_work icl_change_work;
struct delayed_work pl_enable_work;
struct delayed_work bb_removal_work;
struct delayed_work thermal_regulation_work;
struct delayed_work role_reversal_check;
struct charger_param chg_param;
/* cached status */
int system_temp_level;
int thermal_levels;
int *thermal_mitigation;
int fake_capacity;
int fake_batt_status;
bool step_chg_enabled;
bool typec_legacy_use_rp_icl;
int connector_type;
bool suspend_input_on_debug_batt;
bool fake_chg_status_on_debug_batt;
int typec_mode;
int dr_mode;
int term_vbat_uv;
u32 jeita_status;
bool jeita_arb_flag;
bool typec_legacy;
bool otg_present;
int auto_recharge_soc;
enum sink_src_mode sink_src_mode;
enum power_supply_typec_power_role power_role;
enum jeita_cfg_stat jeita_configured;
bool fcc_stepper_enable;
u32 jeita_soft_thlds[2];
u32 jeita_soft_hys_thlds[2];
int jeita_soft_fcc[2];
int jeita_soft_fv[2];
int aicl_5v_threshold_mv;
int default_aicl_5v_threshold_mv;
bool aicl_max_reached;
bool pr_swap_in_progress;
bool ldo_mode;
/* workaround flag */
u32 wa_flags;
int boost_current_ua;
/* extcon for VBUS / ID notification to USB for uUSB */
struct extcon_dev *extcon;
/* battery profile */
int batt_profile_fcc_ua;
int batt_profile_fv_uv;
/* flash */
u32 flash_derating_soc;
u32 flash_disable_soc;
u32 headroom_mode;
bool flash_init_done;
bool flash_active;
u32 irq_status;
};
int smblite_lib_read(struct smb_charger *chg, u16 addr, u8 *val);
int smblite_lib_masked_write(struct smb_charger *chg, u16 addr, u8 mask,
u8 val);
int smblite_lib_write(struct smb_charger *chg, u16 addr, u8 val);
int smblite_lib_batch_write(struct smb_charger *chg, u16 addr, u8 *val,
int count);
int smblite_lib_batch_read(struct smb_charger *chg, u16 addr, u8 *val,
int count);
int smblite_lib_get_charge_param(struct smb_charger *chg,
struct smb_chg_param *param, int *val_u);
int smblite_lib_get_usb_suspend(struct smb_charger *chg, int *suspend);
int smblite_lib_enable_charging(struct smb_charger *chg, bool enable);
int smblite_lib_set_charge_param(struct smb_charger *chg,
struct smb_chg_param *param, int val_u);
int smblite_lib_set_usb_suspend(struct smb_charger *chg, bool suspend);
irqreturn_t smblite_default_irq_handler(int irq, void *data);
irqreturn_t smblite_chg_state_change_irq_handler(int irq, void *data);
irqreturn_t smblite_batt_temp_changed_irq_handler(int irq, void *data);
irqreturn_t smblite_batt_psy_changed_irq_handler(int irq, void *data);
irqreturn_t smblite_usbin_uv_irq_handler(int irq, void *data);
irqreturn_t smblite_usb_plugin_irq_handler(int irq, void *data);
irqreturn_t smblite_icl_change_irq_handler(int irq, void *data);
irqreturn_t smblite_typec_state_change_irq_handler(int irq, void *data);
irqreturn_t smblite_typec_attach_detach_irq_handler(int irq, void *data);
irqreturn_t smblite_switcher_power_ok_irq_handler(int irq, void *data);
irqreturn_t smblite_wdog_bark_irq_handler(int irq, void *data);
irqreturn_t smblite_typec_or_rid_detection_change_irq_handler(int irq,
void *data);
irqreturn_t smblite_temp_change_irq_handler(int irq, void *data);
irqreturn_t smblite_usbin_ov_irq_handler(int irq, void *data);
int smblite_lib_get_prop_input_suspend(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_batt_present(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_batt_capacity(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_batt_status(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_batt_charge_type(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_batt_charge_done(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_batt_current_now(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_batt_health(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_system_temp_level(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_system_temp_level_max(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_input_current_limited(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_batt_iterm(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_set_prop_input_suspend(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_set_prop_batt_capacity(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_set_prop_batt_status(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_set_prop_system_temp_level(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_get_prop_usb_present(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_usb_online(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_usb_online(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_usb_suspend(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_usb_voltage_now(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_usb_prop_typec_mode(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_typec_cc_orientation(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_scope(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_typec_power_role(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_input_current_settled(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_input_voltage_settled(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_charger_temp(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_prop_die_health(struct smb_charger *chg);
int smblite_lib_get_die_health(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_set_prop_current_max(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_set_prop_typec_power_role(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_set_prop_ship_mode(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_set_prop_rechg_soc_thresh(struct smb_charger *chg,
const union power_supply_propval *val);
void smblite_lib_suspend_on_debug_battery(struct smb_charger *chg);
int smblite_lib_get_prop_fcc_delta(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_get_thermal_threshold(struct smb_charger *chg, u16 addr,
int *val);
int smblite_lib_run_aicl(struct smb_charger *chg, int type);
int smblite_lib_set_icl_current(struct smb_charger *chg, int icl_ua);
int smblite_lib_get_icl_current(struct smb_charger *chg, int *icl_ua);
int smblite_lib_get_charge_current(struct smb_charger *chg,
int *total_current_ua);
int smblite_lib_get_hw_current_max(struct smb_charger *chg,
int *total_current_ua);
int smblite_lib_get_prop_pr_swap_in_progress(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_set_prop_pr_swap_in_progress(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_typec_port_type_set(const struct typec_capability *cap,
enum typec_port_type type);
int smblite_lib_get_prop_from_bms(struct smb_charger *chg,
enum power_supply_property psp,
union power_supply_propval *val);
int smblite_lib_get_iio_channel(struct smb_charger *chg, const char *propname,
struct iio_channel **chan);
int smblite_lib_read_iio_channel(struct smb_charger *chg,
struct iio_channel *chan, int div, int *data);
int smblite_lib_icl_override(struct smb_charger *chg,
enum icl_override_mode mode);
int smblite_lib_get_irq_status(struct smb_charger *chg,
union power_supply_propval *val);
int smblite_lib_set_prop_usb_type(struct smb_charger *chg,
const union power_supply_propval *val);
int smblite_lib_init(struct smb_charger *chg);
int smblite_lib_deinit(struct smb_charger *chg);
#endif /* __SMBLITE_LIB_H */

312
drivers/power/supply/qcom/smblite-reg.h Normal file
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@@ -0,0 +1,312 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __SMBLITE_CHARGER_REG_H
#define __SMBLITE_CHARGER_REG_H
#include <linux/bitops.h>
#define CHGR_BASE 0x1000
#define DCDC_BASE 0x1100
#define BATIF_BASE 0x1200
#define USBIN_BASE 0x1300
#define TYPEC_BASE 0X1500
#define MISC_BASE 0x1600
#define PERPH_TYPE_OFFSET 0x04
#define TYPE_MASK GENMASK(7, 0)
#define PERPH_SUBTYPE_OFFSET 0x05
#define SUBTYPE_MASK GENMASK(7, 0)
#define INT_RT_STS_OFFSET 0x10
/********************************
* CHGR Peripheral Registers *
********************************/
#define BATTERY_CHARGER_STATUS_1_REG (CHGR_BASE + 0x06)
#define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0)
enum {
INHIBIT_CHARGE = 0,
TRICKLE_CHARGE,
PRE_CHARGE,
FULLON_CHARGE,
TAPER_CHARGE,
TERMINATE_CHARGE,
PAUSE_CHARGE,
DISABLE_CHARGE,
};
#define CHARGER_VBAT_STATUS_REG (CHGR_BASE + 0x08)
#define BAT_OV_BIT BIT(7)
#define BATTERY_TEMP_STATUS_REG (BATIF_BASE + 0x0C)
#define BAT_TEMP_STATUS_TOO_HOT_AFP_BIT BIT(5)
#define BAT_TEMP_STATUS_TOO_HOT_BIT BIT(4)
#define BAT_TEMP_STATUS_HOT_SOFT_BIT BIT(3)
#define BAT_TEMP_STATUS_COLD_SOFT_BIT BIT(2)
#define BAT_TEMP_STATUS_TOO_COLD_BIT BIT(1)
#define BAT_TEMP_STATUS_TOO_COLD_AFP_BIT BIT(0)
#define CHARGING_ENABLE_CMD_REG (CHGR_BASE + 0x46)
#define CHARGING_ENABLE_CMD_BIT BIT(0)
#define CHARGING_PAUSE_CMD_BIT BIT(4)
#define CHGR_FAST_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x54)
#define CHGR_FLOAT_VOLTAGE_CFG_REG (CHGR_BASE + 0x58)
#define CHGR_TERM_CFG_REG (CHGR_BASE + 0x60)
#define CHGR_ITERM_USE_ANALOG_BIT BIT(3)
#define CHGR_ADC_ITERM_UP_THD_MSB_REG (CHGR_BASE + 0x64)
#define CHGR_ADC_ITERM_UP_THD_LSB_REG (CHGR_BASE + 0x65)
#define CHGR_ADC_ITERM_LO_THD_MSB_REG (CHGR_BASE + 0x66)
#define CHGR_ADC_ITERM_LO_THD_LSB_REG (CHGR_BASE + 0x67)
#define CHGR_RECHG_CFG_REG (CHGR_BASE + 0x70)
#define RECHG_MASK GENMASK(7, 6)
#define VBAT_BASED_RECHG_BIT BIT(7)
#define SOC_BASED_RECHG_BIT GENMASK(7, 6)
#define NO_OF_SAMPLE_FOR_RCHG GENMASK(1, 0)
#define CHGR_ADC_RECHARGE_THRESHOLD_MSB_REG (CHGR_BASE + 0x72)
#define CHARGE_RCHG_SOC_THRESHOLD_CFG_REG (CHGR_BASE + 0x74)
#define CHGR_INHIBIT_REG (CHGR_BASE + 0x78)
#define CHGR_INHIBIT_BIT BIT(7)
#define CHGR_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x7A)
#define CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG (CHGR_BASE + 0x90)
#define FAST_CHARGE_SAFETY_TIMER_EN_BIT BIT(3)
#define FAST_CHARGE_SAFETY_TIMER_MASK GENMASK(1, 0)
#define FAST_CHARGE_SAFETY_TIMER_192_MIN 0x0
#define FAST_CHARGE_SAFETY_TIMER_384_MIN 0x1
#define FAST_CHARGE_SAFETY_TIMER_768_MIN 0x2
#define FAST_CHARGE_SAFETY_TIMER_1536_MIN 0x3
/********************************
* DCDC Peripheral Registers *
********************************/
#define ICL_MAX_STATUS_REG (DCDC_BASE + 0x06)
#define ICL_STATUS_REG (DCDC_BASE + 0x09)
#define POWER_PATH_STATUS_REG (DCDC_BASE + 0x0B)
#define VALID_INPUT_POWER_SOURCE_STS_BIT BIT(7)
#define USE_USBIN_BIT BIT(5)
#define USBIN_SUSPEND_STS_BIT BIT(3)
#define POWER_PATH_MASK GENMASK(1, 0)
#define DCDC_CMD_OTG_REG (DCDC_BASE + 0x50)
#define OTG_EN_BIT BIT(0)
#define DCDC_OTG_CFG_REG (DCDC_BASE + 0x56)
#define OTG_EN_SRC_CFG_BIT BIT(0)
#define DCDC_LDO_CFG_REG (DCDC_BASE + 0x70)
#define LDO_MODE_BIT BIT(0)
/********************************
* BATIF Peripheral Registers *
********************************/
/* BATIF Interrupt Bits */
#define BSM_ACTIVE_RT_STS_BIT BIT(4)
#define BAT_OV_RT_STS_BIT BIT(3)
#define BAT_LOW_RT_STS_BIT BIT(2)
#define BAT_THERM_OR_ID_MISSING_RT_STS_BIT BIT(1)
#define BAT_TEMP_RT_STS_BIT BIT(0)
#define SHIP_MODE_REG (BATIF_BASE + 0x52)
#define SHIP_MODE_EN_BIT BIT(0)
#define CHGR_JEITA_HOT_THRESHOLD_REG (BATIF_BASE + 0x84)
#define CHGR_JEITA_WARM_THRESHOLD_REG (BATIF_BASE + 0x86)
#define CHGR_JEITA_COOL_THRESHOLD_REG (BATIF_BASE + 0x88)
#define CHGR_JEITA_COLD_THRESHOLD_REG (BATIF_BASE + 0x8A)
/********************************
* USBIN Peripheral Registers *
********************************/
/* USBIN Interrupt Bits */
#define USBIN_SOURCE_CHANGE_RT_STS_BIT BIT(7)
#define USBIN_ICL_CHANGE_RT_STS_BIT BIT(6)
#define USBIN_GT_VT_RT_STS_BIT BIT(4)
#define USBIN_OV_RT_STS_BIT BIT(3)
#define USBIN_UV_RT_STS_BIT BIT(2)
#define USBIN_COLLAPSE_RT_STS_BIT BIT(1)
#define USBIN_PLUGIN_RT_STS_BIT BIT(0)
#define USBIN_ICL_OPTIONS_REG (USBIN_BASE + 0x50)
#define USBIN_MODE_CHG_BIT BIT(2)
#define USB51_MODE_BIT BIT(1)
#define CMD_ICL_OVERRIDE_REG (USBIN_BASE + 0x51)
#define ICL_OVERRIDE_BIT BIT(0)
#define USBIN_CURRENT_LIMIT_CFG_REG (USBIN_BASE + 0x52)
#define USBIN_INPUT_SUSPEND_REG (USBIN_BASE + 0x54)
#define SUSPEND_ON_COLLAPSE_USBIN_BIT BIT(7)
#define USBIN_SUSPEND_BIT BIT(0)
#define USBIN_AICL_OPTIONS_CFG_REG (USBIN_BASE + 0x60)
#define USBIN_AICL_EN_BIT BIT(7)
#define USBIN_AICL_START_AT_MAX BIT(4)
#define USBIN_AICL_STEP_TIMING_SEL_MASK GENMASK(3, 2)
#define USBIN_IN_COLLAPSE_GF_SEL_MASK GENMASK(1, 0)
#define USBIN_LV_AICL_THRESHOLD_REG (USBIN_BASE + 0x63)
#define USB_CMD_PULLDOWN_REG (USBIN_BASE + 0x70)
#define EN_PULLDOWN_USB_IN_BIT BIT(0)
/********************************
* TYPEC Peripheral Registers *
********************************/
#define TYPE_C_SNK_STATUS_REG (TYPEC_BASE + 0x06)
#define DETECTED_SRC_TYPE_MASK GENMASK(6, 0)
#define SNK_DAM_500MA_BIT BIT(6)
#define SNK_DAM_1500MA_BIT BIT(5)
#define SNK_DAM_3000MA_BIT BIT(4)
#define SNK_RP_STD_BIT BIT(3)
#define SNK_RP_1P5_BIT BIT(2)
#define SNK_RP_3P0_BIT BIT(1)
#define SNK_RP_SHORT_BIT BIT(0)
#define TYPE_C_SRC_STATUS_REG (TYPEC_BASE + 0x08)
#define DETECTED_SNK_TYPE_MASK GENMASK(4, 0)
#define SRC_HIGH_BATT_BIT BIT(5)
#define SRC_DEBUG_ACCESS_BIT BIT(4)
#define SRC_RD_OPEN_BIT BIT(3)
#define SRC_RA_OPEN_BIT BIT(1)
#define AUDIO_ACCESS_RA_RA_BIT BIT(0)
#define TYPE_C_STATE_MACHINE_STATUS_REG (TYPEC_BASE + 0x09)
#define TYPEC_ATTACH_DETACH_STATE_BIT BIT(5)
#define TYPE_C_MISC_STATUS_REG (TYPEC_BASE + 0x0B)
#define SNK_SRC_MODE_BIT BIT(6)
#define TYPEC_VBUS_ERROR_STATUS_BIT BIT(4)
#define TYPEC_TCCDEBOUNCE_DONE_STATUS_BIT BIT(3)
#define CC_ORIENTATION_BIT BIT(1)
#define CC_ATTACHED_BIT BIT(0)
#define LEGACY_CABLE_STATUS_REG (TYPEC_BASE + 0x0D)
#define TYPEC_LEGACY_CABLE_STATUS_BIT BIT(1)
#define TYPEC_NONCOMP_LEGACY_CABLE_STATUS_BIT BIT(0)
#define TYPEC_U_USB_STATUS_REG (TYPEC_BASE + 0x0F)
#define U_USB_GROUND_NOVBUS_BIT BIT(6)
#define U_USB_GROUND_BIT BIT(4)
#define U_USB_FLOAT1_BIT BIT(2)
#define U_USB_FLOAT2_BIT BIT(0)
#define TYPE_C_MODE_CFG_REG (TYPEC_BASE + 0x44)
#define TYPEC_TRY_MODE_MASK GENMASK(4, 3)
#define EN_TRY_SNK_BIT BIT(4)
#define EN_TRY_SRC_BIT BIT(3)
#define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0)
#define EN_SRC_ONLY_BIT BIT(2)
#define EN_SNK_ONLY_BIT BIT(1)
#define TYPEC_DISABLE_CMD_BIT BIT(0)
#define DEBUG_ACCESS_SRC_CFG_REG (TYPEC_BASE + 0x4C)
#define EN_UNORIENTED_DEBUG_ACCESS_SRC_BIT BIT(0)
#define TYPE_C_EXIT_STATE_CFG_REG (TYPEC_BASE + 0x50)
#define BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT BIT(3)
#define SEL_SRC_UPPER_REF_BIT BIT(2)
#define EXIT_SNK_BASED_ON_CC_BIT BIT(0)
#define TYPE_C_CURRSRC_CFG_REG (TYPEC_BASE + 0x52)
#define TYPEC_SRC_RP_SEL_MASK GENMASK(1, 0)
enum {
TYPEC_SRC_RP_STD,
TYPEC_SRC_RP_1P5A,
TYPEC_SRC_RP_3A,
TYPEC_SRC_RP_3A_DUPLICATE,
TYPEC_SRC_RP_MAX_ELEMENTS
};
#define TYPE_C_INTERRUPT_EN_CFG_1_REG (TYPEC_BASE + 0x5E)
#define TYPEC_LEGACY_CABLE_INT_EN_BIT BIT(7)
#define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_BIT BIT(6)
#define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT BIT(5)
#define TYPEC_TRYSINK_DETECT_INT_EN_BIT BIT(4)
#define TYPEC_CCOUT_DETACH_INT_EN_BIT BIT(3)
#define TYPEC_CCOUT_ATTACH_INT_EN_BIT BIT(2)
#define TYPEC_VBUS_DEASSERT_INT_EN_BIT BIT(1)
#define TYPEC_VBUS_ASSERT_INT_EN_BIT BIT(0)
#define TYPE_C_INTERRUPT_EN_CFG_2_REG (TYPEC_BASE + 0x60)
#define TYPEC_SRC_BATT_HPWR_INT_EN_BIT BIT(6)
#define MICRO_USB_STATE_CHANGE_INT_EN_BIT BIT(5)
#define TYPEC_STATE_MACHINE_CHANGE_INT_EN_BIT BIT(4)
#define TYPEC_DEBUG_ACCESS_DETECT_INT_EN_BIT BIT(3)
#define TYPEC_WATER_DETECTION_INT_EN_BIT BIT(2)
#define TYPEC_VBUS_ERROR_INT_EN_BIT BIT(1)
#define TYPEC_DEBOUNCE_DONE_INT_EN_BIT BIT(0)
#define TYPEC_U_USB_CFG_REG (TYPEC_BASE + 0x70)
#define EN_MICRO_USB_MODE_BIT BIT(0)
/********************************
* MISC Peripheral Registers *
********************************/
#define TEMP_RANGE_STATUS_REG (MISC_BASE + 0x08)
#define THERM_REG_ACTIVE_BIT BIT(6)
#define TLIM_BIT BIT(5)
#define TEMP_RANGE_MASK GENMASK(4, 1)
#define ALERT_LEVEL_BIT BIT(4)
#define TEMP_ABOVE_RANGE_BIT BIT(3)
#define TEMP_WITHIN_RANGE_BIT BIT(2)
#define TEMP_BELOW_RANGE_BIT BIT(1)
#define THERMREG_DISABLED_BIT BIT(0)
#define DIE_TEMP_STATUS_REG (MISC_BASE + 0x09)
#define DIE_TEMP_SHDN_BIT BIT(3)
#define DIE_TEMP_RST_BIT BIT(2)
#define DIE_TEMP_UB_BIT BIT(1)
#define DIE_TEMP_LB_BIT BIT(0)
#define AICL_STATUS_REG (MISC_BASE + 0x06)
#define SOFT_ILIMIT_BIT BIT(6)
#define AICL_DONE_BIT BIT(0)
#define AICL_CMD_REG (MISC_BASE + 0x50)
#define RESTART_AICL_BIT BIT(1)
#define RERUN_AICL_BIT BIT(0)
#define MISC_SMB_EN_CMD_REG (MISC_BASE + 0x4C)
#define SMB_EN_OVERRIDE_VALUE_BIT BIT(0)
#define SMB_EN_OVERRIDE_BIT BIT(1)
#define MISC_AICL_RERUN_CFG_REG (MISC_BASE + 0x54)
#define USBIN_AICL_PERIODIC_RERUN_EN_BIT BIT(5)
#define USBIN_AICL_RERUN_TIME_MASK GENMASK(1, 0)
#define AICL_RERUN_TIME_12S_VAL 0x01
#define WD_CFG_REG (MISC_BASE + 0x58)
#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7)
#define BARK_WDOG_INT_EN_BIT BIT(4)
#define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1)
#define WDOG_TIMER_EN_BIT BIT(0)
#define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x59)
#define SNARL_WDOG_TIMEOUT_MASK GENMASK(2, 0)
#define SNARL_WDOG_TMOUT_62P5MS 0x0
#define SNARL_WDOG_TMOUT_1S 0x4
#define SNARL_WDOG_TMOUT_8S 0x7
#define BARK_WDOG_TIMEOUT_MASK GENMASK(5, 4)
#define BARK_WDOG_TIMEOUT_SHIFT 4
#define BITE_WDOG_TIMEOUT_MASK GENMASK(7, 6)
#define BITE_WDOG_TIMEOUT_8S 0x3
#define BITE_WDOG_TIMEOUT_SHIFT 6
#define MIN_WD_BARK_TIME 16
#define BARK_BITE_WDOG_PET_REG (MISC_BASE + 0x5A)
#define BARK_BITE_WDOG_PET_BIT BIT(0)
#endif /* __SMBLITE_CHARGER_REG_H */