dt-bindings: Add bindings for ADC5 driver
Add devicetree bindings for ADC5 peripheral driver. Change-Id: I4079ea002a810a4cfc53dcb159a56757af1d3f24 Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
This commit is contained in:
Siddartha Mohanadoss
166
Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5.txt
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166
Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5.txt
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Qualcomm Technologies Inc. SPMI PMIC5 voltage and current ADC
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SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read
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voltage. The ADC is a 15-bit sigma-delta ADC.
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ADC node:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
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Should contain "qcom,spmi-adc-rev2" for PMIC refresh ADC driver.
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- reg:
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Usage: required for VADC base address
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Value type: <prop-encoded-array>
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Definition: VADC base address and length in the SPMI PMIC register map.
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ADC_CAL base address and length in SPMI PMIC register map.
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ADC_CAL base is optional and is dependent on USB_IN_V channel
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read sequence for the PMIC.
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- reg-names
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Usage: required
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Value type: <string>
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Definition: Names associated with base addresses. should be
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"adc5-usr-base", "adc5-cal-base".
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- #address-cells:
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Usage: required
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Value type: <u32>
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Definition: Must be one. Child node 'reg' property should define ADC
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channel number.
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- #size-cells:
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Usage: required
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Value type: <u32>
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Definition: Must be zero.
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- #io-channel-cells:
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Usage: required
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Value type: <u32>
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Definition: Must be one. For details about IIO bindings see:
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Documentation/devicetree/bindings/iio/iio-bindings.txt
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- interrupts:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: End of conversion interrupt.
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- qcom,pmic-revid:
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Usage: optional
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Value type:<u32>
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Definition: phandle pointing to the revision peripheral node. Use it to query the
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PMIC type and revision.
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Channel node properties:
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- reg:
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Usage: required
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Value type: <u32>
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Definition: ADC channel number.
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See include/dt-bindings/iio/qcom,spmi-vadc.h
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- label:
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Usage: required
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Value type: <empty>
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Definition: ADC datasheet channel name.
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For thermistor inputs connected to generic AMUX or GPIO inputs
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these can vary across platform for the same pins. Hence select
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the datasheet name for this channel.
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- qcom,pre-scaling:
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Usage: required
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Value type: <u32 array>
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Definition: Used for scaling the channel input signal before the signal is
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fed to VADC. The configuration for this node is to know the
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pre-determined ratio and use it for post scaling. Select one from
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the following options.
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<1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>
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If property is not found default value depending on chip will be used.
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- qcom,decimation:
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Usage: optional
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Value type: <u32>
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Definition: This parameter is used to decrease ADC sampling rate.
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Quicker measurements can be made by reducing decimation ratio.
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For PMIC5 ADC, combined two step decimation values are 250, 420 and 840.
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If property is not found, default value of 840 will be used.
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For PMIC refresh ADC, supported decimation values are 256, 512, 1024.
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If property is not found, default value of 1024 will be used.
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- qcom,ratiometric:
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Usage: optional
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Value type: <empty>
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Definition: Channel calibration type. If this property is specified
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VADC will use the VDD reference (1.875V) and GND for channel
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calibration. If property is not found, channel will be
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calibrated with 0V and 1.25V reference channels, also
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known as absolute calibration.
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- qcom,hw-settle-time:
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Usage: optional
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Value type: <u32>
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Definition: Time between AMUX getting configured and the ADC starting
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conversion.
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For PMIC5, delay = 15us for value 0,
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100us * (value) for values 0 < value < 11, and
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2ms * (value - 10) otherwise.
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Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800,
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900 us and 1, 2, 4, 6, 8, 10 ms
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If property is not found, channel will use 15us.
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For PMIC rev2, delay = 100us * (value) for values 0 < value < 11, and
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2ms * (value - 10) otherwise.
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Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
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900 us and 1, 2, 4, 6, 8, 10 ms
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If property is not found, channel will use 0 us.
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- qcom,avg-samples:
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Usage: optional
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Value type: <u32>
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Definition: Number of samples to be used for measurement.
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Averaging provides the option to obtain a single measurement
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from the ADC that is an average of multiple samples. The value
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selected is 2^(value).
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Valid values are: 1, 2, 4, 8, 16
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If property is not found, 1 sample will be used.
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- qcom,lut-index:
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Usage: optional
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Value type: <u32>
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Definition: Lookup table index (only for bat_therm channels).
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A bat_therm channel (for 30k, 100k or 400k pull-up resistance)
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requires a voltage-temperature look-up table which depends on the target.
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The LUT to be used for a channel is selected from a table of LUTs
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for that particular channel.
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If property is not found, a default LUT is used for that channel,
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corresponding to index 0.
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Example:
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/* VADC node */
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pmic_vadc: vadc@3100 {
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compatible = "qcom,spmi-adc5";
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reg = <0x3100 0x100>;
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interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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/* Channel node */
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vph_pwr {
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reg = <ADC_VPH_PWR>;
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label = "vph_pwr";
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qcom,decimation = <840>;
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qcom,hw-settle-time = <0>;
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qcom,avg-samples = <1>;
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qcom,pre-scaling = <1 3>;
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};
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};
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/* IIO client node */
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usb {
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io-channels = <&pmic_vadc ADC_VPH_PWR>;
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io-channel-names = "vadc";
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};
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@@ -1,16 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* Copyright (c) 2012-2014,2018-2019 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
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#define _DT_BINDINGS_QCOM_SPMI_VADC_H
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@@ -116,4 +109,117 @@
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#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
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#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
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/* ADC channels for SPMI VADC5*/
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#define ADC_REF_GND 0x00
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#define ADC_1P25VREF 0x01
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#define ADC_VREF_VADC 0x02
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#define ADC_VREF_VADC_DIV_3 0x82
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#define ADC_VPH_PWR 0x83
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#define ADC_VBAT_SNS 0x84
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#define ADC_VCOIN 0x85
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#define ADC_DIE_TEMP 0x06
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#define ADC_USB_IN_I 0x07
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#define ADC_USB_IN_V_16 0x08
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#define ADC_CHG_TEMP 0x09
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#define ADC_BAT_THERM 0x0a
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#define ADC_BAT_ID 0x0b
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#define ADC_XO_THERM 0x0c
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#define ADC_AMUX_THM1 0x0d
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#define ADC_AMUX_THM2 0x0e
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#define ADC_AMUX_THM3 0x0f
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#define ADC_AMUX_THM4 0x10
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#define ADC_AMUX_THM5 0x11
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#define ADC_GPIO1 0x12
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#define ADC_GPIO2 0x13
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#define ADC_GPIO3 0x14
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#define ADC_GPIO4 0x15
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#define ADC_GPIO5 0x16
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#define ADC_GPIO6 0x17
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#define ADC_GPIO7 0x18
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#define ADC_SBUx 0x99
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#define ADC_MID_CHG_DIV6 0x1e
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#define ADC_OFF 0xff
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/* 30k pull-up1 */
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#define ADC_BAT_THERM_PU1 0x2a
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#define ADC_BAT_ID_PU1 0x2b
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#define ADC_XO_THERM_PU1 0x2c
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#define ADC_AMUX_THM1_PU1 0x2d
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#define ADC_AMUX_THM2_PU1 0x2e
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#define ADC_AMUX_THM3_PU1 0x2f
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#define ADC_AMUX_THM4_PU1 0x30
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#define ADC_AMUX_THM5_PU1 0x31
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#define ADC_GPIO1_PU1 0x32
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#define ADC_GPIO2_PU1 0x33
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#define ADC_GPIO3_PU1 0x34
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#define ADC_GPIO4_PU1 0x35
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#define ADC_GPIO5_PU1 0x36
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#define ADC_GPIO6_PU1 0x37
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#define ADC_GPIO7_PU1 0x38
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#define ADC_SBUx_PU1 0x39
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/* 100k pull-up2 */
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#define ADC_BAT_THERM_PU2 0x4a
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#define ADC_BAT_ID_PU2 0x4b
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#define ADC_XO_THERM_PU2 0x4c
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#define ADC_AMUX_THM1_PU2 0x4d
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#define ADC_AMUX_THM2_PU2 0x4e
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#define ADC_AMUX_THM3_PU2 0x4f
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#define ADC_AMUX_THM4_PU2 0x50
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#define ADC_AMUX_THM5_PU2 0x51
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#define ADC_GPIO1_PU2 0x52
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#define ADC_GPIO2_PU2 0x53
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#define ADC_GPIO3_PU2 0x54
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#define ADC_GPIO4_PU2 0x55
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#define ADC_GPIO5_PU2 0x56
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#define ADC_GPIO6_PU2 0x57
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#define ADC_GPIO7_PU2 0x58
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#define ADC_SBUx_PU2 0x59
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/* 400k pull-up3 */
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#define ADC_BAT_THERM_PU3 0x6a
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#define ADC_BAT_ID_PU3 0x6b
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#define ADC_XO_THERM_PU3 0x6c
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#define ADC_AMUX_THM1_PU3 0x6d
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#define ADC_AMUX_THM2_PU3 0x6e
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#define ADC_AMUX_THM3_PU3 0x6f
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#define ADC_AMUX_THM4_PU3 0x70
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#define ADC_AMUX_THM5_PU3 0x71
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#define ADC_GPIO1_PU3 0x72
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#define ADC_GPIO2_PU3 0x73
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#define ADC_GPIO3_PU3 0x74
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#define ADC_GPIO4_PU3 0x75
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#define ADC_GPIO5_PU3 0x76
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#define ADC_GPIO6_PU3 0x77
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#define ADC_GPIO7_PU3 0x78
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#define ADC_SBUx_PU3 0x79
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/* 1/3 Divider */
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#define ADC_GPIO1_DIV3 0x92
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#define ADC_GPIO2_DIV3 0x93
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#define ADC_GPIO3_DIV3 0x94
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#define ADC_GPIO4_DIV3 0x95
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#define ADC_GPIO5_DIV3 0x96
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#define ADC_GPIO6_DIV3 0x97
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#define ADC_GPIO7_DIV3 0x98
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#define ADC_SBUx_DIV3 0x99
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/* Current and combined current/voltage channels */
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#define ADC_INT_EXT_ISENSE 0xa1
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#define ADC_PARALLEL_ISENSE 0xa5
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#define ADC_CUR_REPLICA_VDS 0xa7
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#define ADC_CUR_SENS_BATFET_VDS_OFFSET 0xa9
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#define ADC_CUR_SENS_REPLICA_VDS_OFFSET 0xab
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#define ADC_EXT_SENS_OFFSET 0xad
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#define ADC_INT_EXT_ISENSE_VBAT_VDATA 0xb0
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#define ADC_INT_EXT_ISENSE_VBAT_IDATA 0xb1
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#define ADC_EXT_ISENSE_VBAT_VDATA 0xb2
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#define ADC_EXT_ISENSE_VBAT_IDATA 0xb3
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#define ADC_PARALLEL_ISENSE_VBAT_VDATA 0xb4
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#define ADC_PARALLEL_ISENSE_VBAT_IDATA 0xb5
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#define ADC_MAX_CHANNEL 0xc0
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#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
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