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techpack: audio: Import Xiaomi changes

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* From dagu-s-oss
* Run clang-format on source files

Change-Id: I04f86a89df0d3af0ecb3eecd7ec75fa522d44506
This commit is contained in:
Sebastiano Barezzi
2022-11-22 01:11:29 +01:00
committed by Sebastiano Barezzi
parent 6b9e4a0d18
commit ac3d5527dd
186 changed files with 124226 additions and 1137 deletions
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8
techpack/audio/Makefile
View File

@@ -37,8 +37,16 @@ USERINCLUDE += \
# Needed to be compatible with the O= option
LINUXINCLUDE += \
-I$(srctree)/techpack/audio/include/uapi \
-I$(srctree)/techpack/audio/include/elliptic \
-I$(srctree)/techpack/audio/include
#for mius start
ifeq ($(CONFIG_US_PROXIMITY), y)
LINUXINCLUDE += \
-I$(srctree)/techpack/audio/include/mius
endif
#for mius end
ifeq ($(CONFIG_ARCH_SDXPOORWILLS), y)
LINUXINCLUDE += \
-include $(srctree)/techpack/audio/config/sdxpoorwillsautoconf.h

6
techpack/audio/asoc/Kbuild
View File

@@ -224,6 +224,12 @@ CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-Werror\
-D__linux__
ifeq (y, $(filter y,\
$(CONFIG_MACH_XIAOMI_LMI) \
$(CONFIG_MACH_XIAOMI_MUNCH)))
CDEFINES += -DTFA_ADSP_SUPPORTED
endif
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile

11
techpack/audio/asoc/codecs/Kbuild
View File

@@ -231,6 +231,17 @@ ifeq ($(KERNEL_BUILD), 1)
obj-y += wcd937x/
obj-y += wcd938x/
obj-y += bolero/
ifeq (y, $(filter y, \
$(CONFIG_MACH_XIAOMI_DAGU) \
$(CONFIG_MACH_XIAOMI_ELISH) \
$(CONFIG_MACH_XIAOMI_ENUMA)))
obj-y += cs35l41_k81/
else ifeq ($(CONFIG_MACH_XIAOMI_MUNCH), y)
obj-y += tfa9874/
else
obj-y += cs35l41/
obj-y += tfa98xx/
endif
obj-y += rouleur/
obj-y += wsa883x/
obj-y += sdm660_cdc/

2
techpack/audio/asoc/codecs/bolero/bolero-cdc-regmap.c
View File

@@ -274,7 +274,7 @@ static const struct reg_default bolero_defaults[] = {
{ BOLERO_CDC_RX_RX0_RX_PATH_CFG2, 0x8F},
{ BOLERO_CDC_RX_RX0_RX_PATH_CFG3, 0x00},
{ BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0x00},
{ BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04},
{ BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x05},
{ BOLERO_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E},
{ BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00},
{ BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x08},

2
techpack/audio/asoc/codecs/bolero/bolero-cdc.c
View File

@@ -1379,6 +1379,7 @@ static int bolero_probe(struct platform_device *pdev)
mutex_init(&priv->vote_lock);
INIT_WORK(&priv->bolero_add_child_devices_work,
bolero_add_child_devices);
schedule_work(&priv->bolero_add_child_devices_work);
/* Register LPASS core hw vote */
lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");
@@ -1402,7 +1403,6 @@ static int bolero_probe(struct platform_device *pdev)
}
priv->lpass_audio_hw_vote = lpass_audio_hw_vote;
schedule_work(&priv->bolero_add_child_devices_work);
return 0;
}

5
techpack/audio/asoc/codecs/bolero/bolero-cdc.h
View File

@@ -127,7 +127,12 @@ int bolero_tx_mclk_enable(struct snd_soc_component *c, bool enable);
int bolero_get_version(struct device *dev);
int bolero_dmic_clk_enable(struct snd_soc_component *component,
u32 dmic, u32 tx_mode, bool enable);
void bolero_tx_macro_mute_hs(void);
#else
static inline void bolero_tx_macro_mute_hs(void)
{
}
static inline int bolero_register_res_clk(struct device *dev, rsc_clk_cb_t cb)
{
return 0;

28
techpack/audio/asoc/codecs/bolero/rx-macro.c
View File

@@ -350,7 +350,6 @@ struct rx_macro_bcl_pmic_params {
u8 ppid;
};
static int rx_macro_core_vote(void *handle, bool enable);
static int rx_macro_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai);
@@ -1231,12 +1230,10 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv,
if (rx_priv->rx_mclk_users == 0) {
if (rx_priv->is_native_on)
rx_priv->clk_id = RX_CORE_CLK;
rx_macro_core_vote(rx_priv, true);
ret = bolero_clk_rsc_request_clock(rx_priv->dev,
rx_priv->default_clk_id,
rx_priv->clk_id,
true);
rx_macro_core_vote(rx_priv, false);
if (ret < 0) {
dev_err(rx_priv->dev,
"%s: rx request clock enable failed\n",
@@ -1286,12 +1283,10 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv,
0x01, 0x00);
bolero_clk_rsc_fs_gen_request(rx_priv->dev,
false);
rx_macro_core_vote(rx_priv, true);
bolero_clk_rsc_request_clock(rx_priv->dev,
rx_priv->default_clk_id,
rx_priv->clk_id,
false);
rx_macro_core_vote(rx_priv, false);
rx_priv->clk_id = rx_priv->default_clk_id;
}
}
@@ -1401,21 +1396,18 @@ static int rx_macro_event_handler(struct snd_soc_component *component,
}
break;
case BOLERO_MACRO_EVT_PRE_SSR_UP:
rx_macro_core_vote(rx_priv, true);
/* enable&disable RX_CORE_CLK to reset GFMUX reg */
ret = bolero_clk_rsc_request_clock(rx_priv->dev,
rx_priv->default_clk_id,
RX_CORE_CLK, true);
if (ret < 0) {
if (ret < 0)
dev_err_ratelimited(rx_priv->dev,
"%s, failed to enable clk, ret:%d\n",
__func__, ret);
} else {
else
bolero_clk_rsc_request_clock(rx_priv->dev,
rx_priv->default_clk_id,
RX_CORE_CLK, false);
}
rx_macro_core_vote(rx_priv, false);
break;
case BOLERO_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
@@ -1782,6 +1774,7 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
(comp * RX_MACRO_COMP_OFFSET);
rx_path_cfg0_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0 +
(comp * RX_MACRO_RX_PATH_OFFSET);
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Enable Compander Clock */
snd_soc_component_update_bits(component, comp_ctl0_reg,
@@ -3680,25 +3673,22 @@ static const struct snd_soc_dapm_route rx_audio_map[] = {
static int rx_macro_core_vote(void *handle, bool enable)
{
int rc = 0;
struct rx_macro_priv *rx_priv = (struct rx_macro_priv *) handle;
if (rx_priv == NULL) {
pr_err("%s: rx priv data is NULL\n", __func__);
return -EINVAL;
}
if (enable) {
pm_runtime_get_sync(rx_priv->dev);
if (bolero_check_core_votes(rx_priv->dev))
rc = 0;
else
rc = -ENOTSYNC;
} else {
pm_runtime_put_autosuspend(rx_priv->dev);
pm_runtime_mark_last_busy(rx_priv->dev);
}
return rc;
if (bolero_check_core_votes(rx_priv->dev))
return 0;
else
return -EINVAL;
}
static int rx_swrm_clock(void *handle, bool enable)
@@ -4176,12 +4166,12 @@ static int rx_macro_probe(struct platform_device *pdev)
"%s: register macro failed\n", __func__);
goto err_reg_macro;
}
schedule_work(&rx_priv->rx_macro_add_child_devices_work);
pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_suspend_ignore_children(&pdev->dev, true);
pm_runtime_enable(&pdev->dev);
schedule_work(&rx_priv->rx_macro_add_child_devices_work);
return 0;

93
techpack/audio/asoc/codecs/bolero/tx-macro.c
View File

@@ -45,10 +45,17 @@
#define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
#define TX_MACRO_DMIC_HPF_DELAY_MS 300
#define TX_MACRO_DMIC_HPF_DELAY_MS 100
#if defined(CONFIG_MACH_XIAOMI_PSYCHE) || defined(CONFIG_MACH_XIAOMI_MUNCH)
#define TX_MACRO_AMIC_HPF_DELAY_MS 300
#else
#define TX_MACRO_AMIC_HPF_DELAY_MS 100
#endif
static int tx_unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
struct tx_macro_priv *g_tx_priv;
module_param(tx_unmute_delay, int, 0664);
MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path");
@@ -158,7 +165,9 @@ struct tx_macro_priv {
struct work_struct tx_macro_add_child_devices_work;
struct hpf_work tx_hpf_work[NUM_DECIMATORS];
struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
struct delayed_work tx_hs_unmute_dwork;
u16 dmic_clk_div;
u16 reg_before_mute;
u32 version;
u32 is_used_tx_swr_gpio;
unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
@@ -560,6 +569,21 @@ static void tx_macro_mute_update_callback(struct work_struct *work)
dev_dbg(tx_priv->dev, "%s: decimator %u unmute\n",
__func__, decimator);
}
static void tx_macro_hs_unmute_dwork(struct work_struct *work)
{
struct snd_soc_component *component = NULL;
struct tx_macro_priv *tx_priv = NULL;
struct delayed_work *delayed_work = NULL;
u16 reg_val = 0;
delayed_work = to_delayed_work(work);
tx_priv = container_of(delayed_work, struct tx_macro_priv, tx_hs_unmute_dwork);
component = tx_priv->component;
snd_soc_component_update_bits(component, BOLERO_CDC_TX0_TX_VOL_CTL,
0xff, tx_priv->reg_before_mute);
reg_val = snd_soc_component_read32(component, BOLERO_CDC_TX0_TX_VOL_CTL);
dev_info(tx_priv->dev, "%s: the reg value after unmute is: %#x \n", __func__, reg_val);
}
static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
@@ -915,6 +939,35 @@ static int tx_macro_enable_dmic(struct snd_soc_dapm_widget *w,
return 0;
}
void bolero_tx_macro_mute_hs(void)
{
struct snd_soc_component *component = NULL;
u16 reg_val = 0;
int tx_unmute_delay = 1200;
if (!g_tx_priv)
return;
component = g_tx_priv->component;
if (delayed_work_pending(&g_tx_priv->tx_hs_unmute_dwork)) {
dev_err(component->dev, "%s: there is already a work, give up unmute\n",
__func__);
return;
}
g_tx_priv->reg_before_mute = snd_soc_component_read32(component, BOLERO_CDC_TX0_TX_VOL_CTL);
dev_info(component->dev, "%s: the reg value before mute is: %#x \n",
__func__, g_tx_priv->reg_before_mute);
snd_soc_component_update_bits(component, BOLERO_CDC_TX0_TX_VOL_CTL, 0xff, 0xac);
reg_val = snd_soc_component_read32(component, BOLERO_CDC_TX0_TX_VOL_CTL);
dev_info(component->dev, "%s: the reg value after mute is: %#x \n",
__func__, reg_val);
schedule_delayed_work(&g_tx_priv->tx_hs_unmute_dwork,
msecs_to_jiffies(tx_unmute_delay));
return;
}
EXPORT_SYMBOL(bolero_tx_macro_mute_hs);
static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
@@ -1016,9 +1069,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
msecs_to_jiffies(tx_unmute_delay));
if (tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq !=
CF_MIN_3DB_150HZ) {
#if defined(CONFIG_MACH_XIAOMI_PSYCHE) || defined(CONFIG_MACH_XIAOMI_MUNCH)
queue_delayed_work(system_freezable_wq,
&tx_priv->tx_hpf_work[decimator].dwork,
msecs_to_jiffies(hpf_delay));
#else
queue_delayed_work(system_freezable_wq,
&tx_priv->tx_hpf_work[decimator].dwork,
msecs_to_jiffies(100));
#endif
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x02);
if (!is_amic_enabled(component, decimator))
@@ -1035,7 +1094,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
snd_soc_component_write(component, tx_gain_ctl_reg,
snd_soc_component_read32(component,
tx_gain_ctl_reg));
if (tx_priv->bcs_enable) {
if (tx_priv->bcs_enable && decimator == 0) {
snd_soc_component_update_bits(component, dec_cfg_reg,
0x01, 0x01);
tx_priv->bcs_clk_en = true;
@@ -1086,7 +1145,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
dec_cfg_reg, 0x06, 0x00);
snd_soc_component_update_bits(component, tx_vol_ctl_reg,
0x10, 0x00);
if (tx_priv->bcs_enable) {
if (tx_priv->bcs_enable && decimator == 0) {
snd_soc_component_update_bits(component, dec_cfg_reg,
0x01, 0x00);
snd_soc_component_update_bits(component,
@@ -2445,7 +2504,11 @@ static int tx_macro_register_event_listener(struct snd_soc_component *component,
ret = swrm_wcd_notify(
tx_priv->swr_ctrl_data[0].tx_swr_pdev,
SWR_REGISTER_WAKEUP, NULL);
msm_cdc_pinctrl_set_wakeup_capable(
tx_priv->tx_swr_gpio_p, false);
} else {
msm_cdc_pinctrl_set_wakeup_capable(
tx_priv->tx_swr_gpio_p, true);
ret = swrm_wcd_notify(
tx_priv->swr_ctrl_data[0].tx_swr_pdev,
SWR_DEREGISTER_WAKEUP, NULL);
@@ -2480,8 +2543,6 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv,
__func__);
goto exit;
}
msm_cdc_pinctrl_set_wakeup_capable(
tx_priv->tx_swr_gpio_p, false);
}
clk_tx_ret = bolero_clk_rsc_request_clock(tx_priv->dev,
@@ -2610,8 +2671,6 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv,
TX_CORE_CLK,
false);
if (tx_priv->swr_clk_users == 0) {
msm_cdc_pinctrl_set_wakeup_capable(
tx_priv->tx_swr_gpio_p, true);
ret = msm_cdc_pinctrl_select_sleep_state(
tx_priv->tx_swr_gpio_p);
if (ret < 0) {
@@ -2678,25 +2737,22 @@ static int tx_macro_clk_switch(struct snd_soc_component *component, int clk_src)
static int tx_macro_core_vote(void *handle, bool enable)
{
int rc = 0;
struct tx_macro_priv *tx_priv = (struct tx_macro_priv *) handle;
if (tx_priv == NULL) {
pr_err("%s: tx priv data is NULL\n", __func__);
return -EINVAL;
}
if (enable) {
pm_runtime_get_sync(tx_priv->dev);
if (bolero_check_core_votes(tx_priv->dev))
rc = 0;
else
rc = -ENOTSYNC;
} else {
pm_runtime_put_autosuspend(tx_priv->dev);
pm_runtime_mark_last_busy(tx_priv->dev);
}
return rc;
if (bolero_check_core_votes(tx_priv->dev))
return 0;
else
return -EINVAL;
}
static int tx_macro_swrm_clock(void *handle, bool enable)
@@ -3004,6 +3060,7 @@ static int tx_macro_init(struct snd_soc_component *component)
INIT_DELAYED_WORK(&tx_priv->tx_mute_dwork[i].dwork,
tx_macro_mute_update_callback);
}
INIT_DELAYED_WORK(&tx_priv->tx_hs_unmute_dwork, tx_macro_hs_unmute_dwork);
tx_priv->component = component;
for (i = 0; i < ARRAY_SIZE(tx_macro_reg_init); i++)
@@ -3205,7 +3262,7 @@ static int tx_macro_probe(struct platform_device *pdev)
if (!tx_priv)
return -ENOMEM;
platform_set_drvdata(pdev, tx_priv);
g_tx_priv = tx_priv;
tx_priv->dev = &pdev->dev;
ret = of_property_read_u32(pdev->dev.of_node, "reg",
&tx_base_addr);
@@ -3283,13 +3340,13 @@ static int tx_macro_probe(struct platform_device *pdev)
"%s: register macro failed\n", __func__);
goto err_reg_macro;
}
if (is_used_tx_swr_gpio)
schedule_work(&tx_priv->tx_macro_add_child_devices_work);
pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_suspend_ignore_children(&pdev->dev, true);
pm_runtime_enable(&pdev->dev);
if (is_used_tx_swr_gpio)
schedule_work(&tx_priv->tx_macro_add_child_devices_work);
return 0;
err_reg_macro:

37
techpack/audio/asoc/codecs/bolero/va-macro.c
View File

@@ -388,6 +388,9 @@ static int va_macro_swr_pwr_event_v2(struct snd_soc_dapm_widget *w,
dev_dbg(va_dev, "%s: event = %d, lpi_enable = %d\n",
__func__, event, va_priv->lpi_enable);
if (!va_priv->lpi_enable)
return ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (va_priv->swr_ctrl_data) {
@@ -399,8 +402,12 @@ static int va_macro_swr_pwr_event_v2(struct snd_soc_dapm_widget *w,
dev_dbg(va_dev, "%s: clock switch failed\n",
__func__);
}
msm_cdc_pinctrl_set_wakeup_capable(
va_priv->va_swr_gpio_p, false);
break;
case SND_SOC_DAPM_POST_PMD:
msm_cdc_pinctrl_set_wakeup_capable(
va_priv->va_swr_gpio_p, true);
if (va_priv->swr_ctrl_data) {
clk_src = CLK_SRC_TX_RCG;
ret = swrm_wcd_notify(
@@ -434,6 +441,9 @@ static int va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w,
dev_dbg(va_dev, "%s: event = %d, lpi_enable = %d\n",
__func__, event, va_priv->lpi_enable);
if (!va_priv->lpi_enable)
return ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (va_priv->lpass_audio_hw_vote) {
@@ -553,12 +563,9 @@ static int va_macro_tx_va_mclk_enable(struct va_macro_priv *va_priv,
(enable ? "enable" : "disable"), va_priv->va_mclk_users);
if (enable) {
if (va_priv->swr_clk_users == 0) {
if (va_priv->swr_clk_users == 0)
msm_cdc_pinctrl_select_active_state(
va_priv->va_swr_gpio_p);
msm_cdc_pinctrl_set_wakeup_capable(
va_priv->va_swr_gpio_p, false);
}
clk_tx_ret = bolero_clk_rsc_request_clock(va_priv->dev,
TX_CORE_CLK,
TX_CORE_CLK,
@@ -651,12 +658,9 @@ static int va_macro_tx_va_mclk_enable(struct va_macro_priv *va_priv,
TX_CORE_CLK,
TX_CORE_CLK,
false);
if (va_priv->swr_clk_users == 0) {
msm_cdc_pinctrl_set_wakeup_capable(
va_priv->va_swr_gpio_p, true);
if (va_priv->swr_clk_users == 0)
msm_cdc_pinctrl_select_sleep_state(
va_priv->va_swr_gpio_p);
}
}
return 0;
@@ -671,25 +675,22 @@ static int va_macro_tx_va_mclk_enable(struct va_macro_priv *va_priv,
static int va_macro_core_vote(void *handle, bool enable)
{
int rc = 0;
struct va_macro_priv *va_priv = (struct va_macro_priv *) handle;
if (va_priv == NULL) {
pr_err("%s: va priv data is NULL\n", __func__);
return -EINVAL;
}
if (enable) {
pm_runtime_get_sync(va_priv->dev);
if (bolero_check_core_votes(va_priv->dev))
rc = 0;
else
rc = -ENOTSYNC;
} else {
pm_runtime_put_autosuspend(va_priv->dev);
pm_runtime_mark_last_busy(va_priv->dev);
}
return rc;
if (bolero_check_core_votes(va_priv->dev))
return 0;
else
return -EINVAL;
}
static int va_macro_swrm_clock(void *handle, bool enable)
@@ -3146,13 +3147,13 @@ static int va_macro_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "%s: register macro failed\n", __func__);
goto reg_macro_fail;
}
if (is_used_va_swr_gpio)
schedule_work(&va_priv->va_macro_add_child_devices_work);
pm_runtime_set_autosuspend_delay(&pdev->dev, VA_AUTO_SUSPEND_DELAY);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_suspend_ignore_children(&pdev->dev, true);
pm_runtime_enable(&pdev->dev);
if (is_used_va_swr_gpio)
schedule_work(&va_priv->va_macro_add_child_devices_work);
return ret;
reg_macro_fail:

29
techpack/audio/asoc/codecs/bolero/wsa-macro.c
View File

@@ -445,8 +445,8 @@ static struct snd_soc_dai_driver wsa_macro_dai[] = {
static const struct wsa_macro_reg_mask_val wsa_macro_spkr_default[] = {
{BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80},
{BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80},
{BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x1F, 0x19},
{BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x1F, 0x19},
{BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01},
{BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01},
{BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58},
{BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58},
};
@@ -454,8 +454,8 @@ static const struct wsa_macro_reg_mask_val wsa_macro_spkr_default[] = {
static const struct wsa_macro_reg_mask_val wsa_macro_spkr_mode1[] = {
{BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00},
{BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00},
{BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x1F, 0x18},
{BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x1F, 0x18},
{BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00},
{BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00},
{BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44},
{BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44},
};
@@ -2744,10 +2744,10 @@ static const struct snd_soc_dapm_route wsa_audio_map[] = {
static const struct wsa_macro_reg_mask_val wsa_macro_reg_init[] = {
{BOLERO_CDC_WSA_BOOST0_BOOST_CFG1, 0x3F, 0x12},
{BOLERO_CDC_WSA_BOOST0_BOOST_CFG2, 0x1C, 0x08},
{BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x1E, 0x0C},
{BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x1E, 0x18},
{BOLERO_CDC_WSA_BOOST1_BOOST_CFG1, 0x3F, 0x12},
{BOLERO_CDC_WSA_BOOST1_BOOST_CFG2, 0x1C, 0x08},
{BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x1E, 0x0C},
{BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x1E, 0x18},
{BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0x70, 0x58},
{BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0x70, 0x58},
{BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x08, 0x08},
@@ -2758,6 +2758,8 @@ static const struct wsa_macro_reg_mask_val wsa_macro_reg_init[] = {
{BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
{BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
{BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
{BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80},
{BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80},
{BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01},
{BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01},
{BOLERO_CDC_WSA_RX0_RX_PATH_CFG0, 0x01, 0x01},
@@ -2828,25 +2830,22 @@ static void wsa_macro_init_reg(struct snd_soc_component *component)
static int wsa_macro_core_vote(void *handle, bool enable)
{
int rc = 0;
struct wsa_macro_priv *wsa_priv = (struct wsa_macro_priv *) handle;
if (wsa_priv == NULL) {
pr_err("%s: wsa priv data is NULL\n", __func__);
return -EINVAL;
}
if (enable) {
pm_runtime_get_sync(wsa_priv->dev);
if (bolero_check_core_votes(wsa_priv->dev))
rc = 0;
else
rc = -ENOTSYNC;
} else {
pm_runtime_put_autosuspend(wsa_priv->dev);
pm_runtime_mark_last_busy(wsa_priv->dev);
}
return rc;
if (bolero_check_core_votes(wsa_priv->dev))
return 0;
else
return -EINVAL;
}
static int wsa_swrm_clock(void *handle, bool enable)
@@ -3240,12 +3239,12 @@ static int wsa_macro_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "%s: register macro failed\n", __func__);
goto reg_macro_fail;
}
schedule_work(&wsa_priv->wsa_macro_add_child_devices_work);
pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_suspend_ignore_children(&pdev->dev, true);
pm_runtime_enable(&pdev->dev);
schedule_work(&wsa_priv->wsa_macro_add_child_devices_work);
return ret;
reg_macro_fail:

139
techpack/audio/asoc/codecs/cs35l41/Kbuild Executable file
View File

@@ -0,0 +1,139 @@
# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.19
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ CS35L41 ############
# for CS35L41 Codec
ifdef CONFIG_SND_SOC_CS35L41
CS35L41_OBJS += cs35l41.o
CS35L41_OBJS += cs35l41-i2c.o
CS35L41_OBJS += cs35l41-tables.o
CS35L41_OBJS += wm_adsp.o
CS35L41_OBJS += send_data_to_xlog.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
EXTRA_CFLAGS += $(INCS)
ifeq (y, $(filter y,\
$(CONFIG_MACH_XIAOMI_ALIOTH) \
$(CONFIG_MACH_XIAOMI_APOLLO) \
$(CONFIG_MACH_XIAOMI_CAS) \
$(CONFIG_MACH_XIAOMI_CMI) \
$(CONFIG_MACH_XIAOMI_ELISH) \
$(CONFIG_MACH_XIAOMI_ENUMA) \
$(CONFIG_MACH_XIAOMI_MUNCH) \
$(CONFIG_MACH_XIAOMI_PSYCHE) \
$(CONFIG_MACH_XIAOMI_THYME) \
$(CONFIG_MACH_XIAOMI_UMI)))
CDEFINES += -DCONFIG_AUDIO_SMARTPA_STEREO
endif
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_CS35L41) += cs35l41_dlkm.o
cs35l41_dlkm-y := $(CS35L41_OBJS)

124
techpack/audio/asoc/codecs/cs35l41/cs35l41-i2c.c Normal file
View File

@@ -0,0 +1,124 @@
/*
* cs35l41-i2c.c -- CS35l41 I2C driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Author: David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/gpio.h>
#include "wm_adsp.h"
#include "cs35l41.h"
#include <sound/cs35l41.h>
static struct regmap_config cs35l41_regmap_i2c = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct i2c_device_id cs35l41_id_i2c[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{},
};
MODULE_DEVICE_TABLE(i2c, cs35l41_id_i2c);
static int cs35l41_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct cs35l41_private *cs35l41;
struct device *dev = &client->dev;
struct cs35l41_platform_data *pdata = dev_get_platdata(dev);
const struct regmap_config *regmap_config = &cs35l41_regmap_i2c;
int ret;
dev_info(dev, "cs35l41 i2c probe start\n");
cs35l41 = devm_kzalloc(dev, sizeof(struct cs35l41_private), GFP_KERNEL);
if (cs35l41 == NULL)
return -ENOMEM;
mutex_init(&cs35l41->rate_lock);
cs35l41->dev = dev;
cs35l41->irq = client->irq;
cs35l41->bus_spi = false;
i2c_set_clientdata(client, cs35l41);
cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(cs35l41->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
return cs35l41_probe(cs35l41, pdata);
}
static int cs35l41_i2c_remove(struct i2c_client *client)
{
struct cs35l41_private *cs35l41 = i2c_get_clientdata(client);
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
wm_adsp2_remove(&cs35l41->dsp);
regulator_bulk_disable(cs35l41->num_supplies, cs35l41->supplies);
snd_soc_unregister_component(cs35l41->dev);
return 0;
}
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
static struct i2c_driver cs35l41_i2c_driver = {
.driver = {
.name = "cs35l41",
.of_match_table = cs35l41_of_match,
},
.id_table = cs35l41_id_i2c,
.probe = cs35l41_i2c_probe,
.remove = cs35l41_i2c_remove,
};
module_i2c_driver(cs35l41_i2c_driver);
MODULE_DESCRIPTION("I2C CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
MODULE_LICENSE("GPL");

115
techpack/audio/asoc/codecs/cs35l41/cs35l41-spi.c Normal file
View File

@@ -0,0 +1,115 @@
/*
* cs35l41-spi.c -- CS35l41 SPI driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Author: David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include "wm_adsp.h"
#include "cs35l41.h"
#include <sound/cs35l41.h>
static struct regmap_config cs35l41_regmap_spi = {
.reg_bits = 32,
.val_bits = 32,
.pad_bits = 16,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct spi_device_id cs35l41_id_spi[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{},
};
MODULE_DEVICE_TABLE(spi, cs35l41_id_spi);
static int cs35l41_spi_probe(struct spi_device *spi)
{
const struct regmap_config *regmap_config = &cs35l41_regmap_spi;
struct cs35l41_platform_data *pdata = dev_get_platdata(&spi->dev);
struct cs35l41_private *cs35l41;
int ret;
cs35l41 = devm_kzalloc(&spi->dev, sizeof(struct cs35l41_private),
GFP_KERNEL);
if (cs35l41 == NULL)
return -ENOMEM;
mutex_init(&cs35l41->rate_lock);
spi_set_drvdata(spi, cs35l41);
cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
cs35l41->dev = &spi->dev;
cs35l41->irq = spi->irq;
return cs35l41_probe(cs35l41, pdata);
}
static int cs35l41_spi_remove(struct spi_device *spi)
{
struct cs35l41_private *cs35l41 = spi_get_drvdata(spi);
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
wm_adsp2_remove(&cs35l41->dsp);
regulator_bulk_disable(cs35l41->num_supplies, cs35l41->supplies);
snd_soc_unregister_component(cs35l41->dev);
return 0;
}
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
static struct spi_driver cs35l41_spi_driver = {
.driver = {
.name = "cs35l41",
.of_match_table = cs35l41_of_match,
},
.id_table = cs35l41_id_spi,
.probe = cs35l41_spi_probe,
.remove = cs35l41_spi_remove,
};
module_spi_driver(cs35l41_spi_driver);
MODULE_DESCRIPTION("SPI CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
MODULE_LICENSE("GPL");

952
techpack/audio/asoc/codecs/cs35l41/cs35l41-tables.c Normal file
View File

@@ -0,0 +1,952 @@
/*
* cs35l41-tables.c -- CS35L41 ALSA SoC audio driver
*
* Copyright 2018 Cirrus Logic, Inc.
*
* Author: Brian Austin <brian.austin@cirrus.com>
* David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "cs35l41.h"
const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = {
{ CS35L41_TEST_KEY_CTL, 0x00000000 },
{ CS35L41_USER_KEY_CTL, 0x00000000 },
{ CS35L41_OTP_CTRL0, 0x00006418 },
{ CS35L41_OTP_CTRL1, 0x00000000 },
{ CS35L41_OTP_CTRL3, 0x00000000 },
{ CS35L41_OTP_CTRL4, 0x00000000 },
{ CS35L41_OTP_CTRL5, 0x00000030 },
{ CS35L41_OTP_CTRL6, 0x00000000 },
{ CS35L41_OTP_CTRL7, 0x00000000 },
{ CS35L41_OTP_CTRL8, 0x00000000 },
{ CS35L41_PWR_CTRL1, 0x00000000 },
{ CS35L41_PWR_CTRL3, 0x01000010 },
{ CS35L41_CTRL_OVRRIDE, 0x00000002 },
{ CS35L41_AMP_OUT_MUTE, 0x00000000 },
{ CS35L41_PROTECT_REL_ERR_IGN, 0x00000000 },
{ CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
{ CS35L41_JTAG_CONTROL, 0x00000000 },
{ CS35L41_PLL_CLK_CTRL, 0x00000010 },
{ CS35L41_DSP_CLK_CTRL, 0x00000003 },
{ CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
{ CS35L41_DATA_FS_SEL, 0x00000000 },
{ CS35L41_MDSYNC_EN, 0x00000200 },
{ CS35L41_MDSYNC_TX_ID, 0x00000000 },
{ CS35L41_MDSYNC_PWR_CTRL, 0x00000002 },
{ CS35L41_MDSYNC_DATA_TX, 0x00000000 },
{ CS35L41_MDSYNC_TX_STATUS, 0x00000002 },
{ CS35L41_MDSYNC_DATA_RX, 0x00000000 },
{ CS35L41_MDSYNC_RX_STATUS, 0x00000002 },
{ CS35L41_MDSYNC_ERR_STATUS, 0x00000000 },
{ CS35L41_MDSYNC_SYNC_PTE2, 0x00000000 },
{ CS35L41_MDSYNC_SYNC_PTE3, 0x00000000 },
{ CS35L41_MDSYNC_SYNC_MSM_STATUS, 0x00000000 },
{ CS35L41_BSTCVRT_VCTRL1, 0x00000000 },
{ CS35L41_BSTCVRT_VCTRL2, 0x00000001 },
{ CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
{ CS35L41_BSTCVRT_SFT_RAMP, 0x00000003 },
{ CS35L41_BSTCVRT_COEFF, 0x00002424 },
{ CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
{ CS35L41_BSTCVRT_SW_FREQ, 0x01008000 },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00002001 },
{ CS35L41_BSTCVRT_DCM_MODE_FORCE, 0x00000000 },
{ CS35L41_BSTCVRT_OVERVOLT_CTRL, 0x00000130 },
{ CS35L41_VI_VOL_POL, 0x08000800 },
{ CS35L41_DTEMP_WARN_THLD, 0x00000002 },
{ CS35L41_DTEMP_EN, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000001 },
{ CS35L41_SP_ENABLES, 0x00000000 },
{ CS35L41_SP_RATE_CTRL, 0x00000028 },
{ CS35L41_SP_FORMAT, 0x20200200 },
{ CS35L41_SP_HIZ_CTRL, 0x00000002 },
{ CS35L41_SP_FRAME_TX_SLOT, 0x03020100 },
{ CS35L41_SP_FRAME_RX_SLOT, 0x00000100 },
{ CS35L41_SP_TX_WL, 0x00000018 },
{ CS35L41_SP_RX_WL, 0x00000018 },
{ CS35L41_DAC_PCM1_SRC, 0x00000008 },
{ CS35L41_ASP_TX1_SRC, 0x00000018 },
{ CS35L41_ASP_TX2_SRC, 0x00000019 },
{ CS35L41_ASP_TX3_SRC, 0x00000020 },
{ CS35L41_ASP_TX4_SRC, 0x00000021 },
{ CS35L41_DSP1_RX1_SRC, 0x00000008 },
{ CS35L41_DSP1_RX2_SRC, 0x00000009 },
{ CS35L41_DSP1_RX3_SRC, 0x00000018 },
{ CS35L41_DSP1_RX4_SRC, 0x00000019 },
{ CS35L41_DSP1_RX5_SRC, 0x00000020 },
{ CS35L41_DSP1_RX6_SRC, 0x00000021 },
{ CS35L41_DSP1_RX7_SRC, 0x0000003A },
{ CS35L41_DSP1_RX8_SRC, 0x00000001 },
{ CS35L41_NGATE1_SRC, 0x00000008 },
{ CS35L41_NGATE2_SRC, 0x00000009 },
{ CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
{ CS35L41_VPBR_CFG, 0x02AA1905 },
{ CS35L41_VBBR_CFG, 0x02AA1905 },
{ CS35L41_VPBR_STATUS, 0x00000000 },
{ CS35L41_VBBR_STATUS, 0x00000000 },
{ CS35L41_OVERTEMP_CFG, 0x00000001 },
{ CS35L41_AMP_ERR_VOL, 0x00000000 },
{ CS35L41_VOL_STATUS_TO_DSP, 0x00000000 },
{ CS35L41_CLASSH_CFG, 0x000B0405 },
{ CS35L41_WKFET_CFG, 0x00000111 },
{ CS35L41_NG_CFG, 0x00000033 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000273 },
{ CS35L41_DAC_MSM_CFG, 0x00580000 },
{ CS35L41_GPIO1_CTRL1, 0xE1000001 },
{ CS35L41_GPIO2_CTRL1, 0xE1000001 },
{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },
{ CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
{ CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
{ CS35L41_CLOCK_DETECT_1, 0x00000000 },
{ CS35L41_TIMER1_CONTROL, 0x00000000 },
{ CS35L41_TIMER1_COUNT_PRESET, 0x00000000 },
{ CS35L41_TIMER1_START_STOP, 0x00000000 },
{ CS35L41_TIMER1_STATUS, 0x00000000 },
{ CS35L41_TIMER1_COUNT_READBACK, 0x00000000 },
{ CS35L41_TIMER1_DSP_CLK_CFG, 0x00000000 },
{ CS35L41_TIMER1_DSP_CLK_STATUS, 0x00000000 },
{ CS35L41_TIMER2_CONTROL, 0x00000000 },
{ CS35L41_TIMER2_COUNT_PRESET, 0x00000000 },
{ CS35L41_TIMER2_START_STOP, 0x00000000 },
{ CS35L41_TIMER2_STATUS, 0x00000000 },
{ CS35L41_TIMER2_COUNT_READBACK, 0x00000000 },
{ CS35L41_TIMER2_DSP_CLK_CFG, 0x00000000 },
{ CS35L41_TIMER2_DSP_CLK_STATUS, 0x00000000 },
{ CS35L41_DFT_JTAG_CONTROL, 0x00000000 },
{ CS35L41_DIE_STS1, 0x00000000 },
{ CS35L41_DIE_STS2, 0x00000000 },
{ CS35L41_TEMP_CAL1, 0x00000000 },
{ CS35L41_TEMP_CAL2, 0x00000000 },
};
bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_REVID:
case CS35L41_FABID:
case CS35L41_RELID:
case CS35L41_OTPID:
case CS35L41_TEST_KEY_CTL:
case CS35L41_USER_KEY_CTL:
case CS35L41_OTP_CTRL0:
case CS35L41_OTP_CTRL3:
case CS35L41_OTP_CTRL4:
case CS35L41_OTP_CTRL5:
case CS35L41_OTP_CTRL6:
case CS35L41_OTP_CTRL7:
case CS35L41_OTP_CTRL8:
case CS35L41_PWR_CTRL1:
case CS35L41_PWR_CTRL2:
case CS35L41_PWR_CTRL3:
case CS35L41_CTRL_OVRRIDE:
case CS35L41_AMP_OUT_MUTE:
case CS35L41_PROTECT_REL_ERR_IGN:
case CS35L41_GPIO_PAD_CONTROL:
case CS35L41_JTAG_CONTROL:
case CS35L41_PLL_CLK_CTRL:
case CS35L41_DSP_CLK_CTRL:
case CS35L41_GLOBAL_CLK_CTRL:
case CS35L41_DATA_FS_SEL:
case CS35L41_MDSYNC_EN:
case CS35L41_MDSYNC_TX_ID:
case CS35L41_MDSYNC_PWR_CTRL:
case CS35L41_MDSYNC_DATA_TX:
case CS35L41_MDSYNC_TX_STATUS:
case CS35L41_MDSYNC_DATA_RX:
case CS35L41_MDSYNC_RX_STATUS:
case CS35L41_MDSYNC_ERR_STATUS:
case CS35L41_MDSYNC_SYNC_PTE2:
case CS35L41_MDSYNC_SYNC_PTE3:
case CS35L41_MDSYNC_SYNC_MSM_STATUS:
case CS35L41_BSTCVRT_VCTRL1:
case CS35L41_BSTCVRT_VCTRL2:
case CS35L41_BSTCVRT_PEAK_CUR:
case CS35L41_BSTCVRT_SFT_RAMP:
case CS35L41_BSTCVRT_COEFF:
case CS35L41_BSTCVRT_SLOPE_LBST:
case CS35L41_BSTCVRT_SW_FREQ:
case CS35L41_BSTCVRT_DCM_CTRL:
case CS35L41_BSTCVRT_DCM_MODE_FORCE:
case CS35L41_BSTCVRT_OVERVOLT_CTRL:
case CS35L41_VI_VOL_POL:
case CS35L41_DTEMP_WARN_THLD:
case CS35L41_DTEMP_CFG:
case CS35L41_DTEMP_EN:
case CS35L41_VPVBST_FS_SEL:
case CS35L41_SP_ENABLES:
case CS35L41_SP_RATE_CTRL:
case CS35L41_SP_FORMAT:
case CS35L41_SP_HIZ_CTRL:
case CS35L41_SP_FRAME_TX_SLOT:
case CS35L41_SP_FRAME_RX_SLOT:
case CS35L41_SP_TX_WL:
case CS35L41_SP_RX_WL:
case CS35L41_DAC_PCM1_SRC:
case CS35L41_ASP_TX1_SRC:
case CS35L41_ASP_TX2_SRC:
case CS35L41_ASP_TX3_SRC:
case CS35L41_ASP_TX4_SRC:
case CS35L41_DSP1_RX1_SRC:
case CS35L41_DSP1_RX2_SRC:
case CS35L41_DSP1_RX3_SRC:
case CS35L41_DSP1_RX4_SRC:
case CS35L41_DSP1_RX5_SRC:
case CS35L41_DSP1_RX6_SRC:
case CS35L41_DSP1_RX7_SRC:
case CS35L41_DSP1_RX8_SRC:
case CS35L41_NGATE1_SRC:
case CS35L41_NGATE2_SRC:
case CS35L41_AMP_DIG_VOL_CTRL:
case CS35L41_VPBR_CFG:
case CS35L41_VBBR_CFG:
case CS35L41_VPBR_STATUS:
case CS35L41_VBBR_STATUS:
case CS35L41_OVERTEMP_CFG:
case CS35L41_AMP_ERR_VOL:
case CS35L41_VOL_STATUS_TO_DSP:
case CS35L41_CLASSH_CFG:
case CS35L41_WKFET_CFG:
case CS35L41_NG_CFG:
case CS35L41_AMP_GAIN_CTRL:
case CS35L41_DAC_MSM_CFG:
case CS35L41_IRQ1_CFG:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ1_MASK1:
case CS35L41_IRQ1_MASK2:
case CS35L41_IRQ1_MASK3:
case CS35L41_IRQ1_MASK4:
case CS35L41_IRQ1_FRC1:
case CS35L41_IRQ1_FRC2:
case CS35L41_IRQ1_FRC3:
case CS35L41_IRQ1_FRC4:
case CS35L41_IRQ1_EDGE1:
case CS35L41_IRQ1_EDGE4:
case CS35L41_IRQ1_POL1:
case CS35L41_IRQ1_POL2:
case CS35L41_IRQ1_POL3:
case CS35L41_IRQ1_POL4:
case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_CFG:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_IRQ2_MASK1:
case CS35L41_IRQ2_MASK2:
case CS35L41_IRQ2_MASK3:
case CS35L41_IRQ2_MASK4:
case CS35L41_IRQ2_FRC1:
case CS35L41_IRQ2_FRC2:
case CS35L41_IRQ2_FRC3:
case CS35L41_IRQ2_FRC4:
case CS35L41_IRQ2_EDGE1:
case CS35L41_IRQ2_EDGE4:
case CS35L41_IRQ2_POL1:
case CS35L41_IRQ2_POL2:
case CS35L41_IRQ2_POL3:
case CS35L41_IRQ2_POL4:
case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
case CS35L41_GPIO1_CTRL1:
case CS35L41_GPIO2_CTRL1:
case CS35L41_MIXER_NGATE_CFG:
case CS35L41_MIXER_NGATE_CH1_CFG:
case CS35L41_MIXER_NGATE_CH2_CFG:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_CLOCK_DETECT_1:
case CS35L41_TIMER1_CONTROL:
case CS35L41_TIMER1_COUNT_PRESET:
case CS35L41_TIMER1_STATUS:
case CS35L41_TIMER1_COUNT_READBACK:
case CS35L41_TIMER1_DSP_CLK_CFG:
case CS35L41_TIMER1_DSP_CLK_STATUS:
case CS35L41_TIMER2_CONTROL:
case CS35L41_TIMER2_COUNT_PRESET:
case CS35L41_TIMER2_STATUS:
case CS35L41_TIMER2_COUNT_READBACK:
case CS35L41_TIMER2_DSP_CLK_CFG:
case CS35L41_TIMER2_DSP_CLK_STATUS:
case CS35L41_DFT_JTAG_CONTROL:
case CS35L41_DIE_STS1:
case CS35L41_DIE_STS2:
case CS35L41_TEMP_CAL1:
case CS35L41_TEMP_CAL2:
case CS35L41_DSP1_TIMESTAMP_COUNT:
case CS35L41_DSP1_SYS_ID:
case CS35L41_DSP1_SYS_VERSION:
case CS35L41_DSP1_SYS_CORE_ID:
case CS35L41_DSP1_SYS_AHB_ADDR:
case CS35L41_DSP1_SYS_XSRAM_SIZE:
case CS35L41_DSP1_SYS_YSRAM_SIZE:
case CS35L41_DSP1_SYS_PSRAM_SIZE:
case CS35L41_DSP1_SYS_PM_BOOT_SIZE:
case CS35L41_DSP1_SYS_FEATURES:
case CS35L41_DSP1_SYS_FIR_FILTERS:
case CS35L41_DSP1_SYS_LMS_FILTERS:
case CS35L41_DSP1_SYS_XM_BANK_SIZE:
case CS35L41_DSP1_SYS_YM_BANK_SIZE:
case CS35L41_DSP1_SYS_PM_BANK_SIZE:
case CS35L41_DSP1_AHBM_WIN0_CTRL0:
case CS35L41_DSP1_AHBM_WIN0_CTRL1:
case CS35L41_DSP1_AHBM_WIN1_CTRL0:
case CS35L41_DSP1_AHBM_WIN1_CTRL1:
case CS35L41_DSP1_AHBM_WIN2_CTRL0:
case CS35L41_DSP1_AHBM_WIN2_CTRL1:
case CS35L41_DSP1_AHBM_WIN3_CTRL0:
case CS35L41_DSP1_AHBM_WIN3_CTRL1:
case CS35L41_DSP1_AHBM_WIN4_CTRL0:
case CS35L41_DSP1_AHBM_WIN4_CTRL1:
case CS35L41_DSP1_AHBM_WIN5_CTRL0:
case CS35L41_DSP1_AHBM_WIN5_CTRL1:
case CS35L41_DSP1_AHBM_WIN6_CTRL0:
case CS35L41_DSP1_AHBM_WIN6_CTRL1:
case CS35L41_DSP1_AHBM_WIN7_CTRL0:
case CS35L41_DSP1_AHBM_WIN7_CTRL1:
case CS35L41_DSP1_AHBM_WIN_DBG_CTRL0:
case CS35L41_DSP1_AHBM_WIN_DBG_CTRL1:
case CS35L41_DSP1_DEBUG:
case CS35L41_DSP1_TIMER_CTRL:
case CS35L41_DSP1_RX1_RATE:
case CS35L41_DSP1_RX2_RATE:
case CS35L41_DSP1_RX3_RATE:
case CS35L41_DSP1_RX4_RATE:
case CS35L41_DSP1_RX5_RATE:
case CS35L41_DSP1_RX6_RATE:
case CS35L41_DSP1_RX7_RATE:
case CS35L41_DSP1_RX8_RATE:
case CS35L41_DSP1_TX1_RATE:
case CS35L41_DSP1_TX2_RATE:
case CS35L41_DSP1_TX3_RATE:
case CS35L41_DSP1_TX4_RATE:
case CS35L41_DSP1_TX5_RATE:
case CS35L41_DSP1_TX6_RATE:
case CS35L41_DSP1_TX7_RATE:
case CS35L41_DSP1_TX8_RATE:
case CS35L41_DSP1_NMI_CTRL1:
case CS35L41_DSP1_NMI_CTRL2:
case CS35L41_DSP1_NMI_CTRL3:
case CS35L41_DSP1_NMI_CTRL4:
case CS35L41_DSP1_NMI_CTRL5:
case CS35L41_DSP1_NMI_CTRL6:
case CS35L41_DSP1_NMI_CTRL7:
case CS35L41_DSP1_NMI_CTRL8:
case CS35L41_DSP1_RESUME_CTRL:
case CS35L41_DSP1_IRQ1_CTRL:
case CS35L41_DSP1_IRQ2_CTRL:
case CS35L41_DSP1_IRQ3_CTRL:
case CS35L41_DSP1_IRQ4_CTRL:
case CS35L41_DSP1_IRQ5_CTRL:
case CS35L41_DSP1_IRQ6_CTRL:
case CS35L41_DSP1_IRQ7_CTRL:
case CS35L41_DSP1_IRQ8_CTRL:
case CS35L41_DSP1_IRQ9_CTRL:
case CS35L41_DSP1_IRQ10_CTRL:
case CS35L41_DSP1_IRQ11_CTRL:
case CS35L41_DSP1_IRQ12_CTRL:
case CS35L41_DSP1_IRQ13_CTRL:
case CS35L41_DSP1_IRQ14_CTRL:
case CS35L41_DSP1_IRQ15_CTRL:
case CS35L41_DSP1_IRQ16_CTRL:
case CS35L41_DSP1_IRQ17_CTRL:
case CS35L41_DSP1_IRQ18_CTRL:
case CS35L41_DSP1_IRQ19_CTRL:
case CS35L41_DSP1_IRQ20_CTRL:
case CS35L41_DSP1_IRQ21_CTRL:
case CS35L41_DSP1_IRQ22_CTRL:
case CS35L41_DSP1_IRQ23_CTRL:
case CS35L41_DSP1_SCRATCH1:
case CS35L41_DSP1_SCRATCH2:
case CS35L41_DSP1_SCRATCH3:
case CS35L41_DSP1_SCRATCH4:
case CS35L41_DSP1_CCM_CORE_CTRL:
case CS35L41_DSP1_CCM_CLK_OVERRIDE:
case CS35L41_DSP1_XM_MSTR_EN:
case CS35L41_DSP1_XM_CORE_PRI:
case CS35L41_DSP1_XM_AHB_PACK_PL_PRI:
case CS35L41_DSP1_XM_AHB_UP_PL_PRI:
case CS35L41_DSP1_XM_ACCEL_PL0_PRI:
case CS35L41_DSP1_XM_NPL0_PRI:
case CS35L41_DSP1_YM_MSTR_EN:
case CS35L41_DSP1_YM_CORE_PRI:
case CS35L41_DSP1_YM_AHB_PACK_PL_PRI:
case CS35L41_DSP1_YM_AHB_UP_PL_PRI:
case CS35L41_DSP1_YM_ACCEL_PL0_PRI:
case CS35L41_DSP1_YM_NPL0_PRI:
case CS35L41_DSP1_PM_MSTR_EN:
case CS35L41_DSP1_PM_PATCH0_ADDR:
case CS35L41_DSP1_PM_PATCH0_EN:
case CS35L41_DSP1_PM_PATCH0_DATA_LO:
case CS35L41_DSP1_PM_PATCH0_DATA_HI:
case CS35L41_DSP1_PM_PATCH1_ADDR:
case CS35L41_DSP1_PM_PATCH1_EN:
case CS35L41_DSP1_PM_PATCH1_DATA_LO:
case CS35L41_DSP1_PM_PATCH1_DATA_HI:
case CS35L41_DSP1_PM_PATCH2_ADDR:
case CS35L41_DSP1_PM_PATCH2_EN:
case CS35L41_DSP1_PM_PATCH2_DATA_LO:
case CS35L41_DSP1_PM_PATCH2_DATA_HI:
case CS35L41_DSP1_PM_PATCH3_ADDR:
case CS35L41_DSP1_PM_PATCH3_EN:
case CS35L41_DSP1_PM_PATCH3_DATA_LO:
case CS35L41_DSP1_PM_PATCH3_DATA_HI:
case CS35L41_DSP1_PM_PATCH4_ADDR:
case CS35L41_DSP1_PM_PATCH4_EN:
case CS35L41_DSP1_PM_PATCH4_DATA_LO:
case CS35L41_DSP1_PM_PATCH4_DATA_HI:
case CS35L41_DSP1_PM_PATCH5_ADDR:
case CS35L41_DSP1_PM_PATCH5_EN:
case CS35L41_DSP1_PM_PATCH5_DATA_LO:
case CS35L41_DSP1_PM_PATCH5_DATA_HI:
case CS35L41_DSP1_PM_PATCH6_ADDR:
case CS35L41_DSP1_PM_PATCH6_EN:
case CS35L41_DSP1_PM_PATCH6_DATA_LO:
case CS35L41_DSP1_PM_PATCH6_DATA_HI:
case CS35L41_DSP1_PM_PATCH7_ADDR:
case CS35L41_DSP1_PM_PATCH7_EN:
case CS35L41_DSP1_PM_PATCH7_DATA_LO:
case CS35L41_DSP1_PM_PATCH7_DATA_HI:
case CS35L41_DSP1_MPU_XM_ACCESS0:
case CS35L41_DSP1_MPU_YM_ACCESS0:
case CS35L41_DSP1_MPU_WNDW_ACCESS0:
case CS35L41_DSP1_MPU_XREG_ACCESS0:
case CS35L41_DSP1_MPU_YREG_ACCESS0:
case CS35L41_DSP1_MPU_XM_ACCESS1:
case CS35L41_DSP1_MPU_YM_ACCESS1:
case CS35L41_DSP1_MPU_WNDW_ACCESS1:
case CS35L41_DSP1_MPU_XREG_ACCESS1:
case CS35L41_DSP1_MPU_YREG_ACCESS1:
case CS35L41_DSP1_MPU_XM_ACCESS2:
case CS35L41_DSP1_MPU_YM_ACCESS2:
case CS35L41_DSP1_MPU_WNDW_ACCESS2:
case CS35L41_DSP1_MPU_XREG_ACCESS2:
case CS35L41_DSP1_MPU_YREG_ACCESS2:
case CS35L41_DSP1_MPU_XM_ACCESS3:
case CS35L41_DSP1_MPU_YM_ACCESS3:
case CS35L41_DSP1_MPU_WNDW_ACCESS3:
case CS35L41_DSP1_MPU_XREG_ACCESS3:
case CS35L41_DSP1_MPU_YREG_ACCESS3:
case CS35L41_DSP1_MPU_XM_VIO_ADDR:
case CS35L41_DSP1_MPU_XM_VIO_STATUS:
case CS35L41_DSP1_MPU_YM_VIO_ADDR:
case CS35L41_DSP1_MPU_YM_VIO_STATUS:
case CS35L41_DSP1_MPU_PM_VIO_ADDR:
case CS35L41_DSP1_MPU_PM_VIO_STATUS:
case CS35L41_DSP1_MPU_LOCK_CONFIG:
case CS35L41_DSP1_MPU_WDT_RST_CTRL:
case CS35L41_DSP1_STRMARB_MSTR0_CFG0:
case CS35L41_DSP1_STRMARB_MSTR0_CFG1:
case CS35L41_DSP1_STRMARB_MSTR0_CFG2:
case CS35L41_DSP1_STRMARB_MSTR1_CFG0:
case CS35L41_DSP1_STRMARB_MSTR1_CFG1:
case CS35L41_DSP1_STRMARB_MSTR1_CFG2:
case CS35L41_DSP1_STRMARB_MSTR2_CFG0:
case CS35L41_DSP1_STRMARB_MSTR2_CFG1:
case CS35L41_DSP1_STRMARB_MSTR2_CFG2:
case CS35L41_DSP1_STRMARB_MSTR3_CFG0:
case CS35L41_DSP1_STRMARB_MSTR3_CFG1:
case CS35L41_DSP1_STRMARB_MSTR3_CFG2:
case CS35L41_DSP1_STRMARB_MSTR4_CFG0:
case CS35L41_DSP1_STRMARB_MSTR4_CFG1:
case CS35L41_DSP1_STRMARB_MSTR4_CFG2:
case CS35L41_DSP1_STRMARB_MSTR5_CFG0:
case CS35L41_DSP1_STRMARB_MSTR5_CFG1:
case CS35L41_DSP1_STRMARB_MSTR5_CFG2:
case CS35L41_DSP1_STRMARB_MSTR6_CFG0:
case CS35L41_DSP1_STRMARB_MSTR6_CFG1:
case CS35L41_DSP1_STRMARB_MSTR6_CFG2:
case CS35L41_DSP1_STRMARB_MSTR7_CFG0:
case CS35L41_DSP1_STRMARB_MSTR7_CFG1:
case CS35L41_DSP1_STRMARB_MSTR7_CFG2:
case CS35L41_DSP1_STRMARB_TX0_CFG0:
case CS35L41_DSP1_STRMARB_TX0_CFG1:
case CS35L41_DSP1_STRMARB_TX1_CFG0:
case CS35L41_DSP1_STRMARB_TX1_CFG1:
case CS35L41_DSP1_STRMARB_TX2_CFG0:
case CS35L41_DSP1_STRMARB_TX2_CFG1:
case CS35L41_DSP1_STRMARB_TX3_CFG0:
case CS35L41_DSP1_STRMARB_TX3_CFG1:
case CS35L41_DSP1_STRMARB_TX4_CFG0:
case CS35L41_DSP1_STRMARB_TX4_CFG1:
case CS35L41_DSP1_STRMARB_TX5_CFG0:
case CS35L41_DSP1_STRMARB_TX5_CFG1:
case CS35L41_DSP1_STRMARB_TX6_CFG0:
case CS35L41_DSP1_STRMARB_TX6_CFG1:
case CS35L41_DSP1_STRMARB_TX7_CFG0:
case CS35L41_DSP1_STRMARB_TX7_CFG1:
case CS35L41_DSP1_STRMARB_RX0_CFG0:
case CS35L41_DSP1_STRMARB_RX0_CFG1:
case CS35L41_DSP1_STRMARB_RX1_CFG0:
case CS35L41_DSP1_STRMARB_RX1_CFG1:
case CS35L41_DSP1_STRMARB_RX2_CFG0:
case CS35L41_DSP1_STRMARB_RX2_CFG1:
case CS35L41_DSP1_STRMARB_RX3_CFG0:
case CS35L41_DSP1_STRMARB_RX3_CFG1:
case CS35L41_DSP1_STRMARB_RX4_CFG0:
case CS35L41_DSP1_STRMARB_RX4_CFG1:
case CS35L41_DSP1_STRMARB_RX5_CFG0:
case CS35L41_DSP1_STRMARB_RX5_CFG1:
case CS35L41_DSP1_STRMARB_RX6_CFG0:
case CS35L41_DSP1_STRMARB_RX6_CFG1:
case CS35L41_DSP1_STRMARB_RX7_CFG0:
case CS35L41_DSP1_STRMARB_RX7_CFG1:
case CS35L41_DSP1_STRMARB_IRQ0_CFG0:
case CS35L41_DSP1_STRMARB_IRQ0_CFG1:
case CS35L41_DSP1_STRMARB_IRQ0_CFG2:
case CS35L41_DSP1_STRMARB_IRQ1_CFG0:
case CS35L41_DSP1_STRMARB_IRQ1_CFG1:
case CS35L41_DSP1_STRMARB_IRQ1_CFG2:
case CS35L41_DSP1_STRMARB_IRQ2_CFG0:
case CS35L41_DSP1_STRMARB_IRQ2_CFG1:
case CS35L41_DSP1_STRMARB_IRQ2_CFG2:
case CS35L41_DSP1_STRMARB_IRQ3_CFG0:
case CS35L41_DSP1_STRMARB_IRQ3_CFG1:
case CS35L41_DSP1_STRMARB_IRQ3_CFG2:
case CS35L41_DSP1_STRMARB_IRQ4_CFG0:
case CS35L41_DSP1_STRMARB_IRQ4_CFG1:
case CS35L41_DSP1_STRMARB_IRQ4_CFG2:
case CS35L41_DSP1_STRMARB_IRQ5_CFG0:
case CS35L41_DSP1_STRMARB_IRQ5_CFG1:
case CS35L41_DSP1_STRMARB_IRQ5_CFG2:
case CS35L41_DSP1_STRMARB_IRQ6_CFG0:
case CS35L41_DSP1_STRMARB_IRQ6_CFG1:
case CS35L41_DSP1_STRMARB_IRQ6_CFG2:
case CS35L41_DSP1_STRMARB_IRQ7_CFG0:
case CS35L41_DSP1_STRMARB_IRQ7_CFG1:
case CS35L41_DSP1_STRMARB_IRQ7_CFG2:
case CS35L41_DSP1_STRMARB_RESYNC_MSK:
case CS35L41_DSP1_STRMARB_ERR_STATUS:
case CS35L41_DSP1_INTPCTL_RES_STATIC:
case CS35L41_DSP1_INTPCTL_RES_DYN:
case CS35L41_DSP1_INTPCTL_NMI_CTRL:
case CS35L41_DSP1_INTPCTL_IRQ_INV:
case CS35L41_DSP1_INTPCTL_IRQ_MODE:
case CS35L41_DSP1_INTPCTL_IRQ_EN:
case CS35L41_DSP1_INTPCTL_IRQ_MSK:
case CS35L41_DSP1_INTPCTL_IRQ_ERR:
case CS35L41_DSP1_INTPCTL_IRQ_PEND:
case CS35L41_DSP1_INTPCTL_TESTBITS:
case CS35L41_DSP1_WDT_CONTROL:
case CS35L41_DSP1_WDT_STATUS:
case CS35L41_OTP_TRIM_1:
case CS35L41_OTP_TRIM_2:
case CS35L41_OTP_TRIM_3:
case CS35L41_OTP_TRIM_4:
case CS35L41_OTP_TRIM_5:
case CS35L41_OTP_TRIM_6:
case CS35L41_OTP_TRIM_7:
case CS35L41_OTP_TRIM_8:
case CS35L41_OTP_TRIM_9:
case CS35L41_OTP_TRIM_10:
case CS35L41_OTP_TRIM_11:
case CS35L41_OTP_TRIM_12:
case CS35L41_OTP_TRIM_13:
case CS35L41_OTP_TRIM_14:
case CS35L41_OTP_TRIM_15:
case CS35L41_OTP_TRIM_16:
case CS35L41_OTP_TRIM_17:
case CS35L41_OTP_TRIM_18:
case CS35L41_OTP_TRIM_19:
case CS35L41_OTP_TRIM_20:
case CS35L41_OTP_TRIM_21:
case CS35L41_OTP_TRIM_22:
case CS35L41_OTP_TRIM_23:
case CS35L41_OTP_TRIM_24:
case CS35L41_OTP_TRIM_25:
case CS35L41_OTP_TRIM_26:
case CS35L41_OTP_TRIM_27:
case CS35L41_OTP_TRIM_28:
case CS35L41_OTP_TRIM_29:
case CS35L41_OTP_TRIM_30:
case CS35L41_OTP_TRIM_31:
case CS35L41_OTP_TRIM_32:
case CS35L41_OTP_TRIM_33:
case CS35L41_OTP_TRIM_34:
case CS35L41_OTP_TRIM_35:
case CS35L41_OTP_TRIM_36:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
/*test regs*/
case CS35L41_PLL_OVR:
case CS35L41_BST_TEST_DUTY:
case CS35L41_DIGPWM_IOCTRL:
return true;
default:
return false;
}
}
bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
return false;
}
}
bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_SFT_RESET:
case CS35L41_FABID:
case CS35L41_REVID:
case CS35L41_DTEMP_EN:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ1_FRC1:
case CS35L41_IRQ1_FRC2:
case CS35L41_IRQ1_FRC3:
case CS35L41_IRQ1_FRC4:
case CS35L41_IRQ1_EDGE1:
case CS35L41_IRQ1_EDGE4:
case CS35L41_IRQ1_POL1:
case CS35L41_IRQ1_POL2:
case CS35L41_IRQ1_POL3:
case CS35L41_IRQ1_POL4:
case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_IRQ2_FRC1:
case CS35L41_IRQ2_FRC2:
case CS35L41_IRQ2_FRC3:
case CS35L41_IRQ2_FRC4:
case CS35L41_IRQ2_EDGE1:
case CS35L41_IRQ2_EDGE4:
case CS35L41_IRQ2_POL1:
case CS35L41_IRQ2_POL2:
case CS35L41_IRQ2_POL3:
case CS35L41_IRQ2_POL4:
case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
case CS35L41_OTP_TRIM_1:
case CS35L41_OTP_TRIM_2:
case CS35L41_OTP_TRIM_3:
case CS35L41_OTP_TRIM_4:
case CS35L41_OTP_TRIM_5:
case CS35L41_OTP_TRIM_6:
case CS35L41_OTP_TRIM_7:
case CS35L41_OTP_TRIM_8:
case CS35L41_OTP_TRIM_9:
case CS35L41_OTP_TRIM_10:
case CS35L41_OTP_TRIM_11:
case CS35L41_OTP_TRIM_12:
case CS35L41_OTP_TRIM_13:
case CS35L41_OTP_TRIM_14:
case CS35L41_OTP_TRIM_15:
case CS35L41_OTP_TRIM_16:
case CS35L41_OTP_TRIM_17:
case CS35L41_OTP_TRIM_18:
case CS35L41_OTP_TRIM_19:
case CS35L41_OTP_TRIM_20:
case CS35L41_OTP_TRIM_21:
case CS35L41_OTP_TRIM_22:
case CS35L41_OTP_TRIM_23:
case CS35L41_OTP_TRIM_24:
case CS35L41_OTP_TRIM_25:
case CS35L41_OTP_TRIM_26:
case CS35L41_OTP_TRIM_27:
case CS35L41_OTP_TRIM_28:
case CS35L41_OTP_TRIM_29:
case CS35L41_OTP_TRIM_30:
case CS35L41_OTP_TRIM_31:
case CS35L41_OTP_TRIM_32:
case CS35L41_OTP_TRIM_33:
case CS35L41_OTP_TRIM_34:
case CS35L41_OTP_TRIM_35:
case CS35L41_OTP_TRIM_36:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
return false;
}
}
static const struct cs35l41_otp_packed_element_t
otp_map_1[CS35L41_NUM_OTP_ELEM] = {
/* addr shift size */
{ 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{ 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{ 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{ 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{ 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{ 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{ 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{ 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{ 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{ 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{ 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{ 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{ 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{ 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{ 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{ 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{ 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{ 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{ 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{ 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{ 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{ 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{ 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{ 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{ 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{ 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{ 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{ 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{ 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{ 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{ 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{ 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{ 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{ 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{ 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{ 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{ 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{ 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{ 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{ 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{ 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{ 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{ 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{ 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{ 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{ 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{ 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{ 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{ 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{ 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{ 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{ 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{ 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{ 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{ 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{ 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{ 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{ 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{ 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{ 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{ 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{ 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{ 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{ 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{ 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{ 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{ 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{ 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{ 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{ 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{ 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{ 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{ 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{ 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{ 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{ 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{ 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{ 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{ 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{ 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{ 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{ 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{ 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{ 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{ 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{ 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{ 0x00007434, 17, 1 }, /*FORCE_CAL*/
{ 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{ 0x00007068, 0, 9 }, /*MODIX*/
{ 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{ 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{ 0x00000000, 0, 1 }, /*extra bit*/
{ 0x00017040, 0, 8 }, /*X_COORDINATE*/
{ 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{ 0x00017040, 16, 8 }, /*WAFER_ID*/
{ 0x00017040, 24, 8 }, /*DVS*/
{ 0x00017044, 0, 24 }, /*LOT_NUMBER*/
};
static const struct cs35l41_otp_packed_element_t
otp_map_2[CS35L41_NUM_OTP_ELEM] = {
/* addr shift size */
{ 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{ 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{ 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{ 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{ 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{ 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{ 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{ 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{ 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{ 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{ 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{ 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{ 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{ 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{ 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{ 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{ 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{ 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{ 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{ 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{ 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{ 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{ 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{ 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{ 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{ 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{ 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{ 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{ 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{ 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{ 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{ 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{ 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{ 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{ 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{ 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{ 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{ 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{ 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{ 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{ 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{ 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{ 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{ 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{ 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{ 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{ 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{ 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{ 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{ 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{ 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{ 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{ 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{ 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{ 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{ 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{ 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{ 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{ 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{ 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{ 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{ 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{ 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{ 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{ 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{ 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{ 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{ 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{ 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{ 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{ 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{ 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{ 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{ 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{ 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{ 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{ 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{ 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{ 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{ 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{ 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{ 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{ 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{ 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{ 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{ 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{ 0x00007434, 17, 1 }, /*FORCE_CAL*/
{ 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{ 0x00007068, 0, 9 }, /*MODIX*/
{ 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{ 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{ 0x00004000, 11, 1 }, /*VMON_POL*/
{ 0x00017040, 0, 8 }, /*X_COORDINATE*/
{ 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{ 0x00017040, 16, 8 }, /*WAFER_ID*/
{ 0x00017040, 24, 8 }, /*DVS*/
{ 0x00017044, 0, 24 }, /*LOT_NUMBER*/
};
const struct cs35l41_otp_map_element_t
cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS] = {
{
.id = 0x01,
.map = otp_map_1,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x02,
.map = otp_map_2,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x06,
.map = otp_map_2,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x08,
.map = otp_map_1,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
};

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techpack/audio/asoc/codecs/cs35l41/cs35l41.c Normal file
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techpack/audio/asoc/codecs/cs35l41/cs35l41.h Normal file
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@@ -0,0 +1,792 @@
/*
* cs35l41.h -- CS35L41 ALSA SoC audio driver
*
* Copyright 2018 Cirrus Logic, Inc.
*
* Author: Brian Austin <brian.austin@cirrus.com>
* David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __CS35L41_H__
#define __CS35L41_H__
#include <linux/regmap.h>
#define CS35L41_FIRSTREG 0x00000000
#define CS35L41_LASTREG 0x03804FE8
#define CS35L41_DEVID 0x00000000
#define CS35L41_REVID 0x00000004
#define CS35L41_FABID 0x00000008
#define CS35L41_RELID 0x0000000C
#define CS35L41_OTPID 0x00000010
#define CS35L41_SFT_RESET 0x00000020
#define CS35L41_TEST_KEY_CTL 0x00000040
#define CS35L41_USER_KEY_CTL 0x00000044
#define CS35L41_OTP_MEM0 0x00000400
#define CS35L41_OTP_MEM31 0x0000047C
#define CS35L41_OTP_CTRL0 0x00000500
#define CS35L41_OTP_CTRL1 0x00000504
#define CS35L41_OTP_CTRL3 0x00000508
#define CS35L41_OTP_CTRL4 0x0000050C
#define CS35L41_OTP_CTRL5 0x00000510
#define CS35L41_OTP_CTRL6 0x00000514
#define CS35L41_OTP_CTRL7 0x00000518
#define CS35L41_OTP_CTRL8 0x0000051C
#define CS35L41_PWR_CTRL1 0x00002014
#define CS35L41_PWR_CTRL2 0x00002018
#define CS35L41_PWR_CTRL3 0x0000201C
#define CS35L41_CTRL_OVRRIDE 0x00002020
#define CS35L41_AMP_OUT_MUTE 0x00002024
#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034
#define CS35L41_GPIO_PAD_CONTROL 0x0000242C
#define CS35L41_JTAG_CONTROL 0x00002438
#define CS35L41_PLL_CLK_CTRL 0x00002C04
#define CS35L41_DSP_CLK_CTRL 0x00002C08
#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C
#define CS35L41_DATA_FS_SEL 0x00002C10
#define CS35L41_TST_FS_MON0 0x00002D10
#define CS35L41_MDSYNC_EN 0x00003400
#define CS35L41_MDSYNC_TX_ID 0x00003408
#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C
#define CS35L41_MDSYNC_DATA_TX 0x00003410
#define CS35L41_MDSYNC_TX_STATUS 0x00003414
#define CS35L41_MDSYNC_DATA_RX 0x0000341C
#define CS35L41_MDSYNC_RX_STATUS 0x00003420
#define CS35L41_MDSYNC_ERR_STATUS 0x00003424
#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528
#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C
#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C
#define CS35L41_BSTCVRT_VCTRL1 0x00003800
#define CS35L41_BSTCVRT_VCTRL2 0x00003804
#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808
#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C
#define CS35L41_BSTCVRT_COEFF 0x00003810
#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814
#define CS35L41_BSTCVRT_SW_FREQ 0x00003818
#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C
#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820
#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830
#define CS35L41_VI_VOL_POL 0x00004000
#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100
#define CS35L41_DTEMP_WARN_THLD 0x00004220
#define CS35L41_DTEMP_CFG 0x00004224
#define CS35L41_DTEMP_EN 0x00004308
#define CS35L41_VPVBST_FS_SEL 0x00004400
#define CS35L41_SP_ENABLES 0x00004800
#define CS35L41_SP_RATE_CTRL 0x00004804
#define CS35L41_SP_FORMAT 0x00004808
#define CS35L41_SP_HIZ_CTRL 0x0000480C
#define CS35L41_SP_FRAME_TX_SLOT 0x00004810
#define CS35L41_SP_FRAME_RX_SLOT 0x00004820
#define CS35L41_SP_TX_WL 0x00004830
#define CS35L41_SP_RX_WL 0x00004840
#define CS35L41_ASP_CONTROL4 0x00004854
#define CS35L41_DAC_PCM1_SRC 0x00004C00
#define CS35L41_ASP_TX1_SRC 0x00004C20
#define CS35L41_ASP_TX2_SRC 0x00004C24
#define CS35L41_ASP_TX3_SRC 0x00004C28
#define CS35L41_ASP_TX4_SRC 0x00004C2C
#define CS35L41_DSP1_RX1_SRC 0x00004C40
#define CS35L41_DSP1_RX2_SRC 0x00004C44
#define CS35L41_DSP1_RX3_SRC 0x00004C48
#define CS35L41_DSP1_RX4_SRC 0x00004C4C
#define CS35L41_DSP1_RX5_SRC 0x00004C50
#define CS35L41_DSP1_RX6_SRC 0x00004C54
#define CS35L41_DSP1_RX7_SRC 0x00004C58
#define CS35L41_DSP1_RX8_SRC 0x00004C5C
#define CS35L41_NGATE1_SRC 0x00004C60
#define CS35L41_NGATE2_SRC 0x00004C64
#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000
#define CS35L41_VPBR_CFG 0x00006404
#define CS35L41_VBBR_CFG 0x00006408
#define CS35L41_VPBR_STATUS 0x0000640C
#define CS35L41_VBBR_STATUS 0x00006410
#define CS35L41_OVERTEMP_CFG 0x00006414
#define CS35L41_AMP_ERR_VOL 0x00006418
#define CS35L41_VOL_STATUS_TO_DSP 0x00006450
#define CS35L41_CLASSH_CFG 0x00006800
#define CS35L41_WKFET_CFG 0x00006804
#define CS35L41_NG_CFG 0x00006808
#define CS35L41_AMP_GAIN_CTRL 0x00006C04
#define CS35L41_DAC_MSM_CFG 0x00007400
#define CS35L41_IRQ1_CFG 0x00010000
#define CS35L41_IRQ1_STATUS 0x00010004
#define CS35L41_IRQ1_STATUS1 0x00010010
#define CS35L41_IRQ1_STATUS2 0x00010014
#define CS35L41_IRQ1_STATUS3 0x00010018
#define CS35L41_IRQ1_STATUS4 0x0001001C
#define CS35L41_IRQ1_RAW_STATUS1 0x00010090
#define CS35L41_IRQ1_RAW_STATUS2 0x00010094
#define CS35L41_IRQ1_RAW_STATUS3 0x00010098
#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C
#define CS35L41_IRQ1_MASK1 0x00010110
#define CS35L41_IRQ1_MASK2 0x00010114
#define CS35L41_IRQ1_MASK3 0x00010118
#define CS35L41_IRQ1_MASK4 0x0001011C
#define CS35L41_IRQ1_FRC1 0x00010190
#define CS35L41_IRQ1_FRC2 0x00010194
#define CS35L41_IRQ1_FRC3 0x00010198
#define CS35L41_IRQ1_FRC4 0x0001019C
#define CS35L41_IRQ1_EDGE1 0x00010210
#define CS35L41_IRQ1_EDGE4 0x0001021C
#define CS35L41_IRQ1_POL1 0x00010290
#define CS35L41_IRQ1_POL2 0x00010294
#define CS35L41_IRQ1_POL3 0x00010298
#define CS35L41_IRQ1_POL4 0x0001029C
#define CS35L41_IRQ1_DB3 0x00010318
#define CS35L41_IRQ2_CFG 0x00010800
#define CS35L41_IRQ2_STATUS 0x00010804
#define CS35L41_IRQ2_STATUS1 0x00010810
#define CS35L41_IRQ2_STATUS2 0x00010814
#define CS35L41_IRQ2_STATUS3 0x00010818
#define CS35L41_IRQ2_STATUS4 0x0001081C
#define CS35L41_IRQ2_RAW_STATUS1 0x00010890
#define CS35L41_IRQ2_RAW_STATUS2 0x00010894
#define CS35L41_IRQ2_RAW_STATUS3 0x00010898
#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C
#define CS35L41_IRQ2_MASK1 0x00010910
#define CS35L41_IRQ2_MASK2 0x00010914
#define CS35L41_IRQ2_MASK3 0x00010918
#define CS35L41_IRQ2_MASK4 0x0001091C
#define CS35L41_IRQ2_FRC1 0x00010990
#define CS35L41_IRQ2_FRC2 0x00010994
#define CS35L41_IRQ2_FRC3 0x00010998
#define CS35L41_IRQ2_FRC4 0x0001099C
#define CS35L41_IRQ2_EDGE1 0x00010A10
#define CS35L41_IRQ2_EDGE4 0x00010A1C
#define CS35L41_IRQ2_POL1 0x00010A90
#define CS35L41_IRQ2_POL2 0x00010A94
#define CS35L41_IRQ2_POL3 0x00010A98
#define CS35L41_IRQ2_POL4 0x00010A9C
#define CS35L41_IRQ2_DB3 0x00010B18
#define CS35L41_GPIO_STATUS1 0x00011000
#define CS35L41_GPIO1_CTRL1 0x00011008
#define CS35L41_GPIO2_CTRL1 0x0001100C
#define CS35L41_MIXER_NGATE_CFG 0x00012000
#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004
#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008
#define CS35L41_DSP_MBOX_1 0x00013000
#define CS35L41_DSP_MBOX_2 0x00013004
#define CS35L41_DSP_MBOX_3 0x00013008
#define CS35L41_DSP_MBOX_4 0x0001300C
#define CS35L41_DSP_MBOX_5 0x00013010
#define CS35L41_DSP_MBOX_6 0x00013014
#define CS35L41_DSP_MBOX_7 0x00013018
#define CS35L41_DSP_MBOX_8 0x0001301C
#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020
#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024
#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028
#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C
#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030
#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034
#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038
#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C
#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040
#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044
#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048
#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C
#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050
#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054
#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058
#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C
#define CS35L41_CLOCK_DETECT_1 0x00014000
#define CS35L41_TIMER1_CONTROL 0x00015000
#define CS35L41_TIMER1_COUNT_PRESET 0x00015004
#define CS35L41_TIMER1_START_STOP 0x0001500C
#define CS35L41_TIMER1_STATUS 0x00015010
#define CS35L41_TIMER1_COUNT_READBACK 0x00015014
#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018
#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C
#define CS35L41_TIMER2_CONTROL 0x00015100
#define CS35L41_TIMER2_COUNT_PRESET 0x00015104
#define CS35L41_TIMER2_START_STOP 0x0001510C
#define CS35L41_TIMER2_STATUS 0x00015110
#define CS35L41_TIMER2_COUNT_READBACK 0x00015114
#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118
#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C
#define CS35L41_DFT_JTAG_CONTROL 0x00016000
#define CS35L41_DIE_STS1 0x00017040
#define CS35L41_DIE_STS2 0x00017044
#define CS35L41_TEMP_CAL1 0x00017048
#define CS35L41_TEMP_CAL2 0x0001704C
#define CS35L41_DSP1_XMEM_PACK_0 0x02000000
#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0
#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000
#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8
#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800
#define CS35L41_DSP1_SYS_ID 0x025E0000
#define CS35L41_DSP1_SYS_VERSION 0x025E0004
#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008
#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C
#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010
#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018
#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020
#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028
#define CS35L41_DSP1_SYS_FEATURES 0x025E002C
#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030
#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034
#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038
#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C
#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040
#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000
#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004
#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008
#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C
#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010
#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014
#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018
#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C
#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020
#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024
#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028
#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C
#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030
#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034
#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038
#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044
#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000
#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4
#define CS35L41_DSP1_CTRL_BASE 0x02B80000
#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010
#define CS35L41_DSP1_DEBUG 0x02B80040
#define CS35L41_DSP1_TIMER_CTRL 0x02B80048
#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050
#define CS35L41_DSP1_RX1_RATE 0x02B80080
#define CS35L41_DSP1_RX2_RATE 0x02B80088
#define CS35L41_DSP1_RX3_RATE 0x02B80090
#define CS35L41_DSP1_RX4_RATE 0x02B80098
#define CS35L41_DSP1_RX5_RATE 0x02B800A0
#define CS35L41_DSP1_RX6_RATE 0x02B800A8
#define CS35L41_DSP1_RX7_RATE 0x02B800B0
#define CS35L41_DSP1_RX8_RATE 0x02B800B8
#define CS35L41_DSP1_TX1_RATE 0x02B80280
#define CS35L41_DSP1_TX2_RATE 0x02B80288
#define CS35L41_DSP1_TX3_RATE 0x02B80290
#define CS35L41_DSP1_TX4_RATE 0x02B80298
#define CS35L41_DSP1_TX5_RATE 0x02B802A0
#define CS35L41_DSP1_TX6_RATE 0x02B802A8
#define CS35L41_DSP1_TX7_RATE 0x02B802B0
#define CS35L41_DSP1_TX8_RATE 0x02B802B8
#define CS35L41_DSP1_NMI_CTRL1 0x02B80480
#define CS35L41_DSP1_NMI_CTRL2 0x02B80488
#define CS35L41_DSP1_NMI_CTRL3 0x02B80490
#define CS35L41_DSP1_NMI_CTRL4 0x02B80498
#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0
#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8
#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0
#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8
#define CS35L41_DSP1_RESUME_CTRL 0x02B80500
#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508
#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510
#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518
#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520
#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528
#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530
#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538
#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540
#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548
#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550
#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558
#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560
#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568
#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570
#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578
#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580
#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588
#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590
#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598
#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0
#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8
#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0
#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8
#define CS35L41_DSP1_SCRATCH1 0x02B805C0
#define CS35L41_DSP1_SCRATCH2 0x02B805C8
#define CS35L41_DSP1_SCRATCH3 0x02B805D0
#define CS35L41_DSP1_SCRATCH4 0x02B805D8
#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000
#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008
#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000
#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008
#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010
#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018
#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020
#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078
#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0
#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8
#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0
#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8
#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0
#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138
#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180
#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188
#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C
#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190
#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194
#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198
#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C
#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0
#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4
#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8
#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC
#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0
#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4
#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8
#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC
#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0
#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4
#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8
#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC
#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0
#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4
#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8
#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC
#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0
#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4
#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8
#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC
#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0
#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4
#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8
#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC
#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200
#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204
#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000
#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004
#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008
#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C
#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014
#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018
#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C
#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020
#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024
#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C
#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030
#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034
#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038
#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C
#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044
#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048
#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C
#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050
#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054
#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C
#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100
#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104
#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108
#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C
#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110
#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114
#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140
#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180
#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000
#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004
#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008
#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010
#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014
#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018
#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020
#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024
#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028
#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030
#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034
#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038
#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040
#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044
#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048
#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050
#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054
#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058
#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060
#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064
#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068
#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070
#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074
#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078
#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200
#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204
#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208
#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C
#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210
#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214
#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218
#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C
#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220
#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224
#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228
#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C
#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230
#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234
#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238
#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C
#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400
#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404
#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408
#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C
#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410
#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414
#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418
#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C
#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420
#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424
#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428
#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C
#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430
#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434
#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438
#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C
#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600
#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604
#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608
#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610
#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614
#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618
#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620
#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624
#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628
#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630
#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634
#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638
#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640
#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644
#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648
#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650
#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654
#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658
#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660
#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664
#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668
#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670
#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674
#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678
#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00
#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08
#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000
#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004
#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008
#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010
#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014
#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018
#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C
#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020
#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024
#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028
#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C
#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030
#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034
#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038
#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040
#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000
#define CS35L41_DSP1_WDT_STATUS 0x02BC7008
#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000
#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0
#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000
#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8
#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000
#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4
#define CS35L41_DSP1_PMEM_0 0x03800000
#define CS35L41_DSP1_PMEM_5114 0x03804FE8
/*test regs for emulation bringup*/
#define CS35L41_PLL_OVR 0x00003018
#define CS35L41_BST_TEST_DUTY 0x00003900
#define CS35L41_DIGPWM_IOCTRL 0x0000706C
/*registers populated by OTP*/
#define CS35L41_OTP_TRIM_1 0x0000208c
#define CS35L41_OTP_TRIM_2 0x00002090
#define CS35L41_OTP_TRIM_3 0x00003010
#define CS35L41_OTP_TRIM_4 0x0000300C
#define CS35L41_OTP_TRIM_5 0x0000394C
#define CS35L41_OTP_TRIM_6 0x00003950
#define CS35L41_OTP_TRIM_7 0x00003954
#define CS35L41_OTP_TRIM_8 0x00003958
#define CS35L41_OTP_TRIM_9 0x0000395C
#define CS35L41_OTP_TRIM_10 0x0000416C
#define CS35L41_OTP_TRIM_11 0x00004160
#define CS35L41_OTP_TRIM_12 0x00004170
#define CS35L41_OTP_TRIM_13 0x00004360
#define CS35L41_OTP_TRIM_14 0x00004448
#define CS35L41_OTP_TRIM_15 0x0000444C
#define CS35L41_OTP_TRIM_16 0x00006E30
#define CS35L41_OTP_TRIM_17 0x00006E34
#define CS35L41_OTP_TRIM_18 0x00006E38
#define CS35L41_OTP_TRIM_19 0x00006E3C
#define CS35L41_OTP_TRIM_20 0x00006E40
#define CS35L41_OTP_TRIM_21 0x00006E44
#define CS35L41_OTP_TRIM_22 0x00006E48
#define CS35L41_OTP_TRIM_23 0x00006E4C
#define CS35L41_OTP_TRIM_24 0x00006E50
#define CS35L41_OTP_TRIM_25 0x00006E54
#define CS35L41_OTP_TRIM_26 0x00006E58
#define CS35L41_OTP_TRIM_27 0x00006E5C
#define CS35L41_OTP_TRIM_28 0x00006E60
#define CS35L41_OTP_TRIM_29 0x00006E64
#define CS35L41_OTP_TRIM_30 0x00007418
#define CS35L41_OTP_TRIM_31 0x0000741C
#define CS35L41_OTP_TRIM_32 0x00007434
#define CS35L41_OTP_TRIM_33 0x00007068
#define CS35L41_OTP_TRIM_34 0x0000410C
#define CS35L41_OTP_TRIM_35 0x0000400C
#define CS35L41_OTP_TRIM_36 0x00002030
#define CS35L41_MAX_CACHE_REG 0x0000006B
#define CS35L41_OTP_SIZE_WORDS 32
#define CS35L41_NUM_OTP_ELEM 100
#define CS35L41_NUM_OTP_MAPS 4
#define CS35L41_VALID_PDATA 0x80000000
#define CS35L41_SCLK_MSTR_MASK 0x10
#define CS35L41_SCLK_MSTR_SHIFT 4
#define CS35L41_LRCLK_MSTR_MASK 0x01
#define CS35L41_LRCLK_MSTR_SHIFT 0
#define CS35L41_SCLK_INV_MASK 0x40
#define CS35L41_SCLK_INV_SHIFT 6
#define CS35L41_LRCLK_INV_MASK 0x04
#define CS35L41_LRCLK_INV_SHIFT 2
#define CS35L41_SCLK_FRC_MASK 0x20
#define CS35L41_SCLK_FRC_SHIFT 5
#define CS35L41_LRCLK_FRC_MASK 0x02
#define CS35L41_LRCLK_FRC_SHIFT 1
#define CS35L41_AMP_GAIN_ZC_MASK 0x0400
#define CS35L41_AMP_GAIN_ZC_SHIFT 10
#define CS35L41_BST_CTL_MASK 0xFF
#define CS35L41_BST_CTL_SEL_MASK 0x03
#define CS35L41_BST_CTL_SEL_REG 0x00
#define CS35L41_BST_CTL_SEL_CLASSH 0x01
#define CS35L41_BST_IPK_MASK 0x7F
#define CS35L41_BST_IPK_SHIFT 0
#define CS35L41_BST_LIM_MASK 0x4
#define CS35L41_BST_LIM_SHIFT 2
#define CS35L41_BST_K1_MASK 0x000000FF
#define CS35L41_BST_K1_SHIFT 0
#define CS35L41_BST_K2_MASK 0x0000FF00
#define CS35L41_BST_K2_SHIFT 8
#define CS35L41_BST_SLOPE_MASK 0x0000FF00
#define CS35L41_BST_SLOPE_SHIFT 8
#define CS35L41_BST_LBST_VAL_MASK 0x00000003
#define CS35L41_BST_LBST_VAL_SHIFT 0
#define CS35L41_TEMP_THLD_MASK 0x03
#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF
#define CS35L41_PDM_MODE_MASK 0x01
#define CS35L41_PDM_MODE_SHIFT 0
#define CS35L41_CH_MEM_DEPTH_MASK 0x07
#define CS35L41_CH_MEM_DEPTH_SHIFT 0
#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000
#define CS35L41_CH_HDRM_CTL_SHIFT 16
#define CS35L41_CH_REL_RATE_MASK 0xFF00
#define CS35L41_CH_REL_RATE_SHIFT 8
#define CS35L41_CH_WKFET_DLY_MASK 0x001C
#define CS35L41_CH_WKFET_DLY_SHIFT 2
#define CS35L41_CH_WKFET_THLD_MASK 0x0F00
#define CS35L41_CH_WKFET_THLD_SHIFT 8
#define CS35L41_NG_ENABLE_MASK 0x00010000
#define CS35L41_NG_ENABLE_SHIFT 16
#define CS35L41_NG_THLD_MASK 0x7
#define CS35L41_NG_THLD_SHIFT 0
#define CS35L41_NG_DELAY_MASK 0x0F00
#define CS35L41_NG_DELAY_SHIFT 8
#define CS35L41_ASP_FMT_MASK 0x0700
#define CS35L41_ASP_FMT_SHIFT 8
#define CS35L41_ASP_DOUT_HIZ_MASK 0x03
#define CS35L41_ASP_DOUT_HIZ_SHIFT 0
#define CS35L41_ASP_WIDTH_16 0x10
#define CS35L41_ASP_WIDTH_24 0x18
#define CS35L41_ASP_WIDTH_32 0x20
#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000
#define CS35L41_ASP_WIDTH_TX_SHIFT 16
#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000
#define CS35L41_ASP_WIDTH_RX_SHIFT 24
#define CS35L41_ASP_RX1_SLOT_MASK 0x3F
#define CS35L41_ASP_RX1_SLOT_SHIFT 0
#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00
#define CS35L41_ASP_RX2_SLOT_SHIFT 8
#define CS35L41_ASP_RX_WL_MASK 0x3F
#define CS35L41_ASP_TX_WL_MASK 0x3F
#define CS35L41_ASP_RX_WL_SHIFT 0
#define CS35L41_ASP_TX_WL_SHIFT 0
#define CS35L41_ASP_SOURCE_MASK 0x7F
#define CS35L41_INPUT_SRC_ASPRX1 0x08
#define CS35L41_INPUT_SRC_ASPRX2 0x09
#define CS35L41_INPUT_SRC_VMON 0x18
#define CS35L41_INPUT_SRC_IMON 0x19
#define CS35L41_INPUT_SRC_CLASSH 0x21
#define CS35L41_INPUT_SRC_VPMON 0x28
#define CS35L41_INPUT_SRC_VBSTMON 0x29
#define CS35L41_INPUT_SRC_TEMPMON 0x3A
#define CS35L41_INPUT_SRC_RSVD 0x3B
#define CS35L41_INPUT_DSP_TX1 0x32
#define CS35L41_INPUT_DSP_TX2 0x33
#define CS35L41_PLL_CLK_SEL_MASK 0x07
#define CS35L41_PLL_CLK_SEL_SHIFT 0
#define CS35L41_PLL_CLK_EN_MASK 0x10
#define CS35L41_PLL_CLK_EN_SHIFT 4
#define CS35L41_PLL_OPENLOOP_MASK 0x0800
#define CS35L41_PLL_OPENLOOP_SHIFT 11
#define CS35L41_PLL_FORCE_EN_MASK 0x10000
#define CS35L41_PLL_FORCE_EN_SHIFT 16
#define CS35L41_PLLSRC_SCLK 0
#define CS35L41_PLLSRC_LRCLK 1
#define CS35L41_PLLSRC_SELF 3
#define CS35L41_PLLSRC_PDMCLK 4
#define CS35L41_PLLSRC_MCLK 5
#define CS35L41_PLLSRC_SWIRE 7
#define CS35L41_REFCLK_FREQ_MASK 0x7E0
#define CS35L41_REFCLK_FREQ_SHIFT 5
#define CS35L41_GLOBAL_FS_MASK 0x1F
#define CS35L41_GLOBAL_FS_SHIFT 0
#define CS35L41_GLOBAL_EN_MASK 0x01
#define CS35L41_GLOBAL_EN_SHIFT 0
#define CS35L41_BST_EN_MASK 0x0030
#define CS35L41_BST_EN_SHIFT 4
#define CS35L41_BST_EN_DEFAULT 0x2
#define CS35L41_PDN_DONE_MASK 0x00800000
#define CS35L41_PDN_DONE_SHIFT 23
#define CS35L41_PUP_DONE_MASK 0x01000000
#define CS35L41_PUP_DONE_SHIFT 24
#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F
#define CS35L36_PUP_DONE_IRQ_MASK 0xBF
#define CS35L41_AMP_SHORT_ERR 0x80000000
#define CS35L41_BST_SHORT_ERR 0x0100
#define CS35L41_TEMP_WARN 0x8000
#define CS35L41_TEMP_ERR 0x00020000
#define CS35L41_BST_OVP_ERR 0x40
#define CS35L41_BST_DCM_UVP_ERR 0x80
#define CS35L41_OTP_BOOT_DONE 0x02
#define CS35L41_PLL_UNLOCK 0x10
#define CS35L41_OTP_BOOT_ERR 0x80000000
#define CS35L41_AMP_SHORT_ERR_RLS 0x02
#define CS35L41_BST_SHORT_ERR_RLS 0x04
#define CS35L41_BST_OVP_ERR_RLS 0x08
#define CS35L41_BST_UVP_ERR_RLS 0x10
#define CS35L41_TEMP_WARN_ERR_RLS 0x20
#define CS35L41_TEMP_ERR_RLS 0x40
#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F
#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF
#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF
#define CS35L41_GPIO_DIR_MASK 0x80000000
#define CS35L41_GPIO1_CTRL_MASK 0x00030000
#define CS35L41_GPIO1_CTRL_SHIFT 16
#define CS35L41_GPIO2_CTRL_MASK 0x07000000
#define CS35L41_GPIO2_CTRL_SHIFT 24
#define CS35L41_GPIO_CTRL_ACTV_LO 4
#define CS35L41_GPIO_CTRL_ACTV_HI 5
#define CS35L41_GPIO_POL_MASK 0x1000
#define CS35L41_GPIO_POL_SHIFT 12
#define CS35L41_CHIP_ID 0x35a40
#define CS35L41R_CHIP_ID 0x35b40
#define CS35L41_MTLREVID_MASK 0x0F
#define CS35L41_REVID_A0 0xA0
#define CS35L41_REVID_B0 0xB0
#define CS35L41_REVID_B2 0xB2
#define CS35L41_DSP_N_RX_RATES 8
#define CS35L41_DSP_N_TX_RATES 8
#define CS35L41_HALO_CORE_RESET 0x00000200
#define CS35L41_FS1_WINDOW_MASK 0x000007FF
#define CS35L41_FS2_WINDOW_MASK 0x00FFF800
#define CS35L41_FS2_WINDOW_SHIFT 12
#define CS35L41_SPI_MAX_FREQ_OTP 4000000
#define CS35L41_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
#define CS35L41_TX_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
bool cs35l41_readable_reg(struct device *dev, unsigned int reg);
bool cs35l41_precious_reg(struct device *dev, unsigned int reg);
bool cs35l41_volatile_reg(struct device *dev, unsigned int reg);
struct cs35l41_otp_packed_element_t {
u32 reg;
u8 shift;
u8 size;
};
struct cs35l41_otp_map_element_t {
u32 id;
u32 num_elements;
const struct cs35l41_otp_packed_element_t *map;
u32 bit_offset;
u32 word_offset;
};
extern const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG];
extern const struct cs35l41_otp_map_element_t
cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS];
#define CS35L41_REGSTRIDE 4
#define CS35L41_MBOXWAIT 100
#define CS35L41_BUFSIZE 64
#define CS35L41_DSP_VIRT1_MBOX_SHIFT 20
#define CS35L41_DSP_VIRT2_MBOX_SHIFT 21
#define CS35L41_CSPL_MBOX_STS CS35L41_DSP_MBOX_2
/* Firmware update following reg */
#define CS35L41_CSPL_MBOX_CMD_FW CS35L41_DSP_VIRT2_MBOX_1
#define CS35L41_CSPL_MBOX_CMD_FW_SHIFT CS35L41_DSP_VIRT2_MBOX_SHIFT
/* Driver update following reg */
#define CS35L41_CSPL_MBOX_CMD_DRV CS35L41_DSP_VIRT1_MBOX_1
#define CS35L41_CSPL_MBOX_CMD_DRV_SHIFT CS35L41_DSP_VIRT1_MBOX_SHIFT
#define CS35L41_AMP_MUTE_SHIFT 4
#define CS35L41_DC_CURRENT_THRESHOLD 3
enum cs35l41_cspl_mboxstate {
CSPL_MBOX_STS_RUNNING = 0,
CSPL_MBOX_STS_PAUSED = 1,
CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
};
enum cs35l41_cspl_mboxcmd {
CSPL_MBOX_CMD_NONE = 0,
CSPL_MBOX_CMD_PAUSE = 1,
CSPL_MBOX_CMD_RESUME = 2,
CSPL_MBOX_CMD_REINIT = 3,
CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
};
enum cs35l41_cspl_cmd {
CSPL_CMD_NONE = 0,
CSPL_CMD_MUTE = 1,
CSPL_CMD_UNMUTE = 2,
CSPL_CMD_UPDATE_PARAM = 8,
};
enum cs35l41_cspl_st {
CSPL_ST_RUNNING = 0,
CSPL_ST_ERROR = 1,
CSPL_ST_MUTED = 2,
CSPL_ST_REINITING = 3,
CSPL_ST_DIAGNOSING = 6,
};
#endif /*__CS35L41_H__*/

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techpack/audio/asoc/codecs/cs35l41/cs35l41.txt Executable file
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CS35L41 Speaker Amplifier
Required properties:
- compatible : "cirrus,cs35l41"
"cirrus,cs35l40"
- reg : the SPI chip select line for the device
- VA-supply, VP-supply : power supplies for the device,
as covered in
Documentation/devicetree/bindings/regulator/regulator.txt.
Optional properties:
- cirrus,sclk-force-output : Audio serial port SCLK force
output control. Forces the SCLK to continue to drive even
if no ASP_TXn channels are enabled.
- cirrus,lrclk-force-output : Audio serial port LRCLK force
output control. Forces the LRCLK to continue to drive even
if no ASP_TXn channels are enabled.
- cirrus,right-channel-amp : Boolean to determine which channel
the amplifier is to receive the audio data on. If present the
amplifier receives data on the right channel of I2S data.
If not present the amplifier receives data on the left
channel of I2S data
- cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the
boost converter's output voltage in mV. The range is from 2550 mV to
11000 mV with increments of 50 mV.
(Default) VP
Boost hardware configuration:
These three properties should be used together to specify the external
component configuration of the part. See section 4.3.6 of the datasheet
for details regarding how these values are used to configure the
digital boost converter's control loop.
- cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
Configures the peak current by monitoring the current through the boost FET.
Range starts at 1600 mA and goes to a maximum of 4500 mA with increments
of 50 mA.
(Default) 4.50 Amps
- cirrus,boost-ind-nanohenry : Boost inductor value, expressed in nH. Valid
values include 1000, 1200, 1500 and 2200.
- cirrus,boost-cap-microfarad : Total equivalent boost capacitance on the VBST
and VAMP pins, derated at 11 volts DC. The value must be rounded to the
nearest integer and expressed in uF.
- cirrus,amp-gain-zc : Boolean to determine whether to use the amplifier
gain-change zero-crossing feature. If the feature is enabled, any
user-controlled amplifier gain change will occur on a zero-crossing point.
(Default) Disabled
- cirrus,temp-warn-threshold : Amplifier overtemperature warning threshold.
Configures the threshold at which the overtemperature warning condition occurs.
When the threshold is met, the ovetemperature warning attenuation is applied
and the TEMP_WARN_EINT interrupt status bit is set.
If TEMP_WARN_MASK = 0, INTb is asserted.
0 = 105C
1 = 115C
2 = 125C (Default)
3 = 135C
- cirrus,noise-gate-enable : DSP Noise Gate feature. If present, noise
gate feature will be enabled.
- cirrus,noise-gate-threshold : Threshold of audio signal input which the
noise gate considers the input audio to be at a low enough level to be
valid to enter a noise gating state of operation.
0 = -66 dBFS
1 = -72 dBFS
2 = -78 dBFS
3 = -84 dBFS (default)
4 = -90 dBFS
5 = -96 dBFS
6 = -102 dBFS
7 = -108 dBFS
- cirrus,noise-gate-delay : Time that the incoming audio signal must be
below the noise gate threshold prior to entering a noise gated state
0 = 5 ms
1 = 10 ms
2 = 25 ms
3 = 50 ms (default)
4 = 100 ms
5 = 250 ms
6 = 500 ms
7 = 1 s
8 = 5 s
9 = 10 s
10 = 20 s
11 = 30 s
12 = 40 s
13 = 50 s
14 = 60 s
15 = 120 s
Optional H/G Algorithm sub-node:
The cs35l41 node can have a single "cirrus,classh-internal-algo" sub-node
that will disable automatic control of the internal H/G Algorithm.
It is strongly recommended that the Datasheet be referenced when adjusting
or using these Class H Algorithm controls over the internal Algorithm.
Serious damage can occur to the Device and surrounding components.
- cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm
See Section 4.4 Internal Class H Algorithm in the Datasheet.
If not used, the device manages the ClassH Algorithm internally.
Optional properties for the "cirrus,classh-internal-algo" Sub-node
Section 7.9 Boost Control
- cirrus,classh-bst-overide : Boolean
- cirrus,classh-bst-max-limit
Section 7.17 Class H, Weak-FET Control
- cirrus,classh-headroom
- cirrus,classh-release-rate
- cirrus,classh-mem-depth
- cirrus,classh-wk-fet-delay
- cirrus,classh-wk-fet-thld
Optional GPIO1 sub-node:
The cs35l41 node can have an single "cirrus,gpio-config1" sub-node for
configuring the GPIO1 pin.
- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO1
level is inverted. If this property is not present the level is not inverted.
- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO1 pin
is configured as an output. If this property is not present the
pin will be configured as an input.
- cirrus,gpio-src-select : Configures the function of the GPIO1 pin.
Note that the options are different from the GPIO2 pin.
0 = High Impedance (Default)
1 = GPIO
2 = Sync
3 = MCLK input
Optional GPIO2 sub-node:
The cs35l41 node can have an single "cirrus,gpio-config2" sub-node for
configuring the GPIO1 pin.
- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO2
level is inverted. If this property is not present the level is not inverted.
- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO2 pin
is configured as an output. If this property is not present the
pin will be configured as an input.
- cirrus,gpio-src-select : Configures the function of the GPIO2 pin.
Note that the options are different from the GPIO1 pin.
0 = High Impedance (Default)
1 = GPIO
2 = Open Drain INTB
3 = MCLK input
4 = Push-pull INTB (active low)
5 = Push-pull INT (active high)
Example:
cs35l41: cs35l41@2 {
compatible = "cirrus,cs35l41";
reg = <2>;
VA-supply = <&dummy_vreg>;
VP-supply = <&dummy_vreg>;
};

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techpack/audio/asoc/codecs/cs35l41/send_data_to_xlog.c Normal file
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#include "send_data_to_xlog.h"
#include <linux/debugfs.h>
char msg_format[] =
"{\"name\":\"dc_detection\",\"audio_event\":{\"dc_reason\":\"%s\"},\"dgt\":\"null\",\"audio_ext\":\"null\" }";
#define MAX_LEN 512
void send_DC_data_to_xlog(char *reason)
{
int ret = -1;
pr_info("%s: reason: %s", __func__, reason);
ret = xlog_send_int(reason);
if (ret < 0) {
pr_info("%s: failed", __func__);
} else {
pr_info("%s: success", __func__);
}
}
int xlog_send_int(char *reason)
{
int ret = 0;
char msg[512];
pr_info("%s: reason: %s", __func__, reason);
ret = xlog_format_msg_int(msg, reason);
if (ret < 0) {
return ret;
}
xlogchar_kwrite(msg, sizeof(msg));
pr_info("%s: send msg: %s", __func__, msg);
return ret;
}
int xlog_format_msg_int(char *msg, char *reason)
{
if (msg == NULL) {
pr_info("%s: the msg is NULL", __func__);
return -EINVAL;
}
pr_info("%s start", __func__);
snprintf(msg, MAX_LEN, msg_format, reason);
pr_info("%s end", __func__);
return 0;
}

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#ifndef SEND_DATA_TO_XLOG
#define SEND_DATA_TO_XLOG
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/cdev.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/uaccess.h>
#include <linux/sched.h>
#include <linux/ratelimit.h>
#include <asm/current.h>
#include <asm/div64.h>
#include <linux/kernel.h>
#include <linux/atomic.h>
#include <linux/poll.h>
extern ssize_t xlogchar_kwrite(const char __user *buf, size_t count);
void send_DC_data_to_xlog(char *reason);
int xlog_send_int(char *reason);
int xlog_format_msg_int(char *msg, char *reason);
#endif

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techpack/audio/asoc/codecs/cs35l41/wm_adsp.c Normal file
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techpack/audio/asoc/codecs/cs35l41/wm_adsp.h Normal file
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/*
* wm_adsp.h -- Wolfson ADSP support
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __WM_ADSP_H
#define __WM_ADSP_H
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/compress_driver.h>
#include "wmfw.h"
/* Return values for wm_adsp_compr_handle_irq */
#define WM_ADSP_COMPR_OK 0
#define WM_ADSP_COMPR_VOICE_TRIGGER 1
#define WM_ADSP2_REGION_0 BIT(0)
#define WM_ADSP2_REGION_1 BIT(1)
#define WM_ADSP2_REGION_2 BIT(2)
#define WM_ADSP2_REGION_3 BIT(3)
#define WM_ADSP2_REGION_4 BIT(4)
#define WM_ADSP2_REGION_5 BIT(5)
#define WM_ADSP2_REGION_6 BIT(6)
#define WM_ADSP2_REGION_7 BIT(7)
#define WM_ADSP2_REGION_8 BIT(8)
#define WM_ADSP2_REGION_9 BIT(9)
#define WM_ADSP2_REGION_1_9 \
(WM_ADSP2_REGION_1 | WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \
WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | WM_ADSP2_REGION_6 | \
WM_ADSP2_REGION_7 | WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9)
#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9)
struct wm_adsp_region {
int type;
unsigned int base;
};
struct wm_adsp_alg_region {
struct list_head list;
unsigned int alg;
int type;
unsigned int base;
};
struct wm_adsp_compr;
struct wm_adsp_compr_buf;
struct wm_adsp_buffer_region_def {
unsigned int mem_type;
unsigned int base_offset;
unsigned int size_offset;
};
struct wm_adsp_fw_caps {
u32 id;
struct snd_codec_desc desc;
int num_regions;
struct wm_adsp_buffer_region_def *region_defs;
};
struct wm_adsp_fw_defs {
const char *file;
const char *binfile;
bool fullname;
int compr_direction;
int num_caps;
struct wm_adsp_fw_caps *caps;
bool voice_trigger;
};
struct wm_adsp {
const char *part;
const char *name;
const char *fwf_name;
int rev;
int num;
int type;
bool ao_dsp;
const char *suffix;
struct device *dev;
struct regmap *regmap;
struct snd_soc_component *component;
struct wm_adsp_ops *ops;
unsigned int base;
int cal_z;
int ambient;
int cal_status;
int cal_chksum;
int block_bypass;
unsigned int base_sysinfo;
unsigned int sysclk_reg;
unsigned int sysclk_mask;
unsigned int sysclk_shift;
struct list_head alg_regions;
unsigned int fw_id;
unsigned int fw_id_version;
unsigned int fw_vendor_id;
const struct wm_adsp_region *mem;
int num_mems;
int fw;
int fw_ver;
bool no_preloader;
bool preloaded;
bool booted;
bool running;
int num_firmwares;
struct wm_adsp_fw_defs *firmwares;
struct snd_kcontrol_new fw_ctrl;
struct soc_enum fw_enum;
struct list_head ctl_list;
struct work_struct boot_work;
struct wm_adsp_compr *compr;
struct wm_adsp_compr_buf *buffer;
struct mutex pwr_lock;
unsigned int lock_regions;
bool unlock_all;
unsigned int n_rx_channels;
unsigned int n_tx_channels;
unsigned int chip_revid;
struct mutex *rate_lock;
u8 *rx_rate_cache;
u8 *tx_rate_cache;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_root;
char *wmfw_file_name;
char *bin_file_name;
#endif
};
#define WM_ADSP1(wname, num) \
SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, num, 0, NULL, 0, \
wm_adsp1_event, \
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD)
#define WM_ADSP2_PRELOAD_SWITCH(wname, num) \
SOC_SINGLE_EXT(wname " Preload Switch", SND_SOC_NOPM, num, 1, 0, \
wm_adsp2_preloader_get, wm_adsp2_preloader_put)
#define WM_ADSP2(wname, num, event_fn) \
SND_SOC_DAPM_SPK(wname " Preload", NULL), \
{ .id = snd_soc_dapm_supply, \
.name = wname " Preloader", \
.reg = SND_SOC_NOPM, \
.shift = num, \
.event = event_fn, \
.event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \
.subseq = 100, \
/* Ensure we run after SYSCLK supply widget */ }, \
{ \
.id = snd_soc_dapm_out_drv, .name = wname, \
.reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp2_event, \
.event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD \
}
#define WM_HALO(wname, num, event_fn) \
SND_SOC_DAPM_SPK(wname " Preload", NULL), \
{ .id = snd_soc_dapm_supply, \
.name = wname " Preloader", \
.reg = SND_SOC_NOPM, \
.shift = num, \
.event = event_fn, \
.event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \
.subseq = 100, \
/* Ensure we run after SYSCLK supply widget */ }, \
{ \
.id = snd_soc_dapm_out_drv, .name = wname, \
.reg = SND_SOC_NOPM, .shift = num, .event = wm_halo_event, \
.event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD \
}
extern const struct snd_kcontrol_new wm_adsp_fw_controls[];
int wm_adsp1_init(struct wm_adsp *dsp);
int wm_adsp2_init(struct wm_adsp *dsp);
void wm_adsp2_remove(struct wm_adsp *dsp);
int wm_adsp2_component_probe(struct wm_adsp *dsp,
struct snd_soc_component *component);
int wm_adsp2_component_remove(struct wm_adsp *dsp,
struct snd_soc_component *component);
void wm_adsp_queue_boot_work(struct wm_adsp *dsp);
int wm_vpu_setup_algs(struct wm_adsp *vpu);
int wm_vpu_init(struct wm_adsp *vpu);
int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock);
int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event);
int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event,
unsigned int freq);
int wm_adsp2_lock(struct wm_adsp *adsp, unsigned int regions);
irqreturn_t wm_adsp2_bus_error(struct wm_adsp *adsp);
irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp);
int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event);
int wm_halo_early_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
int wm_halo_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event);
int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream);
int wm_adsp_compr_free(struct snd_compr_stream *stream);
int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
struct snd_compr_params *params);
int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
struct snd_compr_caps *caps);
int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd);
int wm_adsp_compr_handle_irq(struct wm_adsp *dsp);
int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp);
int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
size_t count);
int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, const void *buf,
size_t len);
int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, void *buf,
size_t len);
#endif

230
techpack/audio/asoc/codecs/cs35l41/wmfw.h Normal file
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/*
* wmfw.h - Wolfson firmware format information
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __WMFW_H
#define __WMFW_H
#include <linux/types.h>
#define WMFW_MAX_ALG_NAME 256
#define WMFW_MAX_ALG_DESCR_NAME 256
#define WMFW_MAX_COEFF_NAME 256
#define WMFW_MAX_COEFF_DESCR_NAME 256
#define WMFW_CTL_FLAG_SYS 0x8000
#define WMFW_CTL_FLAG_VOLATILE 0x0004
#define WMFW_CTL_FLAG_WRITEABLE 0x0002
#define WMFW_CTL_FLAG_READABLE 0x0001
/* Non-ALSA coefficient types start at 0x1000 */
#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */
#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */
#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */
struct wmfw_header {
char magic[4];
__le32 len;
__le16 rev;
u8 core;
u8 ver;
} __packed;
struct wmfw_footer {
__le64 timestamp;
__le32 checksum;
} __packed;
struct wmfw_adsp1_sizes {
__le32 dm;
__le32 pm;
__le32 zm;
} __packed;
struct wmfw_adsp2_sizes {
__le32 xm;
__le32 ym;
__le32 pm;
__le32 zm;
} __packed;
struct wmfw_vpu_sizes {
__le32 dm;
} __packed;
struct wmfw_region {
union {
__be32 type;
__le32 offset;
};
__le32 len;
u8 data[];
} __packed;
struct wmfw_id_hdr {
__be32 core_id;
__be32 core_rev;
__be32 id;
__be32 ver;
} __packed;
struct wmfw_adsp1_id_hdr {
struct wmfw_id_hdr fw;
__be32 zm;
__be32 dm;
__be32 n_algs;
} __packed;
struct wmfw_adsp2_id_hdr {
struct wmfw_id_hdr fw;
__be32 zm;
__be32 xm;
__be32 ym;
__be32 n_algs;
} __packed;
struct wmfw_vpu_fwid_hdr {
__be32 id;
__be32 block_rev;
__be32 vendor_id;
__be32 firmware_id;
__be32 ver;
} __packed;
struct wmfw_vpu_id_hdr {
struct wmfw_vpu_fwid_hdr fw;
__be32 dm_base;
__be32 dm_size;
__be32 n_algs;
} __packed;
struct wmfw_halo_fwid_hdr {
__be32 core_id;
__be32 block_rev;
__be32 vendor_id;
__be32 id;
__be32 ver;
} __packed;
struct wmfw_halo_id_hdr {
struct wmfw_halo_fwid_hdr fw;
__be32 xm_base;
__be32 xm_size;
__be32 ym_base;
__be32 ym_size;
__be32 n_algs;
} __packed;
struct wmfw_alg_hdr {
__be32 id;
__be32 ver;
} __packed;
struct wmfw_adsp1_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 zm;
__be32 dm;
} __packed;
struct wmfw_adsp2_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 zm;
__be32 xm;
__be32 ym;
} __packed;
struct wmfw_vpu_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 dm_base;
__be32 dm_size;
} __packed;
struct wmfw_halo_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 xm_base;
__be32 xm_size;
__be32 ym_base;
__be32 ym_size;
} __packed;
struct wmfw_adsp_alg_data {
__le32 id;
u8 name[WMFW_MAX_ALG_NAME];
u8 descr[WMFW_MAX_ALG_DESCR_NAME];
__le32 ncoeff;
u8 data[];
} __packed;
struct wmfw_adsp_coeff_data {
struct {
__le16 offset;
__le16 type;
__le32 size;
} hdr;
u8 name[WMFW_MAX_COEFF_NAME];
u8 descr[WMFW_MAX_COEFF_DESCR_NAME];
__le16 ctl_type;
__le16 flags;
__le32 len;
u8 data[];
} __packed;
struct wmfw_coeff_hdr {
u8 magic[4];
__le32 len;
union {
__be32 rev;
__le32 ver;
};
union {
__be32 core;
__le32 core_ver;
};
u8 data[];
} __packed;
struct wmfw_coeff_item {
__le16 offset;
__le16 type;
__le32 id;
__le32 ver;
__le32 sr;
__le32 len;
u8 data[];
} __packed;
#define WMFW_ADSP1 1
#define WMFW_ADSP2 2
#define WMFW_HALO 4
#define WMFW_VPU 0x44
#define WMFW_ABSOLUTE 0xf0
#define WMFW_ALGORITHM_DATA 0xf2
#define WMFW_NAME_TEXT 0xfe
#define WMFW_INFO_TEXT 0xff
#define WMFW_ADSP1_PM 2
#define WMFW_ADSP1_DM 3
#define WMFW_ADSP1_ZM 4
#define WMFW_ADSP2_PM 2
#define WMFW_ADSP2_ZM 4
#define WMFW_ADSP2_XM 5
#define WMFW_ADSP2_YM 6
#define WMFW_HALO_PM_PACKED 0x10
#define WMFW_HALO_XM_PACKED 0x11
#define WMFW_HALO_YM_PACKED 0x12
#define WMFW_VPU_DM 0x20
#endif

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# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.19
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ CS35L41 ############
# for CS35L41 Codec
ifdef CONFIG_SND_SOC_CS35L41
CS35L41_OBJS += cs35l41.o
CS35L41_OBJS += cs35l41-i2c.o
CS35L41_OBJS += cs35l41-tables.o
CS35L41_OBJS += wm_adsp.o
CS35L41_OBJS += send_data_to_xlog.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
EXTRA_CFLAGS += $(INCS)
ifeq (y, $(filter y,\
$(CONFIG_MACH_XIAOMI_ALIOTH) \
$(CONFIG_MACH_XIAOMI_APOLLO) \
$(CONFIG_MACH_XIAOMI_CAS) \
$(CONFIG_MACH_XIAOMI_CMI) \
$(CONFIG_MACH_XIAOMI_DAGU) \
$(CONFIG_MACH_XIAOMI_ENUMA) \
$(CONFIG_MACH_XIAOMI_THYME) \
$(CONFIG_MACH_XIAOMI_UMI)))
CDEFINES += -DCONFIG_AUDIO_SMARTPA_STEREO
endif
# PA STANDBY
ifeq ($(CONFIG_MACH_XIAOMI_DAGU), y)
CDEFINES += -DAUDIO_SMART_PA_STANDBY_SUPPORT
endif
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_CS35L41) += cs35l41_dlkm.o
cs35l41_dlkm-y := $(CS35L41_OBJS)

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118
techpack/audio/asoc/codecs/cs35l41_k81/cs35l41-i2c.c Normal file
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/*
* cs35l41-i2c.c -- CS35l41 I2C driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Author: David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/gpio.h>
#include "wm_adsp.h"
#include "cs35l41.h"
#include <sound/cs35l41_k81.h>
static struct regmap_config cs35l41_regmap_i2c = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct i2c_device_id cs35l41_id_i2c[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{},
};
MODULE_DEVICE_TABLE(i2c, cs35l41_id_i2c);
static int cs35l41_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct cs35l41_private *cs35l41;
struct device *dev = &client->dev;
struct cs35l41_platform_data *pdata = dev_get_platdata(dev);
const struct regmap_config *regmap_config = &cs35l41_regmap_i2c;
int ret;
cs35l41 = devm_kzalloc(dev, sizeof(struct cs35l41_private), GFP_KERNEL);
if (cs35l41 == NULL)
return -ENOMEM;
mutex_init(&cs35l41->rate_lock);
cs35l41->dev = dev;
cs35l41->irq = client->irq;
cs35l41->bus_spi = false;
i2c_set_clientdata(client, cs35l41);
cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(cs35l41->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
return cs35l41_probe(cs35l41, pdata);
}
static int cs35l41_i2c_remove(struct i2c_client *client)
{
struct cs35l41_private *cs35l41 = i2c_get_clientdata(client);
return cs35l41_remove(cs35l41);
}
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
static struct i2c_driver cs35l41_i2c_driver = {
.driver = {
.name = "cs35l41",
.of_match_table = cs35l41_of_match,
},
.id_table = cs35l41_id_i2c,
.probe = cs35l41_i2c_probe,
.remove = cs35l41_i2c_remove,
};
module_i2c_driver(cs35l41_i2c_driver);
MODULE_DESCRIPTION("I2C CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
MODULE_LICENSE("GPL");

112
techpack/audio/asoc/codecs/cs35l41_k81/cs35l41-spi.c Normal file
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/*
* cs35l41-spi.c -- CS35l41 SPI driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Author: David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include "wm_adsp.h"
#include "cs35l41.h"
#include <sound/cs35l41_k81.h>
static struct regmap_config cs35l41_regmap_spi = {
.reg_bits = 32,
.val_bits = 32,
.pad_bits = 16,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct spi_device_id cs35l41_id_spi[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{},
};
MODULE_DEVICE_TABLE(spi, cs35l41_id_spi);
static int cs35l41_spi_probe(struct spi_device *spi)
{
const struct regmap_config *regmap_config = &cs35l41_regmap_spi;
struct cs35l41_platform_data *pdata = dev_get_platdata(&spi->dev);
struct cs35l41_private *cs35l41;
int ret;
cs35l41 = devm_kzalloc(&spi->dev, sizeof(struct cs35l41_private),
GFP_KERNEL);
if (cs35l41 == NULL)
return -ENOMEM;
mutex_init(&cs35l41->rate_lock);
spi_set_drvdata(spi, cs35l41);
cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
cs35l41->dev = &spi->dev;
cs35l41->irq = spi->irq;
cs35l41->bus_spi = true;
return cs35l41_probe(cs35l41, pdata);
}
static int cs35l41_spi_remove(struct spi_device *spi)
{
struct cs35l41_private *cs35l41 = spi_get_drvdata(spi);
return cs35l41_remove(cs35l41);
}
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
static struct spi_driver cs35l41_spi_driver = {
.driver = {
.name = "cs35l41",
.of_match_table = cs35l41_of_match,
},
.id_table = cs35l41_id_spi,
.probe = cs35l41_spi_probe,
.remove = cs35l41_spi_remove,
};
module_spi_driver(cs35l41_spi_driver);
MODULE_DESCRIPTION("SPI CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
MODULE_LICENSE("GPL");

997
techpack/audio/asoc/codecs/cs35l41_k81/cs35l41-tables.c Normal file
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/*
* cs35l41-tables.c -- CS35L41 ALSA SoC audio driver
*
* Copyright 2018 Cirrus Logic, Inc.
*
* Author: Brian Austin <brian.austin@cirrus.com>
* David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "cs35l41.h"
const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = {
{ CS35L41_TEST_KEY_CTL, 0x00000000 },
{ CS35L41_USER_KEY_CTL, 0x00000000 },
{ CS35L41_OTP_CTRL0, 0x00006418 },
{ CS35L41_OTP_CTRL1, 0x00000000 },
{ CS35L41_OTP_CTRL3, 0x00000000 },
{ CS35L41_OTP_CTRL4, 0x00000000 },
{ CS35L41_OTP_CTRL5, 0x00000030 },
{ CS35L41_OTP_CTRL6, 0x00000000 },
{ CS35L41_OTP_CTRL7, 0x00000000 },
{ CS35L41_OTP_CTRL8, 0x00000000 },
{ CS35L41_PWR_CTRL1, 0x00000000 },
{ CS35L41_PWR_CTRL3, 0x01000010 },
{ CS35L41_CTRL_OVRRIDE, 0x00000002 },
{ CS35L41_AMP_OUT_MUTE, 0x00000000 },
{ CS35L41_PROTECT_REL_ERR_IGN, 0x00000000 },
{ CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
{ CS35L41_JTAG_CONTROL, 0x00000000 },
{ CS35L41_PLL_CLK_CTRL, 0x00000010 },
{ CS35L41_DSP_CLK_CTRL, 0x00000003 },
{ CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
{ CS35L41_DATA_FS_SEL, 0x00000000 },
{ CS35L41_MDSYNC_EN, 0x00000200 },
{ CS35L41_MDSYNC_TX_ID, 0x00000000 },
{ CS35L41_MDSYNC_PWR_CTRL, 0x00000002 },
{ CS35L41_MDSYNC_DATA_TX, 0x00000000 },
{ CS35L41_MDSYNC_TX_STATUS, 0x00000002 },
{ CS35L41_MDSYNC_DATA_RX, 0x00000000 },
{ CS35L41_MDSYNC_RX_STATUS, 0x00000002 },
{ CS35L41_MDSYNC_ERR_STATUS, 0x00000000 },
{ CS35L41_MDSYNC_SYNC_PTE2, 0x00000000 },
{ CS35L41_MDSYNC_SYNC_PTE3, 0x00000000 },
{ CS35L41_MDSYNC_SYNC_MSM_STATUS, 0x00000000 },
{ CS35L41_BSTCVRT_VCTRL1, 0x00000000 },
{ CS35L41_BSTCVRT_VCTRL2, 0x00000001 },
{ CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
{ CS35L41_BSTCVRT_SFT_RAMP, 0x00000003 },
{ CS35L41_BSTCVRT_COEFF, 0x00002424 },
{ CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
{ CS35L41_BSTCVRT_SW_FREQ, 0x01008000 },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00002001 },
{ CS35L41_BSTCVRT_DCM_MODE_FORCE, 0x00000000 },
{ CS35L41_BSTCVRT_OVERVOLT_CTRL, 0x00000130 },
{ CS35L41_VI_VOL_POL, 0x08000800 },
{ CS35L41_DTEMP_WARN_THLD, 0x00000002 },
{ CS35L41_DTEMP_EN, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000001 },
{ CS35L41_SP_ENABLES, 0x00000000 },
{ CS35L41_SP_RATE_CTRL, 0x00000028 },
{ CS35L41_SP_FORMAT, 0x18180200 },
{ CS35L41_SP_HIZ_CTRL, 0x00000002 },
{ CS35L41_SP_FRAME_TX_SLOT, 0x03020100 },
{ CS35L41_SP_FRAME_RX_SLOT, 0x00000100 },
{ CS35L41_SP_TX_WL, 0x00000018 },
{ CS35L41_SP_RX_WL, 0x00000018 },
{ CS35L41_DAC_PCM1_SRC, 0x00000008 },
{ CS35L41_ASP_TX1_SRC, 0x00000018 },
{ CS35L41_ASP_TX2_SRC, 0x00000019 },
{ CS35L41_ASP_TX3_SRC, 0x00000020 },
{ CS35L41_ASP_TX4_SRC, 0x00000021 },
{ CS35L41_DSP1_RX1_SRC, 0x00000008 },
{ CS35L41_DSP1_RX2_SRC, 0x00000009 },
{ CS35L41_DSP1_RX3_SRC, 0x00000018 },
{ CS35L41_DSP1_RX4_SRC, 0x00000019 },
{ CS35L41_DSP1_RX5_SRC, 0x00000020 },
{ CS35L41_DSP1_RX6_SRC, 0x00000021 },
{ CS35L41_DSP1_RX7_SRC, 0x0000003A },
{ CS35L41_DSP1_RX8_SRC, 0x00000001 },
{ CS35L41_NGATE1_SRC, 0x00000008 },
{ CS35L41_NGATE2_SRC, 0x00000009 },
{ CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
{ CS35L41_VPBR_CFG, 0x02AA1905 },
{ CS35L41_VBBR_CFG, 0x02AA1905 },
{ CS35L41_VPBR_STATUS, 0x00000000 },
{ CS35L41_VBBR_STATUS, 0x00000000 },
{ CS35L41_OVERTEMP_CFG, 0x00000001 },
{ CS35L41_AMP_ERR_VOL, 0x00000000 },
{ CS35L41_VOL_STATUS_TO_DSP, 0x00000000 },
{ CS35L41_CLASSH_CFG, 0x000B0405 },
{ CS35L41_WKFET_CFG, 0x00000111 },
{ CS35L41_NG_CFG, 0x00000033 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000273 },
{ CS35L41_DAC_MSM_CFG, 0x00580000 },
{ CS35L41_GPIO1_CTRL1, 0xE1000001 },
{ CS35L41_GPIO2_CTRL1, 0xE1000001 },
{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },
{ CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
{ CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
{ CS35L41_CLOCK_DETECT_1, 0x00000000 },
{ CS35L41_TIMER1_CONTROL, 0x00000000 },
{ CS35L41_TIMER1_COUNT_PRESET, 0x00000000 },
{ CS35L41_TIMER1_START_STOP, 0x00000000 },
{ CS35L41_TIMER1_STATUS, 0x00000000 },
{ CS35L41_TIMER1_COUNT_READBACK, 0x00000000 },
{ CS35L41_TIMER1_DSP_CLK_CFG, 0x00000000 },
{ CS35L41_TIMER1_DSP_CLK_STATUS, 0x00000000 },
{ CS35L41_TIMER2_CONTROL, 0x00000000 },
{ CS35L41_TIMER2_COUNT_PRESET, 0x00000000 },
{ CS35L41_TIMER2_START_STOP, 0x00000000 },
{ CS35L41_TIMER2_STATUS, 0x00000000 },
{ CS35L41_TIMER2_COUNT_READBACK, 0x00000000 },
{ CS35L41_TIMER2_DSP_CLK_CFG, 0x00000000 },
{ CS35L41_TIMER2_DSP_CLK_STATUS, 0x00000000 },
{ CS35L41_DFT_JTAG_CONTROL, 0x00000000 },
{ CS35L41_DIE_STS1, 0x00000000 },
{ CS35L41_DIE_STS2, 0x00000000 },
{ CS35L41_TEMP_CAL1, 0x00000000 },
{ CS35L41_TEMP_CAL2, 0x00000000 },
};
bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_REVID:
case CS35L41_FABID:
case CS35L41_RELID:
case CS35L41_OTPID:
case CS35L41_TEST_KEY_CTL:
case CS35L41_USER_KEY_CTL:
case CS35L41_OTP_CTRL0:
case CS35L41_OTP_CTRL3:
case CS35L41_OTP_CTRL4:
case CS35L41_OTP_CTRL5:
case CS35L41_OTP_CTRL6:
case CS35L41_OTP_CTRL7:
case CS35L41_OTP_CTRL8:
case CS35L41_PWR_CTRL1:
case CS35L41_PWR_CTRL2:
case CS35L41_PWR_CTRL3:
case CS35L41_CTRL_OVRRIDE:
case CS35L41_AMP_OUT_MUTE:
case CS35L41_PROTECT_REL_ERR_IGN:
case CS35L41_GPIO_PAD_CONTROL:
case CS35L41_JTAG_CONTROL:
case CS35L41_DEVID_OTP:
case CS35L41_PLL_CLK_CTRL:
case CS35L41_DSP_CLK_CTRL:
case CS35L41_GLOBAL_CLK_CTRL:
case CS35L41_DATA_FS_SEL:
case CS35L41_MDSYNC_EN:
case CS35L41_MDSYNC_TX_ID:
case CS35L41_MDSYNC_PWR_CTRL:
case CS35L41_MDSYNC_DATA_TX:
case CS35L41_MDSYNC_TX_STATUS:
case CS35L41_MDSYNC_DATA_RX:
case CS35L41_MDSYNC_RX_STATUS:
case CS35L41_MDSYNC_ERR_STATUS:
case CS35L41_MDSYNC_SYNC_PTE2:
case CS35L41_MDSYNC_SYNC_PTE3:
case CS35L41_MDSYNC_SYNC_MSM_STATUS:
case CS35L41_BSTCVRT_VCTRL1:
case CS35L41_BSTCVRT_VCTRL2:
case CS35L41_BSTCVRT_PEAK_CUR:
case CS35L41_BSTCVRT_SFT_RAMP:
case CS35L41_BSTCVRT_COEFF:
case CS35L41_BSTCVRT_SLOPE_LBST:
case CS35L41_BSTCVRT_SW_FREQ:
case CS35L41_BSTCVRT_DCM_CTRL:
case CS35L41_BSTCVRT_DCM_MODE_FORCE:
case CS35L41_BSTCVRT_OVERVOLT_CTRL:
case CS35L41_VI_VOL_POL:
case CS35L41_DTEMP_WARN_THLD:
case CS35L41_DTEMP_CFG:
case CS35L41_DTEMP_EN:
case CS35L41_VPVBST_FS_SEL:
case CS35L41_SP_ENABLES:
case CS35L41_SP_RATE_CTRL:
case CS35L41_SP_FORMAT:
case CS35L41_SP_HIZ_CTRL:
case CS35L41_SP_FRAME_TX_SLOT:
case CS35L41_SP_FRAME_RX_SLOT:
case CS35L41_SP_TX_WL:
case CS35L41_SP_RX_WL:
case CS35L41_DAC_PCM1_SRC:
case CS35L41_ASP_TX1_SRC:
case CS35L41_ASP_TX2_SRC:
case CS35L41_ASP_TX3_SRC:
case CS35L41_ASP_TX4_SRC:
case CS35L41_DSP1_RX1_SRC:
case CS35L41_DSP1_RX2_SRC:
case CS35L41_DSP1_RX3_SRC:
case CS35L41_DSP1_RX4_SRC:
case CS35L41_DSP1_RX5_SRC:
case CS35L41_DSP1_RX6_SRC:
case CS35L41_DSP1_RX7_SRC:
case CS35L41_DSP1_RX8_SRC:
case CS35L41_NGATE1_SRC:
case CS35L41_NGATE2_SRC:
case CS35L41_AMP_DIG_VOL_CTRL:
case CS35L41_VPBR_CFG:
case CS35L41_VBBR_CFG:
case CS35L41_VPBR_STATUS:
case CS35L41_VBBR_STATUS:
case CS35L41_OVERTEMP_CFG:
case CS35L41_AMP_ERR_VOL:
case CS35L41_VOL_STATUS_TO_DSP:
case CS35L41_CLASSH_CFG:
case CS35L41_WKFET_CFG:
case CS35L41_NG_CFG:
case CS35L41_AMP_GAIN_CTRL:
case CS35L41_DAC_MSM_CFG:
case CS35L41_IRQ1_CFG:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ1_MASK1:
case CS35L41_IRQ1_MASK2:
case CS35L41_IRQ1_MASK3:
case CS35L41_IRQ1_MASK4:
case CS35L41_IRQ1_FRC1:
case CS35L41_IRQ1_FRC2:
case CS35L41_IRQ1_FRC3:
case CS35L41_IRQ1_FRC4:
case CS35L41_IRQ1_EDGE1:
case CS35L41_IRQ1_EDGE4:
case CS35L41_IRQ1_POL1:
case CS35L41_IRQ1_POL2:
case CS35L41_IRQ1_POL3:
case CS35L41_IRQ1_POL4:
case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_CFG:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_IRQ2_MASK1:
case CS35L41_IRQ2_MASK2:
case CS35L41_IRQ2_MASK3:
case CS35L41_IRQ2_MASK4:
case CS35L41_IRQ2_FRC1:
case CS35L41_IRQ2_FRC2:
case CS35L41_IRQ2_FRC3:
case CS35L41_IRQ2_FRC4:
case CS35L41_IRQ2_EDGE1:
case CS35L41_IRQ2_EDGE4:
case CS35L41_IRQ2_POL1:
case CS35L41_IRQ2_POL2:
case CS35L41_IRQ2_POL3:
case CS35L41_IRQ2_POL4:
case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
case CS35L41_GPIO1_CTRL1:
case CS35L41_GPIO2_CTRL1:
case CS35L41_MIXER_NGATE_CFG:
case CS35L41_MIXER_NGATE_CH1_CFG:
case CS35L41_MIXER_NGATE_CH2_CFG:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_CLOCK_DETECT_1:
case CS35L41_TIMER1_CONTROL:
case CS35L41_TIMER1_COUNT_PRESET:
case CS35L41_TIMER1_STATUS:
case CS35L41_TIMER1_COUNT_READBACK:
case CS35L41_TIMER1_DSP_CLK_CFG:
case CS35L41_TIMER1_DSP_CLK_STATUS:
case CS35L41_TIMER2_CONTROL:
case CS35L41_TIMER2_COUNT_PRESET:
case CS35L41_TIMER2_STATUS:
case CS35L41_TIMER2_COUNT_READBACK:
case CS35L41_TIMER2_DSP_CLK_CFG:
case CS35L41_TIMER2_DSP_CLK_STATUS:
case CS35L41_DFT_JTAG_CONTROL:
case CS35L41_DIE_STS1:
case CS35L41_DIE_STS2:
case CS35L41_TEMP_CAL1:
case CS35L41_TEMP_CAL2:
case CS35L41_DSP1_TIMESTAMP_COUNT:
case CS35L41_DSP1_SYS_ID:
case CS35L41_DSP1_SYS_VERSION:
case CS35L41_DSP1_SYS_CORE_ID:
case CS35L41_DSP1_SYS_AHB_ADDR:
case CS35L41_DSP1_SYS_XSRAM_SIZE:
case CS35L41_DSP1_SYS_YSRAM_SIZE:
case CS35L41_DSP1_SYS_PSRAM_SIZE:
case CS35L41_DSP1_SYS_PM_BOOT_SIZE:
case CS35L41_DSP1_SYS_FEATURES:
case CS35L41_DSP1_SYS_FIR_FILTERS:
case CS35L41_DSP1_SYS_LMS_FILTERS:
case CS35L41_DSP1_SYS_XM_BANK_SIZE:
case CS35L41_DSP1_SYS_YM_BANK_SIZE:
case CS35L41_DSP1_SYS_PM_BANK_SIZE:
case CS35L41_DSP1_AHBM_WIN0_CTRL0:
case CS35L41_DSP1_AHBM_WIN0_CTRL1:
case CS35L41_DSP1_AHBM_WIN1_CTRL0:
case CS35L41_DSP1_AHBM_WIN1_CTRL1:
case CS35L41_DSP1_AHBM_WIN2_CTRL0:
case CS35L41_DSP1_AHBM_WIN2_CTRL1:
case CS35L41_DSP1_AHBM_WIN3_CTRL0:
case CS35L41_DSP1_AHBM_WIN3_CTRL1:
case CS35L41_DSP1_AHBM_WIN4_CTRL0:
case CS35L41_DSP1_AHBM_WIN4_CTRL1:
case CS35L41_DSP1_AHBM_WIN5_CTRL0:
case CS35L41_DSP1_AHBM_WIN5_CTRL1:
case CS35L41_DSP1_AHBM_WIN6_CTRL0:
case CS35L41_DSP1_AHBM_WIN6_CTRL1:
case CS35L41_DSP1_AHBM_WIN7_CTRL0:
case CS35L41_DSP1_AHBM_WIN7_CTRL1:
case CS35L41_DSP1_AHBM_WIN_DBG_CTRL0:
case CS35L41_DSP1_AHBM_WIN_DBG_CTRL1:
case CS35L41_DSP1_DEBUG:
case CS35L41_DSP1_TIMER_CTRL:
case CS35L41_DSP1_RX1_RATE:
case CS35L41_DSP1_RX2_RATE:
case CS35L41_DSP1_RX3_RATE:
case CS35L41_DSP1_RX4_RATE:
case CS35L41_DSP1_RX5_RATE:
case CS35L41_DSP1_RX6_RATE:
case CS35L41_DSP1_RX7_RATE:
case CS35L41_DSP1_RX8_RATE:
case CS35L41_DSP1_TX1_RATE:
case CS35L41_DSP1_TX2_RATE:
case CS35L41_DSP1_TX3_RATE:
case CS35L41_DSP1_TX4_RATE:
case CS35L41_DSP1_TX5_RATE:
case CS35L41_DSP1_TX6_RATE:
case CS35L41_DSP1_TX7_RATE:
case CS35L41_DSP1_TX8_RATE:
case CS35L41_DSP1_NMI_CTRL1:
case CS35L41_DSP1_NMI_CTRL2:
case CS35L41_DSP1_NMI_CTRL3:
case CS35L41_DSP1_NMI_CTRL4:
case CS35L41_DSP1_NMI_CTRL5:
case CS35L41_DSP1_NMI_CTRL6:
case CS35L41_DSP1_NMI_CTRL7:
case CS35L41_DSP1_NMI_CTRL8:
case CS35L41_DSP1_RESUME_CTRL:
case CS35L41_DSP1_IRQ1_CTRL:
case CS35L41_DSP1_IRQ2_CTRL:
case CS35L41_DSP1_IRQ3_CTRL:
case CS35L41_DSP1_IRQ4_CTRL:
case CS35L41_DSP1_IRQ5_CTRL:
case CS35L41_DSP1_IRQ6_CTRL:
case CS35L41_DSP1_IRQ7_CTRL:
case CS35L41_DSP1_IRQ8_CTRL:
case CS35L41_DSP1_IRQ9_CTRL:
case CS35L41_DSP1_IRQ10_CTRL:
case CS35L41_DSP1_IRQ11_CTRL:
case CS35L41_DSP1_IRQ12_CTRL:
case CS35L41_DSP1_IRQ13_CTRL:
case CS35L41_DSP1_IRQ14_CTRL:
case CS35L41_DSP1_IRQ15_CTRL:
case CS35L41_DSP1_IRQ16_CTRL:
case CS35L41_DSP1_IRQ17_CTRL:
case CS35L41_DSP1_IRQ18_CTRL:
case CS35L41_DSP1_IRQ19_CTRL:
case CS35L41_DSP1_IRQ20_CTRL:
case CS35L41_DSP1_IRQ21_CTRL:
case CS35L41_DSP1_IRQ22_CTRL:
case CS35L41_DSP1_IRQ23_CTRL:
case CS35L41_DSP1_SCRATCH1:
case CS35L41_DSP1_SCRATCH2:
case CS35L41_DSP1_SCRATCH3:
case CS35L41_DSP1_SCRATCH4:
case CS35L41_DSP1_CCM_CORE_CTRL:
case CS35L41_DSP1_CCM_CLK_OVERRIDE:
case CS35L41_DSP1_XM_MSTR_EN:
case CS35L41_DSP1_XM_CORE_PRI:
case CS35L41_DSP1_XM_AHB_PACK_PL_PRI:
case CS35L41_DSP1_XM_AHB_UP_PL_PRI:
case CS35L41_DSP1_XM_ACCEL_PL0_PRI:
case CS35L41_DSP1_XM_NPL0_PRI:
case CS35L41_DSP1_YM_MSTR_EN:
case CS35L41_DSP1_YM_CORE_PRI:
case CS35L41_DSP1_YM_AHB_PACK_PL_PRI:
case CS35L41_DSP1_YM_AHB_UP_PL_PRI:
case CS35L41_DSP1_YM_ACCEL_PL0_PRI:
case CS35L41_DSP1_YM_NPL0_PRI:
case CS35L41_DSP1_PM_MSTR_EN:
case CS35L41_DSP1_PM_PATCH0_ADDR:
case CS35L41_DSP1_PM_PATCH0_EN:
case CS35L41_DSP1_PM_PATCH0_DATA_LO:
case CS35L41_DSP1_PM_PATCH0_DATA_HI:
case CS35L41_DSP1_PM_PATCH1_ADDR:
case CS35L41_DSP1_PM_PATCH1_EN:
case CS35L41_DSP1_PM_PATCH1_DATA_LO:
case CS35L41_DSP1_PM_PATCH1_DATA_HI:
case CS35L41_DSP1_PM_PATCH2_ADDR:
case CS35L41_DSP1_PM_PATCH2_EN:
case CS35L41_DSP1_PM_PATCH2_DATA_LO:
case CS35L41_DSP1_PM_PATCH2_DATA_HI:
case CS35L41_DSP1_PM_PATCH3_ADDR:
case CS35L41_DSP1_PM_PATCH3_EN:
case CS35L41_DSP1_PM_PATCH3_DATA_LO:
case CS35L41_DSP1_PM_PATCH3_DATA_HI:
case CS35L41_DSP1_PM_PATCH4_ADDR:
case CS35L41_DSP1_PM_PATCH4_EN:
case CS35L41_DSP1_PM_PATCH4_DATA_LO:
case CS35L41_DSP1_PM_PATCH4_DATA_HI:
case CS35L41_DSP1_PM_PATCH5_ADDR:
case CS35L41_DSP1_PM_PATCH5_EN:
case CS35L41_DSP1_PM_PATCH5_DATA_LO:
case CS35L41_DSP1_PM_PATCH5_DATA_HI:
case CS35L41_DSP1_PM_PATCH6_ADDR:
case CS35L41_DSP1_PM_PATCH6_EN:
case CS35L41_DSP1_PM_PATCH6_DATA_LO:
case CS35L41_DSP1_PM_PATCH6_DATA_HI:
case CS35L41_DSP1_PM_PATCH7_ADDR:
case CS35L41_DSP1_PM_PATCH7_EN:
case CS35L41_DSP1_PM_PATCH7_DATA_LO:
case CS35L41_DSP1_PM_PATCH7_DATA_HI:
case CS35L41_DSP1_MPU_XM_ACCESS0:
case CS35L41_DSP1_MPU_YM_ACCESS0:
case CS35L41_DSP1_MPU_WNDW_ACCESS0:
case CS35L41_DSP1_MPU_XREG_ACCESS0:
case CS35L41_DSP1_MPU_YREG_ACCESS0:
case CS35L41_DSP1_MPU_XM_ACCESS1:
case CS35L41_DSP1_MPU_YM_ACCESS1:
case CS35L41_DSP1_MPU_WNDW_ACCESS1:
case CS35L41_DSP1_MPU_XREG_ACCESS1:
case CS35L41_DSP1_MPU_YREG_ACCESS1:
case CS35L41_DSP1_MPU_XM_ACCESS2:
case CS35L41_DSP1_MPU_YM_ACCESS2:
case CS35L41_DSP1_MPU_WNDW_ACCESS2:
case CS35L41_DSP1_MPU_XREG_ACCESS2:
case CS35L41_DSP1_MPU_YREG_ACCESS2:
case CS35L41_DSP1_MPU_XM_ACCESS3:
case CS35L41_DSP1_MPU_YM_ACCESS3:
case CS35L41_DSP1_MPU_WNDW_ACCESS3:
case CS35L41_DSP1_MPU_XREG_ACCESS3:
case CS35L41_DSP1_MPU_YREG_ACCESS3:
case CS35L41_DSP1_MPU_XM_VIO_ADDR:
case CS35L41_DSP1_MPU_XM_VIO_STATUS:
case CS35L41_DSP1_MPU_YM_VIO_ADDR:
case CS35L41_DSP1_MPU_YM_VIO_STATUS:
case CS35L41_DSP1_MPU_PM_VIO_ADDR:
case CS35L41_DSP1_MPU_PM_VIO_STATUS:
case CS35L41_DSP1_MPU_LOCK_CONFIG:
case CS35L41_DSP1_MPU_WDT_RST_CTRL:
case CS35L41_DSP1_STRMARB_MSTR0_CFG0:
case CS35L41_DSP1_STRMARB_MSTR0_CFG1:
case CS35L41_DSP1_STRMARB_MSTR0_CFG2:
case CS35L41_DSP1_STRMARB_MSTR1_CFG0:
case CS35L41_DSP1_STRMARB_MSTR1_CFG1:
case CS35L41_DSP1_STRMARB_MSTR1_CFG2:
case CS35L41_DSP1_STRMARB_MSTR2_CFG0:
case CS35L41_DSP1_STRMARB_MSTR2_CFG1:
case CS35L41_DSP1_STRMARB_MSTR2_CFG2:
case CS35L41_DSP1_STRMARB_MSTR3_CFG0:
case CS35L41_DSP1_STRMARB_MSTR3_CFG1:
case CS35L41_DSP1_STRMARB_MSTR3_CFG2:
case CS35L41_DSP1_STRMARB_MSTR4_CFG0:
case CS35L41_DSP1_STRMARB_MSTR4_CFG1:
case CS35L41_DSP1_STRMARB_MSTR4_CFG2:
case CS35L41_DSP1_STRMARB_MSTR5_CFG0:
case CS35L41_DSP1_STRMARB_MSTR5_CFG1:
case CS35L41_DSP1_STRMARB_MSTR5_CFG2:
case CS35L41_DSP1_STRMARB_MSTR6_CFG0:
case CS35L41_DSP1_STRMARB_MSTR6_CFG1:
case CS35L41_DSP1_STRMARB_MSTR6_CFG2:
case CS35L41_DSP1_STRMARB_MSTR7_CFG0:
case CS35L41_DSP1_STRMARB_MSTR7_CFG1:
case CS35L41_DSP1_STRMARB_MSTR7_CFG2:
case CS35L41_DSP1_STRMARB_TX0_CFG0:
case CS35L41_DSP1_STRMARB_TX0_CFG1:
case CS35L41_DSP1_STRMARB_TX1_CFG0:
case CS35L41_DSP1_STRMARB_TX1_CFG1:
case CS35L41_DSP1_STRMARB_TX2_CFG0:
case CS35L41_DSP1_STRMARB_TX2_CFG1:
case CS35L41_DSP1_STRMARB_TX3_CFG0:
case CS35L41_DSP1_STRMARB_TX3_CFG1:
case CS35L41_DSP1_STRMARB_TX4_CFG0:
case CS35L41_DSP1_STRMARB_TX4_CFG1:
case CS35L41_DSP1_STRMARB_TX5_CFG0:
case CS35L41_DSP1_STRMARB_TX5_CFG1:
case CS35L41_DSP1_STRMARB_TX6_CFG0:
case CS35L41_DSP1_STRMARB_TX6_CFG1:
case CS35L41_DSP1_STRMARB_TX7_CFG0:
case CS35L41_DSP1_STRMARB_TX7_CFG1:
case CS35L41_DSP1_STRMARB_RX0_CFG0:
case CS35L41_DSP1_STRMARB_RX0_CFG1:
case CS35L41_DSP1_STRMARB_RX1_CFG0:
case CS35L41_DSP1_STRMARB_RX1_CFG1:
case CS35L41_DSP1_STRMARB_RX2_CFG0:
case CS35L41_DSP1_STRMARB_RX2_CFG1:
case CS35L41_DSP1_STRMARB_RX3_CFG0:
case CS35L41_DSP1_STRMARB_RX3_CFG1:
case CS35L41_DSP1_STRMARB_RX4_CFG0:
case CS35L41_DSP1_STRMARB_RX4_CFG1:
case CS35L41_DSP1_STRMARB_RX5_CFG0:
case CS35L41_DSP1_STRMARB_RX5_CFG1:
case CS35L41_DSP1_STRMARB_RX6_CFG0:
case CS35L41_DSP1_STRMARB_RX6_CFG1:
case CS35L41_DSP1_STRMARB_RX7_CFG0:
case CS35L41_DSP1_STRMARB_RX7_CFG1:
case CS35L41_DSP1_STRMARB_IRQ0_CFG0:
case CS35L41_DSP1_STRMARB_IRQ0_CFG1:
case CS35L41_DSP1_STRMARB_IRQ0_CFG2:
case CS35L41_DSP1_STRMARB_IRQ1_CFG0:
case CS35L41_DSP1_STRMARB_IRQ1_CFG1:
case CS35L41_DSP1_STRMARB_IRQ1_CFG2:
case CS35L41_DSP1_STRMARB_IRQ2_CFG0:
case CS35L41_DSP1_STRMARB_IRQ2_CFG1:
case CS35L41_DSP1_STRMARB_IRQ2_CFG2:
case CS35L41_DSP1_STRMARB_IRQ3_CFG0:
case CS35L41_DSP1_STRMARB_IRQ3_CFG1:
case CS35L41_DSP1_STRMARB_IRQ3_CFG2:
case CS35L41_DSP1_STRMARB_IRQ4_CFG0:
case CS35L41_DSP1_STRMARB_IRQ4_CFG1:
case CS35L41_DSP1_STRMARB_IRQ4_CFG2:
case CS35L41_DSP1_STRMARB_IRQ5_CFG0:
case CS35L41_DSP1_STRMARB_IRQ5_CFG1:
case CS35L41_DSP1_STRMARB_IRQ5_CFG2:
case CS35L41_DSP1_STRMARB_IRQ6_CFG0:
case CS35L41_DSP1_STRMARB_IRQ6_CFG1:
case CS35L41_DSP1_STRMARB_IRQ6_CFG2:
case CS35L41_DSP1_STRMARB_IRQ7_CFG0:
case CS35L41_DSP1_STRMARB_IRQ7_CFG1:
case CS35L41_DSP1_STRMARB_IRQ7_CFG2:
case CS35L41_DSP1_STRMARB_RESYNC_MSK:
case CS35L41_DSP1_STRMARB_ERR_STATUS:
case CS35L41_DSP1_INTPCTL_RES_STATIC:
case CS35L41_DSP1_INTPCTL_RES_DYN:
case CS35L41_DSP1_INTPCTL_NMI_CTRL:
case CS35L41_DSP1_INTPCTL_IRQ_INV:
case CS35L41_DSP1_INTPCTL_IRQ_MODE:
case CS35L41_DSP1_INTPCTL_IRQ_EN:
case CS35L41_DSP1_INTPCTL_IRQ_MSK:
case CS35L41_DSP1_INTPCTL_IRQ_ERR:
case CS35L41_DSP1_INTPCTL_IRQ_PEND:
case CS35L41_DSP1_INTPCTL_TESTBITS:
case CS35L41_DSP1_WDT_CONTROL:
case CS35L41_DSP1_WDT_STATUS:
case CS35L41_OTP_TRIM_1:
case CS35L41_OTP_TRIM_2:
case CS35L41_OTP_TRIM_3:
case CS35L41_OTP_TRIM_4:
case CS35L41_OTP_TRIM_5:
case CS35L41_OTP_TRIM_6:
case CS35L41_OTP_TRIM_7:
case CS35L41_OTP_TRIM_8:
case CS35L41_OTP_TRIM_9:
case CS35L41_OTP_TRIM_10:
case CS35L41_OTP_TRIM_11:
case CS35L41_OTP_TRIM_12:
case CS35L41_OTP_TRIM_13:
case CS35L41_OTP_TRIM_14:
case CS35L41_OTP_TRIM_15:
case CS35L41_OTP_TRIM_16:
case CS35L41_OTP_TRIM_17:
case CS35L41_OTP_TRIM_18:
case CS35L41_OTP_TRIM_19:
case CS35L41_OTP_TRIM_20:
case CS35L41_OTP_TRIM_21:
case CS35L41_OTP_TRIM_22:
case CS35L41_OTP_TRIM_23:
case CS35L41_OTP_TRIM_24:
case CS35L41_OTP_TRIM_25:
case CS35L41_OTP_TRIM_26:
case CS35L41_OTP_TRIM_27:
case CS35L41_OTP_TRIM_28:
case CS35L41_OTP_TRIM_29:
case CS35L41_OTP_TRIM_30:
case CS35L41_OTP_TRIM_31:
case CS35L41_OTP_TRIM_32:
case CS35L41_OTP_TRIM_33:
case CS35L41_OTP_TRIM_34:
case CS35L41_OTP_TRIM_35:
case CS35L41_OTP_TRIM_36:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
/*test regs*/
case CS35L41_PLL_OVR:
case CS35L41_BST_TEST_DUTY:
case CS35L41_DIGPWM_IOCTRL:
return true;
default:
return false;
}
}
bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
return false;
}
}
bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_SFT_RESET:
case CS35L41_FABID:
case CS35L41_REVID:
case CS35L41_DEVID_OTP:
case CS35L41_CTRL_OVRRIDE:
case CS35L41_DTEMP_EN:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ1_FRC1:
case CS35L41_IRQ1_FRC2:
case CS35L41_IRQ1_FRC3:
case CS35L41_IRQ1_FRC4:
case CS35L41_IRQ1_EDGE1:
case CS35L41_IRQ1_EDGE4:
case CS35L41_IRQ1_POL1:
case CS35L41_IRQ1_POL2:
case CS35L41_IRQ1_POL3:
case CS35L41_IRQ1_POL4:
case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_IRQ2_FRC1:
case CS35L41_IRQ2_FRC2:
case CS35L41_IRQ2_FRC3:
case CS35L41_IRQ2_FRC4:
case CS35L41_IRQ2_EDGE1:
case CS35L41_IRQ2_EDGE4:
case CS35L41_IRQ2_POL1:
case CS35L41_IRQ2_POL2:
case CS35L41_IRQ2_POL3:
case CS35L41_IRQ2_POL4:
case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
case CS35L41_OTP_TRIM_1:
case CS35L41_OTP_TRIM_2:
case CS35L41_OTP_TRIM_3:
case CS35L41_OTP_TRIM_4:
case CS35L41_OTP_TRIM_5:
case CS35L41_OTP_TRIM_6:
case CS35L41_OTP_TRIM_7:
case CS35L41_OTP_TRIM_8:
case CS35L41_OTP_TRIM_9:
case CS35L41_OTP_TRIM_10:
case CS35L41_OTP_TRIM_11:
case CS35L41_OTP_TRIM_12:
case CS35L41_OTP_TRIM_13:
case CS35L41_OTP_TRIM_14:
case CS35L41_OTP_TRIM_15:
case CS35L41_OTP_TRIM_16:
case CS35L41_OTP_TRIM_17:
case CS35L41_OTP_TRIM_18:
case CS35L41_OTP_TRIM_19:
case CS35L41_OTP_TRIM_20:
case CS35L41_OTP_TRIM_21:
case CS35L41_OTP_TRIM_22:
case CS35L41_OTP_TRIM_23:
case CS35L41_OTP_TRIM_24:
case CS35L41_OTP_TRIM_25:
case CS35L41_OTP_TRIM_26:
case CS35L41_OTP_TRIM_27:
case CS35L41_OTP_TRIM_28:
case CS35L41_OTP_TRIM_29:
case CS35L41_OTP_TRIM_30:
case CS35L41_OTP_TRIM_31:
case CS35L41_OTP_TRIM_32:
case CS35L41_OTP_TRIM_33:
case CS35L41_OTP_TRIM_34:
case CS35L41_OTP_TRIM_35:
case CS35L41_OTP_TRIM_36:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
return false;
}
}
static const struct cs35l41_otp_packed_element_t otp_map_1[] = {
/* addr shift size */
{ 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{ 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{ 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{ 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{ 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{ 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{ 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{ 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{ 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{ 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{ 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{ 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{ 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{ 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{ 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{ 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{ 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{ 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{ 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{ 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{ 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{ 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{ 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{ 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{ 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{ 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{ 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{ 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{ 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{ 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{ 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{ 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{ 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{ 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{ 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{ 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{ 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{ 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{ 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{ 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{ 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{ 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{ 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{ 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{ 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{ 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{ 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{ 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{ 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{ 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{ 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{ 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{ 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{ 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{ 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{ 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{ 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{ 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{ 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{ 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{ 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{ 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{ 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{ 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{ 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{ 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{ 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{ 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{ 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{ 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{ 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{ 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{ 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{ 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{ 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{ 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{ 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{ 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{ 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{ 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{ 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{ 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{ 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{ 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{ 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{ 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{ 0x00007434, 17, 1 }, /*FORCE_CAL*/
{ 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{ 0x00007068, 0, 9 }, /*MODIX*/
{ 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{ 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{ 0x00000000, 0, 1 }, /*extra bit*/
{ 0x00017040, 0, 8 }, /*X_COORDINATE*/
{ 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{ 0x00017040, 16, 8 }, /*WAFER_ID*/
{ 0x00017040, 24, 8 }, /*DVS*/
{ 0x00017044, 0, 24 }, /*LOT_NUMBER*/
};
static const struct cs35l41_otp_packed_element_t otp_map_2[] = {
/* addr shift size */
{ 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{ 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{ 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{ 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{ 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{ 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{ 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{ 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{ 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{ 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{ 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{ 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{ 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{ 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{ 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{ 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{ 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{ 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{ 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{ 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{ 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{ 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{ 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{ 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{ 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{ 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{ 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{ 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{ 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{ 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{ 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{ 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{ 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{ 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{ 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{ 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{ 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{ 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{ 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{ 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{ 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{ 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{ 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{ 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{ 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{ 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{ 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{ 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{ 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{ 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{ 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{ 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{ 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{ 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{ 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{ 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{ 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{ 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{ 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{ 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{ 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{ 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{ 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{ 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{ 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{ 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{ 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{ 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{ 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{ 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{ 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{ 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{ 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{ 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{ 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{ 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{ 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{ 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{ 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{ 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{ 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{ 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{ 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{ 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{ 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{ 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{ 0x00007434, 17, 1 }, /*FORCE_CAL*/
{ 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{ 0x00007068, 0, 9 }, /*MODIX*/
{ 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{ 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{ 0x00004000, 11, 1 }, /*VMON_POL*/
{ 0x00017040, 0, 8 }, /*X_COORDINATE*/
{ 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{ 0x00017040, 16, 8 }, /*WAFER_ID*/
{ 0x00017040, 24, 8 }, /*DVS*/
{ 0x00017044, 0, 24 }, /*LOT_NUMBER*/
};
const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = {
{
.devid_otp = CS35L41_CHIP_ID, /* unset by OTP */
.id = 0x01,
.map = otp_map_1,
.num_elements = ARRAY_SIZE(otp_map_1),
.bit_offset = 16,
.word_offset = 2,
},
{
.devid_otp = CS35L41_CHIP_ID, /* unset by OTP */
.id = 0x02,
.map = otp_map_2,
.num_elements = ARRAY_SIZE(otp_map_2),
.bit_offset = 16,
.word_offset = 2,
},
{
.devid_otp = 0, /* unset by OTP */
.id = 0x03,
.map = otp_map_2,
.num_elements = ARRAY_SIZE(otp_map_2),
.bit_offset = 16,
.word_offset = 2,
},
{
.devid_otp = CS35L41_CHIP_ID, /* unset by OTP */
.id = 0x06,
.map = otp_map_2,
.num_elements = ARRAY_SIZE(otp_map_2),
.bit_offset = 16,
.word_offset = 2,
},
{
.devid_otp = CS35L41_CHIP_ID, /* unset by OTP */
.id = 0x08,
.map = otp_map_1,
.num_elements = ARRAY_SIZE(otp_map_1),
.bit_offset = 16,
.word_offset = 2,
},
{
.devid_otp = CS35L41LV_CHIP_ID,
.id = 0x01,
.map = otp_map_1,
.num_elements = ARRAY_SIZE(otp_map_1),
.bit_offset = 16,
.word_offset = 4,
},
};
const struct cs35l41_otp_maps cs35l41_otp_maps = {
.map = cs35l41_otp_map_map,
.len = ARRAY_SIZE(cs35l41_otp_map_map),
};
const unsigned int cs35l41_ctl_cache_regs[CS35L41_CTRL_CACHE_SIZE] = {
CS35L41_DAC_PCM1_SRC, CS35L41_DSP1_RX1_SRC,
CS35L41_DSP1_RX2_SRC, CS35L41_ASP_TX1_SRC,
CS35L41_ASP_TX2_SRC, CS35L41_ASP_TX3_SRC,
CS35L41_ASP_TX4_SRC, CS35L41_SP_FRAME_TX_SLOT,
CS35L41_AMP_GAIN_CTRL, CS35L41_AMP_DIG_VOL_CTRL,
CS35L41_PWR_CTRL1, CS35L41_PWR_CTRL2,
CS35L41_BSTCVRT_VCTRL1, CS35L41_BSTCVRT_VCTRL2,
};
const struct cs35l41_otp_trim_region_t
cs35l41_trim_cache_regs[CS35L41_TRIM_CACHE_REGIONS] = {
{ 0x00002030, 1 }, { 0x0000208c, 2 }, { 0x0000300C, 1 },
{ 0x0000394C, 5 }, { 0x0000416C, 1 }, { 0x00004160, 1 },
{ 0x00004170, 1 }, { 0x00004360, 1 }, { 0x00004448, 2 },
{ 0x00006E30, 14 }, { 0x00007418, 2 }, { 0x00007434, 1 },
{ 0x00007068, 1 }, { 0x0000410C, 1 }, { 0x0000400C, 1 },
{ 0x00004000, 1 }, { 0x00017040, 2 },
};

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techpack/audio/asoc/codecs/cs35l41_k81/cs35l41.c Normal file
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techpack/audio/asoc/codecs/cs35l41_k81/cs35l41.h Normal file
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@@ -0,0 +1,842 @@
/*
* cs35l41.h -- CS35L41 ALSA SoC audio driver
*
* Copyright 2018 Cirrus Logic, Inc.
*
* Author: Brian Austin <brian.austin@cirrus.com>
* David Rhodes <david.rhodes@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __CS35L41_H__
#define __CS35L41_H__
#include <linux/regmap.h>
#define CS35L41_FIRSTREG 0x00000000
#define CS35L41_LASTREG 0x03804FE8
#define CS35L41_DEVID 0x00000000
#define CS35L41_REVID 0x00000004
#define CS35L41_FABID 0x00000008
#define CS35L41_RELID 0x0000000C
#define CS35L41_OTPID 0x00000010
#define CS35L41_SFT_RESET 0x00000020
#define CS35L41_TEST_KEY_CTL 0x00000040
#define CS35L41_USER_KEY_CTL 0x00000044
#define CS35L41_OTP_MEM0 0x00000400
#define CS35L41_OTP_MEM31 0x0000047C
#define CS35L41_OTP_CTRL0 0x00000500
#define CS35L41_OTP_CTRL1 0x00000504
#define CS35L41_OTP_CTRL3 0x00000508
#define CS35L41_OTP_CTRL4 0x0000050C
#define CS35L41_OTP_CTRL5 0x00000510
#define CS35L41_OTP_CTRL6 0x00000514
#define CS35L41_OTP_CTRL7 0x00000518
#define CS35L41_OTP_CTRL8 0x0000051C
#define CS35L41_PWR_CTRL1 0x00002014
#define CS35L41_PWR_CTRL2 0x00002018
#define CS35L41_PWR_CTRL3 0x0000201C
#define CS35L41_CTRL_OVRRIDE 0x00002020
#define CS35L41_AMP_OUT_MUTE 0x00002024
#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034
#define CS35L41_GPIO_PAD_CONTROL 0x0000242C
#define CS35L41_JTAG_CONTROL 0x00002438
#define CS35L41_DEVID_OTP 0x00002850
#define CS35L41_PWRMGT_CTL 0x00002900
#define CS35L41_WAKESRC_CTL 0x00002904
#define CS35L41_PWRMGT_STS 0x00002908
#define CS35L41_PLL_CLK_CTRL 0x00002C04
#define CS35L41_DSP_CLK_CTRL 0x00002C08
#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C
#define CS35L41_DATA_FS_SEL 0x00002C10
#define CS35L41_TST_FS_MON0 0x00002D10
#define CS35L41_MDSYNC_EN 0x00003400
#define CS35L41_MDSYNC_TX_ID 0x00003408
#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C
#define CS35L41_MDSYNC_DATA_TX 0x00003410
#define CS35L41_MDSYNC_TX_STATUS 0x00003414
#define CS35L41_MDSYNC_DATA_RX 0x0000341C
#define CS35L41_MDSYNC_RX_STATUS 0x00003420
#define CS35L41_MDSYNC_ERR_STATUS 0x00003424
#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528
#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C
#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C
#define CS35L41_BSTCVRT_VCTRL1 0x00003800
#define CS35L41_BSTCVRT_VCTRL2 0x00003804
#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808
#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C
#define CS35L41_BSTCVRT_COEFF 0x00003810
#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814
#define CS35L41_BSTCVRT_SW_FREQ 0x00003818
#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C
#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820
#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830
#define CS35L41_VI_VOL_POL 0x00004000
#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100
#define CS35L41_DTEMP_WARN_THLD 0x00004220
#define CS35L41_DTEMP_CFG 0x00004224
#define CS35L41_DTEMP_EN 0x00004308
#define CS35L41_VPVBST_FS_SEL 0x00004400
#define CS35L41_SP_ENABLES 0x00004800
#define CS35L41_SP_RATE_CTRL 0x00004804
#define CS35L41_SP_FORMAT 0x00004808
#define CS35L41_SP_HIZ_CTRL 0x0000480C
#define CS35L41_SP_FRAME_TX_SLOT 0x00004810
#define CS35L41_SP_FRAME_RX_SLOT 0x00004820
#define CS35L41_SP_TX_WL 0x00004830
#define CS35L41_SP_RX_WL 0x00004840
#define CS35L41_ASP_CONTROL4 0x00004854
#define CS35L41_DAC_PCM1_SRC 0x00004C00
#define CS35L41_ASP_TX1_SRC 0x00004C20
#define CS35L41_ASP_TX2_SRC 0x00004C24
#define CS35L41_ASP_TX3_SRC 0x00004C28
#define CS35L41_ASP_TX4_SRC 0x00004C2C
#define CS35L41_DSP1_RX1_SRC 0x00004C40
#define CS35L41_DSP1_RX2_SRC 0x00004C44
#define CS35L41_DSP1_RX3_SRC 0x00004C48
#define CS35L41_DSP1_RX4_SRC 0x00004C4C
#define CS35L41_DSP1_RX5_SRC 0x00004C50
#define CS35L41_DSP1_RX6_SRC 0x00004C54
#define CS35L41_DSP1_RX7_SRC 0x00004C58
#define CS35L41_DSP1_RX8_SRC 0x00004C5C
#define CS35L41_NGATE1_SRC 0x00004C60
#define CS35L41_NGATE2_SRC 0x00004C64
#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000
#define CS35L41_VPBR_CFG 0x00006404
#define CS35L41_VBBR_CFG 0x00006408
#define CS35L41_VPBR_STATUS 0x0000640C
#define CS35L41_VBBR_STATUS 0x00006410
#define CS35L41_OVERTEMP_CFG 0x00006414
#define CS35L41_AMP_ERR_VOL 0x00006418
#define CS35L41_VOL_STATUS_TO_DSP 0x00006450
#define CS35L41_CLASSH_CFG 0x00006800
#define CS35L41_WKFET_CFG 0x00006804
#define CS35L41_NG_CFG 0x00006808
#define CS35L41_AMP_GAIN_CTRL 0x00006C04
#define CS35L41_DAC_MSM_CFG 0x00007400
#define CS35L41_IRQ1_CFG 0x00010000
#define CS35L41_IRQ1_STATUS 0x00010004
#define CS35L41_IRQ1_STATUS1 0x00010010
#define CS35L41_IRQ1_STATUS2 0x00010014
#define CS35L41_IRQ1_STATUS3 0x00010018
#define CS35L41_IRQ1_STATUS4 0x0001001C
#define CS35L41_IRQ1_RAW_STATUS1 0x00010090
#define CS35L41_IRQ1_RAW_STATUS2 0x00010094
#define CS35L41_IRQ1_RAW_STATUS3 0x00010098
#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C
#define CS35L41_IRQ1_MASK1 0x00010110
#define CS35L41_IRQ1_MASK2 0x00010114
#define CS35L41_IRQ1_MASK3 0x00010118
#define CS35L41_IRQ1_MASK4 0x0001011C
#define CS35L41_IRQ1_FRC1 0x00010190
#define CS35L41_IRQ1_FRC2 0x00010194
#define CS35L41_IRQ1_FRC3 0x00010198
#define CS35L41_IRQ1_FRC4 0x0001019C
#define CS35L41_IRQ1_EDGE1 0x00010210
#define CS35L41_IRQ1_EDGE4 0x0001021C
#define CS35L41_IRQ1_POL1 0x00010290
#define CS35L41_IRQ1_POL2 0x00010294
#define CS35L41_IRQ1_POL3 0x00010298
#define CS35L41_IRQ1_POL4 0x0001029C
#define CS35L41_IRQ1_DB3 0x00010318
#define CS35L41_IRQ2_CFG 0x00010800
#define CS35L41_IRQ2_STATUS 0x00010804
#define CS35L41_IRQ2_STATUS1 0x00010810
#define CS35L41_IRQ2_STATUS2 0x00010814
#define CS35L41_IRQ2_STATUS3 0x00010818
#define CS35L41_IRQ2_STATUS4 0x0001081C
#define CS35L41_IRQ2_RAW_STATUS1 0x00010890
#define CS35L41_IRQ2_RAW_STATUS2 0x00010894
#define CS35L41_IRQ2_RAW_STATUS3 0x00010898
#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C
#define CS35L41_IRQ2_MASK1 0x00010910
#define CS35L41_IRQ2_MASK2 0x00010914
#define CS35L41_IRQ2_MASK3 0x00010918
#define CS35L41_IRQ2_MASK4 0x0001091C
#define CS35L41_IRQ2_FRC1 0x00010990
#define CS35L41_IRQ2_FRC2 0x00010994
#define CS35L41_IRQ2_FRC3 0x00010998
#define CS35L41_IRQ2_FRC4 0x0001099C
#define CS35L41_IRQ2_EDGE1 0x00010A10
#define CS35L41_IRQ2_EDGE4 0x00010A1C
#define CS35L41_IRQ2_POL1 0x00010A90
#define CS35L41_IRQ2_POL2 0x00010A94
#define CS35L41_IRQ2_POL3 0x00010A98
#define CS35L41_IRQ2_POL4 0x00010A9C
#define CS35L41_IRQ2_DB3 0x00010B18
#define CS35L41_GPIO_STATUS1 0x00011000
#define CS35L41_GPIO1_CTRL1 0x00011008
#define CS35L41_GPIO2_CTRL1 0x0001100C
#define CS35L41_MIXER_NGATE_CFG 0x00012000
#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004
#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008
#define CS35L41_DSP_MBOX_1 0x00013000
#define CS35L41_DSP_MBOX_2 0x00013004
#define CS35L41_DSP_MBOX_3 0x00013008
#define CS35L41_DSP_MBOX_4 0x0001300C
#define CS35L41_DSP_MBOX_5 0x00013010
#define CS35L41_DSP_MBOX_6 0x00013014
#define CS35L41_DSP_MBOX_7 0x00013018
#define CS35L41_DSP_MBOX_8 0x0001301C
#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020
#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024
#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028
#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C
#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030
#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034
#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038
#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C
#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040
#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044
#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048
#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C
#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050
#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054
#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058
#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C
#define CS35L41_CLOCK_DETECT_1 0x00014000
#define CS35L41_TIMER1_CONTROL 0x00015000
#define CS35L41_TIMER1_COUNT_PRESET 0x00015004
#define CS35L41_TIMER1_START_STOP 0x0001500C
#define CS35L41_TIMER1_STATUS 0x00015010
#define CS35L41_TIMER1_COUNT_READBACK 0x00015014
#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018
#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C
#define CS35L41_TIMER2_CONTROL 0x00015100
#define CS35L41_TIMER2_COUNT_PRESET 0x00015104
#define CS35L41_TIMER2_START_STOP 0x0001510C
#define CS35L41_TIMER2_STATUS 0x00015110
#define CS35L41_TIMER2_COUNT_READBACK 0x00015114
#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118
#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C
#define CS35L41_DFT_JTAG_CONTROL 0x00016000
#define CS35L41_DIE_STS1 0x00017040
#define CS35L41_DIE_STS2 0x00017044
#define CS35L41_TEMP_CAL1 0x00017048
#define CS35L41_TEMP_CAL2 0x0001704C
#define CS35L41_DSP1_XMEM_PACK_0 0x02000000
#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0
#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000
#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8
#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800
#define CS35L41_DSP1_SYS_ID 0x025E0000
#define CS35L41_DSP1_SYS_VERSION 0x025E0004
#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008
#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C
#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010
#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018
#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020
#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028
#define CS35L41_DSP1_SYS_FEATURES 0x025E002C
#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030
#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034
#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038
#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C
#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040
#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000
#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004
#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008
#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C
#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010
#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014
#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018
#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C
#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020
#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024
#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028
#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C
#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030
#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034
#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038
#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044
#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000
#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4
#define CS35L41_DSP1_CTRL_BASE 0x02B80000
#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010
#define CS35L41_DSP1_DEBUG 0x02B80040
#define CS35L41_DSP1_TIMER_CTRL 0x02B80048
#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050
#define CS35L41_DSP1_RX1_RATE 0x02B80080
#define CS35L41_DSP1_RX2_RATE 0x02B80088
#define CS35L41_DSP1_RX3_RATE 0x02B80090
#define CS35L41_DSP1_RX4_RATE 0x02B80098
#define CS35L41_DSP1_RX5_RATE 0x02B800A0
#define CS35L41_DSP1_RX6_RATE 0x02B800A8
#define CS35L41_DSP1_RX7_RATE 0x02B800B0
#define CS35L41_DSP1_RX8_RATE 0x02B800B8
#define CS35L41_DSP1_TX1_RATE 0x02B80280
#define CS35L41_DSP1_TX2_RATE 0x02B80288
#define CS35L41_DSP1_TX3_RATE 0x02B80290
#define CS35L41_DSP1_TX4_RATE 0x02B80298
#define CS35L41_DSP1_TX5_RATE 0x02B802A0
#define CS35L41_DSP1_TX6_RATE 0x02B802A8
#define CS35L41_DSP1_TX7_RATE 0x02B802B0
#define CS35L41_DSP1_TX8_RATE 0x02B802B8
#define CS35L41_DSP1_NMI_CTRL1 0x02B80480
#define CS35L41_DSP1_NMI_CTRL2 0x02B80488
#define CS35L41_DSP1_NMI_CTRL3 0x02B80490
#define CS35L41_DSP1_NMI_CTRL4 0x02B80498
#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0
#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8
#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0
#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8
#define CS35L41_DSP1_RESUME_CTRL 0x02B80500
#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508
#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510
#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518
#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520
#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528
#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530
#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538
#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540
#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548
#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550
#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558
#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560
#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568
#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570
#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578
#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580
#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588
#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590
#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598
#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0
#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8
#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0
#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8
#define CS35L41_DSP1_SCRATCH1 0x02B805C0
#define CS35L41_DSP1_SCRATCH2 0x02B805C8
#define CS35L41_DSP1_SCRATCH3 0x02B805D0
#define CS35L41_DSP1_SCRATCH4 0x02B805D8
#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000
#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008
#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000
#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008
#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010
#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018
#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020
#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078
#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0
#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8
#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0
#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8
#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0
#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138
#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180
#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188
#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C
#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190
#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194
#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198
#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C
#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0
#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4
#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8
#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC
#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0
#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4
#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8
#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC
#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0
#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4
#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8
#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC
#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0
#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4
#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8
#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC
#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0
#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4
#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8
#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC
#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0
#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4
#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8
#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC
#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200
#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204
#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000
#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004
#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008
#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C
#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014
#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018
#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C
#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020
#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024
#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C
#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030
#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034
#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038
#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C
#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044
#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048
#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C
#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050
#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054
#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C
#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100
#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104
#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108
#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C
#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110
#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114
#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140
#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180
#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000
#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004
#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008
#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010
#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014
#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018
#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020
#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024
#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028
#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030
#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034
#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038
#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040
#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044
#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048
#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050
#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054
#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058
#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060
#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064
#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068
#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070
#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074
#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078
#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200
#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204
#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208
#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C
#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210
#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214
#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218
#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C
#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220
#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224
#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228
#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C
#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230
#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234
#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238
#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C
#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400
#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404
#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408
#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C
#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410
#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414
#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418
#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C
#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420
#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424
#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428
#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C
#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430
#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434
#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438
#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C
#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600
#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604
#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608
#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610
#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614
#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618
#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620
#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624
#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628
#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630
#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634
#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638
#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640
#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644
#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648
#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650
#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654
#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658
#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660
#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664
#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668
#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670
#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674
#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678
#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00
#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08
#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000
#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004
#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008
#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010
#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014
#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018
#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C
#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020
#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024
#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028
#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C
#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030
#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034
#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038
#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040
#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000
#define CS35L41_DSP1_WDT_STATUS 0x02BC7008
#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000
#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0
#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000
#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8
#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000
#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4
#define CS35L41_DSP1_PMEM_0 0x03800000
#define CS35L41_DSP1_PMEM_5114 0x03804FE8
/*test regs for emulation bringup*/
#define CS35L41_PLL_OVR 0x00003018
#define CS35L41_BST_TEST_DUTY 0x00003900
#define CS35L41_DIGPWM_IOCTRL 0x0000706C
/*registers populated by OTP*/
#define CS35L41_OTP_TRIM_1 0x0000208c
#define CS35L41_OTP_TRIM_2 0x00002090
#define CS35L41_OTP_TRIM_3 0x00003010
#define CS35L41_OTP_TRIM_4 0x0000300C
#define CS35L41_OTP_TRIM_5 0x0000394C
#define CS35L41_OTP_TRIM_6 0x00003950
#define CS35L41_OTP_TRIM_7 0x00003954
#define CS35L41_OTP_TRIM_8 0x00003958
#define CS35L41_OTP_TRIM_9 0x0000395C
#define CS35L41_OTP_TRIM_10 0x0000416C
#define CS35L41_OTP_TRIM_11 0x00004160
#define CS35L41_OTP_TRIM_12 0x00004170
#define CS35L41_OTP_TRIM_13 0x00004360
#define CS35L41_OTP_TRIM_14 0x00004448
#define CS35L41_OTP_TRIM_15 0x0000444C
#define CS35L41_OTP_TRIM_16 0x00006E30
#define CS35L41_OTP_TRIM_17 0x00006E34
#define CS35L41_OTP_TRIM_18 0x00006E38
#define CS35L41_OTP_TRIM_19 0x00006E3C
#define CS35L41_OTP_TRIM_20 0x00006E40
#define CS35L41_OTP_TRIM_21 0x00006E44
#define CS35L41_OTP_TRIM_22 0x00006E48
#define CS35L41_OTP_TRIM_23 0x00006E4C
#define CS35L41_OTP_TRIM_24 0x00006E50
#define CS35L41_OTP_TRIM_25 0x00006E54
#define CS35L41_OTP_TRIM_26 0x00006E58
#define CS35L41_OTP_TRIM_27 0x00006E5C
#define CS35L41_OTP_TRIM_28 0x00006E60
#define CS35L41_OTP_TRIM_29 0x00006E64
#define CS35L41_OTP_TRIM_30 0x00007418
#define CS35L41_OTP_TRIM_31 0x0000741C
#define CS35L41_OTP_TRIM_32 0x00007434
#define CS35L41_OTP_TRIM_33 0x00007068
#define CS35L41_OTP_TRIM_34 0x0000410C
#define CS35L41_OTP_TRIM_35 0x0000400C
#define CS35L41_OTP_TRIM_36 0x00002030
#define CS35L41_MAX_CACHE_REG 0x0000006B
#define CS35L41_OTP_SIZE_WORDS 32
#define CS35L41_VALID_PDATA 0x80000000
#define CS35L41_SCLK_MSTR_MASK 0x10
#define CS35L41_SCLK_MSTR_SHIFT 4
#define CS35L41_LRCLK_MSTR_MASK 0x01
#define CS35L41_LRCLK_MSTR_SHIFT 0
#define CS35L41_SCLK_INV_MASK 0x40
#define CS35L41_SCLK_INV_SHIFT 6
#define CS35L41_LRCLK_INV_MASK 0x04
#define CS35L41_LRCLK_INV_SHIFT 2
#define CS35L41_SCLK_FRC_MASK 0x20
#define CS35L41_SCLK_FRC_SHIFT 5
#define CS35L41_LRCLK_FRC_MASK 0x02
#define CS35L41_LRCLK_FRC_SHIFT 1
#define CS35L41_AMP_GAIN_ZC_MASK 0x0400
#define CS35L41_AMP_GAIN_ZC_SHIFT 10
#define CS35L41_BST_CTL_MASK 0xFF
#define CS35L41_BST_CTL_SEL_MASK 0x03
#define CS35L41_BST_CTL_SEL_REG 0x00
#define CS35L41_BST_CTL_SEL_CLASSH 0x01
#define CS35L41_BST_IPK_MASK 0x7F
#define CS35L41_BST_IPK_SHIFT 0
#define CS35L41_BST_LIM_MASK 0x4
#define CS35L41_BST_LIM_SHIFT 2
#define CS35L41_BST_K1_MASK 0x000000FF
#define CS35L41_BST_K1_SHIFT 0
#define CS35L41_BST_K2_MASK 0x0000FF00
#define CS35L41_BST_K2_SHIFT 8
#define CS35L41_BST_SLOPE_MASK 0x0000FF00
#define CS35L41_BST_SLOPE_SHIFT 8
#define CS35L41_BST_LBST_VAL_MASK 0x00000003
#define CS35L41_BST_LBST_VAL_SHIFT 0
#define CS35L41_TEMP_THLD_MASK 0x03
#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF
#define CS35L41_PDM_MODE_MASK 0x01
#define CS35L41_PDM_MODE_SHIFT 0
#define CS35L41_CH_MEM_DEPTH_MASK 0x07
#define CS35L41_CH_MEM_DEPTH_SHIFT 0
#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000
#define CS35L41_CH_HDRM_CTL_SHIFT 16
#define CS35L41_CH_REL_RATE_MASK 0xFF00
#define CS35L41_CH_REL_RATE_SHIFT 8
#define CS35L41_CH_WKFET_DLY_MASK 0x001C
#define CS35L41_CH_WKFET_DLY_SHIFT 2
#define CS35L41_CH_WKFET_THLD_MASK 0x0F00
#define CS35L41_CH_WKFET_THLD_SHIFT 8
#define CS35L41_HW_NG_SEL_MASK 0x3F00
#define CS35L41_HW_NG_SEL_SHIFT 8
#define CS35L41_HW_NG_DLY_MASK 0x0070
#define CS35L41_HW_NG_DLY_SHIFT 4
#define CS35L41_HW_NG_THLD_MASK 0x0007
#define CS35L41_HW_NG_THLD_SHIFT 0
#define CS35L41_DSP_NG_ENABLE_MASK 0x00010000
#define CS35L41_DSP_NG_ENABLE_SHIFT 16
#define CS35L41_DSP_NG_THLD_MASK 0x7
#define CS35L41_DSP_NG_THLD_SHIFT 0
#define CS35L41_DSP_NG_DELAY_MASK 0x0F00
#define CS35L41_DSP_NG_DELAY_SHIFT 8
#define CS35L41_ASP_FMT_MASK 0x0700
#define CS35L41_ASP_FMT_SHIFT 8
#define CS35L41_ASP_DOUT_HIZ_MASK 0x03
#define CS35L41_ASP_DOUT_HIZ_SHIFT 0
#define CS35L41_ASP_WIDTH_16 0x10
#define CS35L41_ASP_WIDTH_24 0x18
#define CS35L41_ASP_WIDTH_32 0x20
#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000
#define CS35L41_ASP_WIDTH_TX_SHIFT 16
#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000
#define CS35L41_ASP_WIDTH_RX_SHIFT 24
#define CS35L41_ASP_RX1_SLOT_MASK 0x3F
#define CS35L41_ASP_RX1_SLOT_SHIFT 0
#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00
#define CS35L41_ASP_RX2_SLOT_SHIFT 8
#define CS35L41_ASP_RX_WL_MASK 0x3F
#define CS35L41_ASP_TX_WL_MASK 0x3F
#define CS35L41_ASP_RX_WL_SHIFT 0
#define CS35L41_ASP_TX_WL_SHIFT 0
#define CS35L41_ASP_SOURCE_MASK 0x7F
#define CS35L41_INPUT_SRC_ASPRX1 0x08
#define CS35L41_INPUT_SRC_ASPRX2 0x09
#define CS35L41_INPUT_SRC_VMON 0x18
#define CS35L41_INPUT_SRC_IMON 0x19
#define CS35L41_INPUT_SRC_CLASSH 0x21
#define CS35L41_INPUT_SRC_VPMON 0x28
#define CS35L41_INPUT_SRC_VBSTMON 0x29
#define CS35L41_INPUT_SRC_TEMPMON 0x3A
#define CS35L41_INPUT_SRC_RSVD 0x3B
#define CS35L41_INPUT_DSP_TX1 0x32
#define CS35L41_INPUT_DSP_TX2 0x33
#define CS35L41_PLL_CLK_SEL_MASK 0x07
#define CS35L41_PLL_CLK_SEL_SHIFT 0
#define CS35L41_PLL_CLK_EN_MASK 0x10
#define CS35L41_PLL_CLK_EN_SHIFT 4
#define CS35L41_PLL_OPENLOOP_MASK 0x0800
#define CS35L41_PLL_OPENLOOP_SHIFT 11
#define CS35L41_PLL_FORCE_EN_MASK 0x10000
#define CS35L41_PLL_FORCE_EN_SHIFT 16
#define CS35L41_PLLSRC_SCLK 0
#define CS35L41_PLLSRC_LRCLK 1
#define CS35L41_PLLSRC_SELF 3
#define CS35L41_PLLSRC_PDMCLK 4
#define CS35L41_PLLSRC_MCLK 5
#define CS35L41_PLLSRC_SWIRE 7
#define CS35L41_REFCLK_FREQ_MASK 0x7E0
#define CS35L41_REFCLK_FREQ_SHIFT 5
#define CS35L41_GLOBAL_FS_MASK 0x1F
#define CS35L41_GLOBAL_FS_SHIFT 0
#define CS35L41_GLOBAL_EN_MASK 0x01
#define CS35L41_GLOBAL_EN_SHIFT 0
#define CS35L41_BST_EN_MASK 0x0030
#define CS35L41_BST_EN_SHIFT 4
#define CS35L41_BST_EN_DEFAULT 0x2
#define CS35L41_PDN_DONE_MASK 0x00800000
#define CS35L41_PDN_DONE_SHIFT 23
#define CS35L41_PUP_DONE_MASK 0x01000000
#define CS35L41_PUP_DONE_SHIFT 24
#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F
#define CS35L36_PUP_DONE_IRQ_MASK 0xBF
#define CS35L41_AMP_SHORT_ERR 0x80000000
#define CS35L41_BST_SHORT_ERR 0x0100
#define CS35L41_TEMP_WARN 0x8000
#define CS35L41_TEMP_ERR 0x00020000
#define CS35L41_BST_OVP_ERR 0x40
#define CS35L41_BST_DCM_UVP_ERR 0x80
#define CS35L41_OTP_BOOT_DONE 0x02
#define CS35L41_PLL_UNLOCK 0x10
#define CS35L41_OTP_BOOT_ERR 0x80000000
#define CS35L41_AMP_SHORT_ERR_RLS 0x02
#define CS35L41_BST_SHORT_ERR_RLS 0x04
#define CS35L41_BST_OVP_ERR_RLS 0x08
#define CS35L41_BST_UVP_ERR_RLS 0x10
#define CS35L41_TEMP_WARN_ERR_RLS 0x20
#define CS35L41_TEMP_ERR_RLS 0x40
#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F
#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF
#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF
#define CS35L41_INT1_MASK_FORCE 0xFFFFFFFE
#define CS35L41_GPIO_DIR_MASK 0x80000000
#define CS35L41_GPIO1_CTRL_MASK 0x00030000
#define CS35L41_GPIO1_CTRL_SHIFT 16
#define CS35L41_GPIO2_CTRL_MASK 0x07000000
#define CS35L41_GPIO2_CTRL_SHIFT 24
#define CS35L41_GPIO_CTRL_ACTV_LO 4
#define CS35L41_GPIO_CTRL_ACTV_HI 5
#define CS35L41_GPIO_POL_MASK 0x1000
#define CS35L41_GPIO_POL_SHIFT 12
#define CS35L41_AMP_INV_PCM_SHIFT 14
#define CS35L41_AMP_INV_PCM_MASK (1 << CS35L41_AMP_INV_PCM_SHIFT)
#define CS35L41_AMP_PCM_VOL_SHIFT 3
#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3)
#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF
#define CS35L41_FILT_GLOBAL_OVR_MASK 0x4
#define CS35L41_CHIP_ID 0x35a40
#define CS35L41R_CHIP_ID 0x35b40
#define CS35L41LV_CHIP_ID 0x35a41
#define CS35L41_MTLREVID_MASK 0x0F
#define CS35L41_REVID_A0 0xA0
#define CS35L41_REVID_B0 0xB0
#define CS35L41_REVID_B2 0xB2
#define CS35L41_DSP_N_RX_RATES 8
#define CS35L41_DSP_N_TX_RATES 8
#define CS35L41_HALO_CORE_RESET 0x00000200
#define CS35L41_FS1_WINDOW_MASK 0x000007FF
#define CS35L41_FS2_WINDOW_MASK 0x00FFF800
#define CS35L41_FS2_WINDOW_SHIFT 12
#define CS35L41_SPI_MAX_FREQ_OTP 4000000
#define CS35L41_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
#define CS35L41_TX_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define CS35L41_MAX_AUTO_RAMP_TIMEOUT 65535
#define CS35L41_MAX_PCM_VOL 913
#define CS35L41_MAX_VOL_ATT 120
#define CS35L41_ZERO_PCM_VOL 817
#define CS35L41_OUTPUT_DEV_SPK 0
#define CS35L41_OUTPUT_DEV_RCV 1
bool cs35l41_readable_reg(struct device *dev, unsigned int reg);
bool cs35l41_precious_reg(struct device *dev, unsigned int reg);
bool cs35l41_volatile_reg(struct device *dev, unsigned int reg);
struct cs35l41_otp_packed_element_t {
u32 reg;
u8 shift;
u8 size;
};
struct cs35l41_otp_map_element_t {
u32 devid_otp;
u32 id;
u32 num_elements;
const struct cs35l41_otp_packed_element_t *map;
u32 bit_offset;
u32 word_offset;
};
struct cs35l41_otp_trim_region_t {
u32 reg;
u8 size;
};
struct cs35l41_otp_maps {
const struct cs35l41_otp_map_element_t *map;
int len;
};
extern const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG];
extern const struct cs35l41_otp_maps cs35l41_otp_maps;
#define CS35L41_REGSTRIDE 4
#define CS35L41_BUFSIZE 64
#define CS35L41_DSP_VIRT1_MBOX_SHIFT 20
#define CS35L41_DSP_VIRT2_MBOX_SHIFT 21
#define CS35L41_CSPL_MBOX_STS CS35L41_DSP_MBOX_2
/* Firmware update following reg */
#define CS35L41_CSPL_MBOX_CMD_FW CS35L41_DSP_VIRT2_MBOX_1
#define CS35L41_CSPL_MBOX_CMD_FW_SHIFT CS35L41_DSP_VIRT2_MBOX_SHIFT
/* Driver update following reg */
#define CS35L41_CSPL_MBOX_CMD_DRV CS35L41_DSP_VIRT1_MBOX_1
#define CS35L41_CSPL_MBOX_CMD_DRV_SHIFT CS35L41_DSP_VIRT1_MBOX_SHIFT
#define CS35L41_CTRL_CACHE_SIZE 14
#define CS35L41_TRIM_CACHE_REGIONS 18
#define CS35L41_TRIM_CACHE_SIZE 38
extern const unsigned int cs35l41_ctl_cache_regs[CS35L41_CTRL_CACHE_SIZE];
extern const struct cs35l41_otp_trim_region_t
cs35l41_trim_cache_regs[CS35L41_TRIM_CACHE_REGIONS];
enum cs35l41_cspl_mboxstate {
CSPL_MBOX_STS_RUNNING = 0,
CSPL_MBOX_STS_PAUSED = 1,
CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
CSPL_MBOX_STS_HIBERNATE = 3,
};
enum cs35l41_cspl_mboxcmd {
CSPL_MBOX_CMD_NONE = 0,
CSPL_MBOX_CMD_PAUSE = 1,
CSPL_MBOX_CMD_RESUME = 2,
CSPL_MBOX_CMD_REINIT = 3,
CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
CSPL_MBOX_CMD_HIBERNATE = 5,
CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
};
enum cs35l41_cspl_cmd {
CSPL_CMD_NONE = 0,
CSPL_CMD_MUTE = 1,
CSPL_CMD_UNMUTE = 2,
CSPL_CMD_UPDATE_PARAM = 8,
};
enum cs35l41_cspl_st {
CSPL_ST_RUNNING = 0,
CSPL_ST_ERROR = 1,
CSPL_ST_MUTED = 2,
CSPL_ST_REINITING = 3,
CSPL_ST_DIAGNOSING = 6,
};
enum cs35l41_hibernate_state {
CS35L41_HIBERNATE_AWAKE = 0,
CS35L41_HIBERNATE_STANDBY = 1,
CS35L41_HIBERNATE_NOT_LOADED = 2,
CS35L41_HIBERNATE_INCOMPATIBLE = 3,
};
#endif /*__CS35L41_H__*/

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techpack/audio/asoc/codecs/cs35l41_k81/cs35l41.txt Executable file
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CS35L41 Speaker Amplifier
Required properties:
- compatible : "cirrus,cs35l41"
"cirrus,cs35l40"
- reg : the SPI chip select line for the device
- VA-supply, VP-supply : power supplies for the device,
as covered in
Documentation/devicetree/bindings/regulator/regulator.txt.
Boost hardware configuration:
These three properties should be used together to specify the external
component configuration of the part. See section 4.3.6 of the datasheet
for details regarding how these values are used to configure the
digital boost converter's control loop.
- cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
Configures the peak current by monitoring the current through the boost FET.
Range starts at 1600 mA and goes to a maximum of 4500 mA with increments
of 50 mA.
(Default) 4.50 Amps
- cirrus,boost-ind-nanohenry : Boost inductor value, expressed in nH. Valid
values include 1000, 1200, 1500 and 2200.
- cirrus,boost-cap-microfarad : Total equivalent boost capacitance on the VBST
and VAMP pins, derated at 11 volts DC. The value must be rounded to the
nearest integer and expressed in uF.
Optional properties:
- cirrus,sclk-force-output : Audio serial port SCLK force
output control. Forces the SCLK to continue to drive even
if no ASP_TXn channels are enabled.
- cirrus,lrclk-force-output : Audio serial port LRCLK force
output control. Forces the LRCLK to continue to drive even
if no ASP_TXn channels are enabled.
- cirrus,right-channel-amp : Boolean to determine which channel
the amplifier is to receive the audio data on. If present the
amplifier receives data on the right channel of I2S data.
If not present the amplifier receives data on the left
channel of I2S data
- cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the
boost converter's output voltage in mV. The range is from 2550 mV to
11000 mV with increments of 50 mV.
(Default) VP
- cirrus,amp-gain-zc : Boolean to determine whether to use the amplifier
gain-change zero-crossing feature. If the feature is enabled, any
user-controlled amplifier gain change will occur on a zero-crossing point.
(Default) Disabled
- cirrus,asp-sdout-hiz : Audio serial port SDOUT Hi-Z control. Sets the Hi-Z
configuration for SDOUT pin of amplifier.
0 = Logic 0 during unused slots, and while all transmit channels disabled
1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled
2 = (Default) Logic 0 during unused slots, but Hi-Z while all transmit channels disabled
3 = Hi-Z during unused slots and while all transmit channels disabled
- cirrus,temp-warn-threshold : Amplifier overtemperature warning threshold.
Configures the threshold at which the overtemperature warning condition occurs.
When the threshold is met, the ovetemperature warning attenuation is applied
and the TEMP_WARN_EINT interrupt status bit is set.
If TEMP_WARN_MASK = 0, INTb is asserted.
0 = 105C
1 = 115C
2 = 125C (Default)
3 = 135C
- cirrus,hw-noise-gate-select : Hardware Noise Gate feature. Each bit selects
a different block for detection.
000000 - All noise gating functionality disabled
xxxxx1 - Amplifier noise gating detection enabled
xxxx1x - Boost converter DCM detection enabled
xxx1xx - VMON low power mode detection enabled
xx1xxx - IMON low power mode detection enabled
x1xxxx - VP brownout prevention detection enabled
1xxxxx - VBST brownout prevention detection enabled
- cirrus,hw-noise-gate-delay : Time that the incoming audio signal must be
below the noise gate threshold prior to entering a noise gated state
0 = 5 ms
1 = 10 ms
2 = 25 ms
3 = 50 ms (default)
4 = 100 ms
5 = 250 ms
6 = 500 ms
7 = 1 s
- cirrus,hw-noise-gate-threshold : Threshold of audio signal input which the
noise gate considers the input audio to be at a low enough level to be
valid to enter a noise gating state of operation.
0 = 0.654 mVpk
1 = 0.328 mVpk
2 = 0.164 mVpk
3 = 0.082 mVpk (default)
4 = 0.041 mVpk
5 = 0.021 mVpk
6 = 0.010 mVpk
7 = True zero data (no LSB dither)
- cirrus,dsp-noise-gate-enable : DSP Noise Gate feature. If present, noise
gate feature will be enabled.
- cirrus,dsp-noise-gate-threshold : Threshold of audio signal input which the
noise gate considers the input audio to be at a low enough level to be
valid to enter a noise gating state of operation.
0 = -66 dBFS
1 = -72 dBFS
2 = -78 dBFS
3 = -84 dBFS (default)
4 = -90 dBFS
5 = -96 dBFS
6 = -102 dBFS
7 = -108 dBFS
- cirrus,dsp-noise-gate-delay : Time that the incoming audio signal must be
below the noise gate threshold prior to entering a noise gated state
0 = 5 ms
1 = 10 ms
2 = 25 ms
3 = 50 ms (default)
4 = 100 ms
5 = 250 ms
6 = 500 ms
7 = 1 s
8 = 5 s
9 = 10 s
10 = 20 s
11 = 30 s
12 = 40 s
13 = 50 s
14 = 60 s
15 = 120 s
- cirrus,tuning-has-prefix : Add ALSA component name prefix to
DSP firmware tuning file name.
For example, if the AMP prefix is 'Left' and FW set to 'Protection'
the driver will look for a .bin file named
Left-cs35l41-dsp1-spk-prot.bin
- cirrus,fwname-use-revid : Add Rev ID prefix to DSP firmware file name.
For example, if FW is set to 'Protection'
CS35l41 Rev A: cs35l41-revA-dsp1-spk-prot.wmfw
CS35l41 Rev B0: cs35l41-revB0-dsp1-spk-prot.wmfw
CS35l41 Rev B2: cs35l41-revB2-dsp1-spk-prot.wmfw
- cirrus,fast-switch : Specify file names for Fast Use Case Switching DSP
feature. Files names are comma-separated strings.
- cirrus,invert-pcm : Inverts the polarity of the audio signal output from
the Class-D amplifier.
Optional H/G Algorithm sub-node:
The cs35l41 node can have a single "cirrus,classh-internal-algo" sub-node
that will disable automatic control of the internal H/G Algorithm.
It is strongly recommended that the Datasheet be referenced when adjusting
or using these Class H Algorithm controls over the internal Algorithm.
Serious damage can occur to the Device and surrounding components.
- cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm
See Section 4.4 Internal Class H Algorithm in the Datasheet.
If not used, the device manages the ClassH Algorithm internally.
Optional properties for the "cirrus,classh-internal-algo" Sub-node
Section 7.9 Boost Control
- cirrus,classh-bst-overide : Boolean
- cirrus,classh-bst-max-limit
Above two controls are unavailable for cs35l41l (Low voltage variant)
Section 7.17 Class H, Weak-FET Control
- cirrus,classh-headroom
- cirrus,classh-release-rate
- cirrus,classh-mem-depth
- cirrus,classh-wk-fet-delay
- cirrus,classh-wk-fet-thld
Optional GPIO1 sub-node:
The cs35l41 node can have an single "cirrus,gpio-config1" sub-node for
configuring the GPIO1 pin.
- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO1
level is inverted. If this property is not present the level is not inverted.
- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO1 pin
is configured as an output. If this property is not present the
pin will be configured as an input.
- cirrus,gpio-src-select : Configures the function of the GPIO1 pin.
Note that the options are different from the GPIO2 pin.
0 = High Impedance (Default)
1 = GPIO
2 = Sync
3 = MCLK input
Optional GPIO2 sub-node:
The cs35l41 node can have an single "cirrus,gpio-config2" sub-node for
configuring the GPIO1 pin.
- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO2
level is inverted. If this property is not present the level is not inverted.
- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO2 pin
is configured as an output. If this property is not present the
pin will be configured as an input.
- cirrus,gpio-src-select : Configures the function of the GPIO2 pin.
Note that the options are different from the GPIO1 pin.
0 = High Impedance (Default)
1 = GPIO
2 = Open Drain INTB
3 = MCLK input
4 = Push-pull INTB (active low)
5 = Push-pull INT (active high)
Example:
cs35l41: cs35l41@2 {
compatible = "cirrus,cs35l41";
reg = <2>;
VA-supply = <&dummy_vreg>;
VP-supply = <&dummy_vreg>;
cirrus,boost-peak-milliamp = <4500>;
cirrus,boost-ind-nanohenry = <1000>;
cirrus,boost-cap-microfarad = <15>;
cirrus,fast-switch = "sample_fast_switch1.txt", "sample_fast_switch2.txt";
};

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techpack/audio/asoc/codecs/cs35l41_k81/send_data_to_xlog.c Normal file
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#include "send_data_to_xlog.h"
#include <linux/debugfs.h>
char msg_format[] =
"{\"name\":\"DC detection\",\"audio_event\":{\"count\":\"%d\",\"reason\":\"%s\"},\"dgt\":\"null\",\"audio_ext\":\"null\" }";
#define MAX_LEN 512
void send_DC_data_to_xlog(int dc_current_cnt, char *reason)
{
int ret = -1;
pr_info("%s: dc_current_cnt: %d, reason: %s", __func__, dc_current_cnt,
reason);
ret = xlog_send_int(dc_current_cnt, reason);
if (ret < 0) {
pr_info("%s: failed", __func__);
} else {
pr_info("%s: success", __func__);
}
}
int xlog_send_int(int dc_current_cnt, char *reason)
{
int ret = 0;
char msg[512];
pr_info("%s: cs35l41->dc_current_cnt: %d, reason: %s", __func__,
dc_current_cnt, reason);
ret = xlog_format_msg_int(msg, dc_current_cnt, reason);
if (ret < 0) {
return ret;
}
xlogchar_kwrite(msg, sizeof(msg));
pr_info("%s: send msg: %s", __func__, msg);
return ret;
}
int xlog_format_msg_int(char *msg, int dc_current_cnt, char *reason)
{
if (msg == NULL) {
pr_info("%s: the msg is NULL", __func__);
return -EINVAL;
}
pr_info("%s start", __func__);
snprintf(msg, MAX_LEN, msg_format, dc_current_cnt, reason);
pr_info("%s end", __func__);
return 0;
}

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techpack/audio/asoc/codecs/cs35l41_k81/send_data_to_xlog.h Normal file
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#ifndef SEND_DATA_TO_XLOG
#define SEND_DATA_TO_XLOG
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/cdev.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/uaccess.h>
#include <linux/sched.h>
#include <linux/ratelimit.h>
#include <asm/current.h>
#include <asm/div64.h>
#include <linux/kernel.h>
#include <linux/atomic.h>
#include <linux/poll.h>
extern ssize_t xlogchar_kwrite(const char __user *buf, size_t count);
void send_DC_data_to_xlog(int dc_current_cnt, char *reason);
int xlog_send_int(int dc_current_cnt, char *reason);
int xlog_format_msg_int(char *msg, int dc_current_cnt, char *reason);
#endif

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techpack/audio/asoc/codecs/cs35l41_k81/wm_adsp.c Normal file
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245
techpack/audio/asoc/codecs/cs35l41_k81/wm_adsp.h Normal file
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/*
* wm_adsp.h -- Wolfson ADSP support
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __WM_ADSP_H
#define __WM_ADSP_H
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/compress_driver.h>
#include "wmfw.h"
/* Return values for wm_adsp_compr_handle_irq */
#define WM_ADSP_COMPR_OK 0
#define WM_ADSP_COMPR_VOICE_TRIGGER 1
#define WM_ADSP2_REGION_0 BIT(0)
#define WM_ADSP2_REGION_1 BIT(1)
#define WM_ADSP2_REGION_2 BIT(2)
#define WM_ADSP2_REGION_3 BIT(3)
#define WM_ADSP2_REGION_4 BIT(4)
#define WM_ADSP2_REGION_5 BIT(5)
#define WM_ADSP2_REGION_6 BIT(6)
#define WM_ADSP2_REGION_7 BIT(7)
#define WM_ADSP2_REGION_8 BIT(8)
#define WM_ADSP2_REGION_9 BIT(9)
#define WM_ADSP2_REGION_1_9 \
(WM_ADSP2_REGION_1 | WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \
WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | WM_ADSP2_REGION_6 | \
WM_ADSP2_REGION_7 | WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9)
#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9)
struct wm_adsp_region {
int type;
unsigned int base;
};
struct wm_adsp_alg_region {
struct list_head list;
unsigned int alg;
int type;
unsigned int base;
};
struct wm_adsp_compr;
struct wm_adsp_compr_buf;
struct wm_adsp_ops;
struct wm_adsp {
const char *part;
const char *name;
const char *fwf_name;
int rev;
int num;
int type;
struct device *dev;
struct regmap *regmap;
struct snd_soc_component *component;
struct wm_adsp_ops *ops;
unsigned int base;
unsigned int base_sysinfo;
unsigned int sysclk_reg;
unsigned int sysclk_mask;
unsigned int sysclk_shift;
// Speaker calibration parameters
int cal_ambient;
int cal_r;
int cal_status;
int cal_checksum;
struct list_head alg_regions;
unsigned int fw_id;
unsigned int fw_id_version;
unsigned int fw_vendor_id;
const struct wm_adsp_region *mem;
int num_mems;
int fw;
int fw_ver;
bool no_preloader;
bool preloaded;
bool booted;
bool running;
bool fatal_error;
bool tuning_has_prefix;
bool first_booting;
struct list_head ctl_list;
struct workqueue_struct *work_queue;
struct work_struct boot_work;
struct list_head compr_list;
struct list_head buffer_list;
struct mutex pwr_lock;
unsigned int lock_regions;
unsigned int n_rx_channels;
unsigned int n_tx_channels;
struct mutex *rate_lock;
u8 *rx_rate_cache;
u8 *tx_rate_cache;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_root;
char *wmfw_file_name;
char *bin_file_name;
#endif
unsigned int data_word_mask;
int data_word_size;
};
struct wm_adsp_ops {
unsigned int sys_config_size;
bool (*validate_version)(struct wm_adsp *dsp, unsigned int version);
unsigned int (*parse_sizes)(struct wm_adsp *dsp, const char *const file,
unsigned int pos,
const struct firmware *firmware);
int (*setup_algs)(struct wm_adsp *dsp);
unsigned int (*region_to_reg)(struct wm_adsp_region const *mem,
unsigned int offset);
void (*show_fw_status)(struct wm_adsp *dsp);
void (*stop_watchdog)(struct wm_adsp *dsp);
int (*enable_memory)(struct wm_adsp *dsp);
void (*disable_memory)(struct wm_adsp *dsp);
int (*lock_memory)(struct wm_adsp *dsp, unsigned int lock_regions);
int (*enable_core)(struct wm_adsp *dsp);
void (*disable_core)(struct wm_adsp *dsp);
int (*start_core)(struct wm_adsp *dsp);
void (*stop_core)(struct wm_adsp *dsp);
};
#define WM_ADSP_PRELOADER(wname, num, event_fn) \
{ \
.id = snd_soc_dapm_supply, .name = wname " Preloader", \
.reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \
.event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \
.subseq = 100, /* Ensure we run after SYSCLK supply widget */ \
}
#define WM_ADSP1(wname, num) \
SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, num, 0, NULL, 0, \
wm_adsp1_event, \
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD)
#define WM_ADSP2_PRELOAD_SWITCH(wname, num) \
SOC_SINGLE_EXT(wname " Preload Switch", SND_SOC_NOPM, num, 1, 0, \
wm_adsp2_preloader_get, wm_adsp2_preloader_put)
#define WM_ADSP2(wname, num, event_fn) \
SND_SOC_DAPM_SPK(wname " Preload", NULL), \
WM_ADSP_PRELOADER(wname, num, event_fn), \
{ \
.id = snd_soc_dapm_out_drv, .name = wname, \
.reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp_event, \
.event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD \
}
#define WM_HALO(wname, num, event_fn) WM_ADSP2(wname, num, event_fn)
#define WM_ADSP_FW_CONTROL(dspname, num) \
SOC_ENUM_EXT(dspname " Firmware", wm_adsp_fw_enum[num], \
wm_adsp_fw_get, wm_adsp_fw_put)
extern const struct soc_enum wm_adsp_fw_enum[];
int wm_adsp1_init(struct wm_adsp *dsp);
int wm_adsp2_init(struct wm_adsp *dsp);
void wm_adsp2_remove(struct wm_adsp *dsp);
int wm_adsp2_component_probe(struct wm_adsp *dsp,
struct snd_soc_component *component);
int wm_adsp2_component_remove(struct wm_adsp *dsp,
struct snd_soc_component *component);
void wm_adsp_queue_boot_work(struct wm_adsp *dsp);
int wm_vpu_init(struct wm_adsp *vpu);
int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock);
int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event);
int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
irqreturn_t wm_adsp2_bus_error(struct wm_adsp *adsp);
irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp);
irqreturn_t wm_halo_wdt_expire(int irq, void *data);
int wm_adsp_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event);
int wm_vpu_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event);
int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq);
int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream);
int wm_adsp_compr_free(struct snd_compr_stream *stream);
int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
struct snd_compr_params *params);
int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
struct snd_compr_caps *caps);
int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd);
int wm_adsp_compr_handle_irq(struct wm_adsp *dsp);
int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp);
int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
size_t count);
int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, const void *buf,
size_t len);
int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, void *buf,
size_t len);
void wm_adsp_boot_work(struct work_struct *work);
#endif

223
techpack/audio/asoc/codecs/cs35l41_k81/wmfw.h Normal file
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/*
* wmfw.h - Wolfson firmware format information
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __WMFW_H
#define __WMFW_H
#include <linux/types.h>
#define WMFW_MAX_ALG_NAME 256
#define WMFW_MAX_ALG_DESCR_NAME 256
#define WMFW_MAX_COEFF_NAME 256
#define WMFW_MAX_COEFF_DESCR_NAME 256
#define WMFW_CTL_FLAG_SYS 0x8000
#define WMFW_CTL_FLAG_VOLATILE 0x0004
#define WMFW_CTL_FLAG_WRITEABLE 0x0002
#define WMFW_CTL_FLAG_READABLE 0x0001
/* Non-ALSA coefficient types start at 0x1000 */
#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */
#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */
#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */
struct wmfw_header {
char magic[4];
__le32 len;
__le16 rev;
u8 core;
u8 ver;
} __packed;
struct wmfw_footer {
__le64 timestamp;
__le32 checksum;
} __packed;
struct wmfw_adsp1_sizes {
__le32 dm;
__le32 pm;
__le32 zm;
} __packed;
struct wmfw_adsp2_sizes {
__le32 xm;
__le32 ym;
__le32 pm;
__le32 zm;
} __packed;
struct wmfw_vpu_sizes {
__le32 dm;
} __packed;
struct wmfw_region {
union {
__be32 type;
__le32 offset;
};
__le32 len;
u8 data[];
} __packed;
struct wmfw_id_hdr {
__be32 core_id;
__be32 core_rev;
__be32 id;
__be32 ver;
} __packed;
struct wmfw_v3_id_hdr {
__be32 core_id;
__be32 block_rev;
__be32 vendor_id;
__be32 id;
__be32 ver;
} __packed;
struct wmfw_adsp1_id_hdr {
struct wmfw_id_hdr fw;
__be32 zm;
__be32 dm;
__be32 n_algs;
} __packed;
struct wmfw_adsp2_id_hdr {
struct wmfw_id_hdr fw;
__be32 zm;
__be32 xm;
__be32 ym;
__be32 n_algs;
} __packed;
struct wmfw_halo_id_hdr {
struct wmfw_v3_id_hdr fw;
__be32 xm_base;
__be32 xm_size;
__be32 ym_base;
__be32 ym_size;
__be32 n_algs;
} __packed;
struct wmfw_vpu_id_hdr {
struct wmfw_v3_id_hdr fw;
__be32 dm_base;
__be32 dm_size;
__be32 n_algs;
} __packed;
struct wmfw_alg_hdr {
__be32 id;
__be32 ver;
} __packed;
struct wmfw_adsp1_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 zm;
__be32 dm;
} __packed;
struct wmfw_adsp2_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 zm;
__be32 xm;
__be32 ym;
} __packed;
struct wmfw_vpu_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 dm_base;
__be32 dm_size;
} __packed;
struct wmfw_halo_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 xm_base;
__be32 xm_size;
__be32 ym_base;
__be32 ym_size;
} __packed;
struct wmfw_adsp_alg_data {
__le32 id;
u8 name[WMFW_MAX_ALG_NAME];
u8 descr[WMFW_MAX_ALG_DESCR_NAME];
__le32 ncoeff;
u8 data[];
} __packed;
struct wmfw_adsp_coeff_data {
struct {
__le16 offset;
__le16 type;
__le32 size;
} hdr;
u8 name[WMFW_MAX_COEFF_NAME];
u8 descr[WMFW_MAX_COEFF_DESCR_NAME];
__le16 ctl_type;
__le16 flags;
__le32 len;
u8 data[];
} __packed;
struct wmfw_coeff_hdr {
u8 magic[4];
__le32 len;
union {
__be32 rev;
__le32 ver;
};
union {
__be32 core;
__le32 core_ver;
};
u8 data[];
} __packed;
struct wmfw_coeff_item {
__le16 offset;
__le16 type;
__le32 id;
__le32 ver;
__le32 sr;
__le32 len;
u8 data[];
} __packed;
#define WMFW_ADSP1 1
#define WMFW_ADSP2 2
#define WMFW_HALO 4
#define WMFW_VPU 0x45
#define WMFW_ABSOLUTE 0xf0
#define WMFW_ALGORITHM_DATA 0xf2
#define WMFW_METADATA 0xfc
#define WMFW_NAME_TEXT 0xfe
#define WMFW_INFO_TEXT 0xff
#define WMFW_ADSP1_PM 2
#define WMFW_ADSP1_DM 3
#define WMFW_ADSP1_ZM 4
#define WMFW_ADSP2_PM 2
#define WMFW_ADSP2_ZM 4
#define WMFW_ADSP2_XM 5
#define WMFW_ADSP2_YM 6
#define WMFW_HALO_PM_PACKED 0x10
#define WMFW_HALO_XM_PACKED 0x11
#define WMFW_HALO_YM_PACKED 0x12
#define WMFW_VPU_DM 0x30
#endif

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# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.19
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
TFA_INC := -I$(AUDIO_ROOT)/asoc/codecs/tfa9874/inc
# for TFA9874 Amplifer
ifdef CONFIG_SND_SOC_TFA9874
TFA9874_OBJS += src/tfa98xx.o
TFA9874_OBJS += src/tfa_container.o
TFA9874_OBJS += src/tfa_dsp.o
TFA9874_OBJS += src/tfa_init.o
#TFA9874_OBJS += src/tfa_debug.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC) \
$(TFA_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__\
-DDEBUG
ifeq ($(CONFIG_MACH_XIAOMI_MUNCH), y)
CDEFINES += -DTFA_NON_DSP_SOLUTION
endif
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_TFA9874) += tfa98xx_dlkm.o
tfa98xx_dlkm-y := $(TFA9874_OBJS)

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
Linux kernel specific definitions used by code shared with
Linux/Windows user space.
*/
#ifndef __CONFIG_LINUX_KERNEL_INC__
#define __CONFIG_LINUX_KERNEL_INC__
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/crc32.h>
#include <linux/ftrace.h>
#define _ASSERT(e)
#define PRINT_ASSERT(e) \
if ((e)) \
printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
#if defined(CONFIG_TRACING) && defined(DEBUG)
#define tfa98xx_trace_printk(...) trace_printk(__VA_ARGS__)
#else
#define tfa98xx_trace_printk(...)
#endif
#endif /* __CONFIG_LINUX_KERNEL_INC__ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _DBGPRINT_H
#define _DBGPRINT_H
/* Debugging macro's. */
#ifndef DEBUG
#define DEBUG
#endif
#ifndef ASSERT
//#define ASSERT
#endif
//TODO wwwim
#ifndef _ASSERT
#define _ASSERT(e)
#endif
#ifndef PREFIX
#define PREFIX "tfa98xx: "
#define DRIVER_NAME "tfa98xx"
#endif
#ifdef __KERNEL__
#ifdef DEBUG
#define _DEBUG(level, fmt, va...) \
do { \
if (unlikely(debug >= (level))) \
printk(KERN_INFO PREFIX "%s:%d: " fmt, __func__, \
__LINE__, ##va); \
} while (0)
#else
#define _DEBUG(level, fmt, va...) \
do { \
} while (0)
#endif
#define MSG(fmt, va...) \
printk(KERN_INFO PREFIX "%s:%d: " fmt, __func__, __LINE__, ##va)
#define _ERRORMSG(fmt, va...) \
printk(KERN_ERR PREFIX "ERROR %s:%d: " fmt, __func__, __LINE__, ##va)
#define DEBUG0(x...) MSG(x)
#define DEBUG1(x...) _DEBUG(1, x)
#define DEBUG2(x...) _DEBUG(2, x)
#define DEBUG3(x...) _DEBUG(3, x)
#define ERRORMSG(x...) _ERRORMSG(x)
#define PRINT(x...) printk(x)
#define PRINT_ERROR(x...) printk(KERN_INFO PREFIX " **ERROR** " x)
#define PRINT_ASSERT(e) \
if ((e)) \
printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
#define PRINT_ENTRY DEBUG2("+[%s]\n", __func__)
#define PRINT_EXIT DEBUG2("-[%s]\n", __func__)
#ifdef ASSERT
#define assert(cond, action) \
do { \
if (unlikely(!(cond))) { \
DEBUG0("Assert: %s\n", #cond); \
action; \
} \
} while (0)
#else
#define assert(cond, action) \
do { \
} while (0)
#endif
#else /* __KERNEL__ */
#if defined(WIN32) || defined(_X64)
#include <stdio.h>
/* user mode */
#ifdef DEBUG
#define _DEBUGMSG(level, fmt, ...) \
printf(PREFIX "%s:%d: " fmt, __FUNCTION__, __LINE__, __VA_ARGS__);
#else
#define _DEBUGMSG(level, fmt, ...) \
do { \
} while (0)
#endif
#define _ERRORMSG(fmt, ...) \
printf(PREFIX "%s:%s:%d: " fmt, __FILE__, __FUNCTION__, __LINE__, \
__VA_ARGS__)
#define DEBUG0(...) MSG(__VA_ARGS__)
#define DEBUG1(...) _DEBUGMSG(1, __VA_ARGS__)
#define DEBUG2(...) _DEBUGMSG(2, __VA_ARGS__)
#define DEBUG3(...) _DEBUGMSG(3, __VA_ARGS__)
#define ERRORMSG(fmt, ...) _ERRORMSG(fmt, __VA_ARGS__)
#define PRINT(...) printf(__VA_ARGS__)
/*
# define PRINT(...) { FILE *stream; \
if((stream = freopen("tfa_tfa.txt", "ab+", stdout)) == NULL) exit(-1); \
printf(__VA_ARGS__); \
freopen( "CON", "ab+", stdout ); \
}
*/
#define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__)
#define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__)
#define PRINT_ASSERT(e) \
if ((e)) \
fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#elif defined(__CODE_RED)
#include "app_global.h"
#ifdef DEBUG
#define _DEBUG(level, fmt, va...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, va))
//printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va);
#else
#define _DEBUG(level, fmt, va...) \
do { \
} while (0)
#endif
#define MSG(fmt, ...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__))
//printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va)
//TB_TRACE_INF(TbTracePfx2(APP_PFX,TB_FUNC,"path=%s, chan=%u, muted=%s, vol=%d\n",
// path->isRecording ? "recording" : "playback",
// i,
// channelVol.currentMuteValue ? "YES" : "NO",
// channelVol.currentVolumeValue
// ));
//# define _ERRORMSG(fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va))
#define ERRORMSG(...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__))
//fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va)
#define DEBUG0(x...) MSG(x)
#define DEBUG1(x...) _DEBUG(1, x)
#define DEBUG2(x...) _DEBUG(2, x)
#define DEBUG3(x...) _DEBUG(3, x)
//# define ERRORMSG(x...) _ERRORMSG(x)
#define PRINT(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
//printf(x)
#define PRINT_ERROR(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
//fprintf(stderr,__VA_ARGS__)
#define PRINT_FILE(file, x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
//fprintf(file,__VA_ARGS__)
#define PRINT_ASSERT(e)
//TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,Tfa98xx_GetErrorString(e)))
//if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#else
#include <stdio.h>
/* user mode */
#ifdef DEBUG
#define _DEBUG(level, fmt, va...) \
printf(PREFIX "%s:%d: " fmt, __func__, __LINE__, ##va);
#else
#define _DEBUG(level, fmt, va...) \
do { \
} while (0)
#endif
#define MSG(fmt, va...) \
printf(PREFIX "%s:%s:%d: " fmt, __FILE__, __func__, __LINE__, ##va)
#define _ERRORMSG(fmt, va...) \
fprintf(stderr, PREFIX "ERROR %s:%s:%d: " fmt, __FILE__, __func__, \
__LINE__, ##va)
#define DEBUG0(x...) MSG(x)
#define DEBUG1(x...) _DEBUG(1, x)
#define DEBUG2(x...) _DEBUG(2, x)
#define DEBUG3(x...) _DEBUG(3, x)
#define ERRORMSG(x...) _ERRORMSG(x)
#define PRINT(x...) printf(x)
#define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__)
#define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__)
#define PRINT_ASSERT(e) \
if ((e)) \
fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#endif /* WIN32 */
#endif /* user */
#endif /* _DBGPRINT_H --------------- */

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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SPK_ID_H_
#define __SPK_ID_H_
#include <linux/types.h>
#include <linux/of.h>
#define PIN_PULL_DOWN 0
#define PIN_PULL_UP 1
#define PIN_FLOAT 2
#define VENDOR_ID_NONE 0
#define VENDOR_ID_AAC 1
#define VENDOR_ID_SSI 2
#define VENDOR_ID_GOER 3
#define VENDOR_ID_UNKNOWN 4
extern int spk_id_get_pin_3state(struct device_node *np);
#endif

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef TFA_H_
#define TFA_H_
/* set the limit for the container file length */
#define TFA_MAX_CNT_LENGTH (256 * 1024)
extern struct tfa_device **devs;
/**
* tfa error return codes
*/
enum tfa_error {
tfa_error_ok, /**< no error */
tfa_error_device, /**< no response from device */
tfa_error_bad_param, /**< parameter no accepted */
tfa_error_noclock, /**< required clock not present */
tfa_error_timeout, /**< a timeout occurred */
tfa_error_dsp, /**< a DSP error was returned */
tfa_error_container, /**< no or wrong container file */
tfa_error_max /**< impossible value, max enum */
};
enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx);
struct tfa_device **tfa_devs_create(int count);
void tfa_devs_destroy(int count);
struct tfa_device **tfa_get_device_struct(void);
int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep);
void tfa_lp_mode_interrupt(struct tfa_device *tfa);
void tfa_adapt_noisemode(struct tfa_device *tfa);
#endif /* TFA_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: Tfa9887_TfaFieldnames.h
* This file was generated automatically on 04/14/15 at 10:23:40.
* Source file: TFA9897N1B_I2C_list_URT_source_v34_87Only.xls
*/
#define TFA9887_I2CVERSION 34
#define TFA9895_I2CVERSION 34
#define TFA9887_NAMETABLE \
static tfaBfName_t Tfa9887DatasheetNames[] = { \
{ 0x402, \
"I2SF" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"CHS12" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"CHS3" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"CHSA" }, /* Input selection for amplifier , */ \
{ 0x4b0, \
"I2SDOE" }, /* Enable data output , */ \
{ 0x4c3, \
"I2SSR" }, /* sample rate setting , */ \
{ 0x500, \
"BSSBY" }, /* , */ \
{ 0x511, \
"BSSCR" }, /* 00 = 0.56 dB/Sample , */ \
{ 0x532, \
"BSST" }, /* 000 = 2.92V , */ \
{ 0x5f0, \
"I2SDOC" }, /* selection data out , */ \
{ 0xa02, \
"DOLS" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"DORS" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"SPKL" }, /* Selection speaker induction , */ \
{ 0xa91, \
"SPKR" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"DCFG" }, /* DCDC speaker current compensation gain , */ \
{ 0x4134, \
"PWMDEL" }, /* PWM DelayBits to set the delay , */ \
{ 0x4180, \
"PWMSH" }, /* PWM Shape , */ \
{ 0x4190, \
"PWMRE" }, /* PWM Bitlength in noise shaper , */ \
{ 0x48e1, \
"TCC" }, /* sample & hold track time: , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};
#define TFA9887_BITNAMETABLE \
static tfaBfName_t Tfa9887BitNames[] = { \
{ 0x402, \
"i2s_seti" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"chan_sel1" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"lr_sw_i2si2" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"input_sel" }, /* Input selection for amplifier , */ \
{ 0x4b0, \
"enbl_datao" }, /* Enable data output , */ \
{ 0x4c3, \
"i2s_fs" }, /* sample rate setting , */ \
{ 0x500, \
"bypass_clipper" }, /* , */ \
{ 0x511, \
"vbat_prot_attacktime[1:0]" }, /* 00 = 0.56 dB/Sample , */ \
{ 0x532, \
"vbat_prot_thlevel[2:0]" }, /* 000 = 2.92V , */ \
{ 0x5d0, \
"reset_min_vbat" }, /* to reset the clipper via I2C in case the CF is bypassed, */ \
{ 0x5f0, \
"datao_sel" }, /* selection data out , */ \
{ 0xa02, \
"sel_i2so_l" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"sel_i2so_r" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"ctrl_spkr_coil" }, /* Selection speaker induction , */ \
{ 0xa91, \
"ctrl_spr_res" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"ctrl_dcdc_spkr_i_comp_gain" }, /* DCDC speaker current compensation gain , */ \
{ 0xaf0, \
"ctrl_dcdc_spkr_i_comp_sign" }, /* DCDC speaker current compensation sign , */ \
{ 0x4100, \
"bypass_hp" }, /* bypass_hp, to bypass the hp filter byhind the CoolFlux, */ \
{ 0x4110, \
"hard_mute" }, /* hard mute setting in HW , */ \
{ 0x4120, \
"soft_mute" }, /* Soft mute setting in HW , */ \
{ 0x4134, \
"PWM_Delay[4:0]" }, /* PWM DelayBits to set the delay , */ \
{ 0x4180, \
"PWM_Shape" }, /* PWM Shape , */ \
{ 0x4190, \
"PWM_BitLength" }, /* PWM Bitlength in noise shaper , */ \
{ 0x4800, \
"ctrl_negin" }, /* , */ \
{ 0x4810, \
"ctrl_cs_sein" }, /* , */ \
{ 0x4820, \
"ctrl_coincidencecs" }, /* HIGH => Prevent dcdc switching during clk_cs_clksh, */ \
{ 0x4876, \
"delay_se_neg[6:0]" }, /* delayshiftse2 , */ \
{ 0x48e1, \
"ctrl_cs_ttrack[1:0]" }, /* sample & hold track time: , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: Tfa9890_TfaFieldnames.h
* This file was generated automatically on 04/07/15 at 14:46:37.
* Source file: TFA9897N1B_I2C_list_URT_source_v34_90Only.xls
*/
#define TFA9890_I2CVERSION 34
#define TFA9890_NAMETABLE \
static tfaBfName_t Tfa9890DatasheetNames[] = { \
{ 0x402, \
"I2SF" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"CHS12" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"CHS3" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"CHSA" }, /* Input selection for amplifier , */ \
{ 0x481, \
"I2SDOC" }, /* selection data out , */ \
{ 0x4a0, \
"DISP" }, /* idp protection , */ \
{ 0x4b0, \
"I2SDOE" }, /* Enable data output , */ \
{ 0x4c3, \
"I2SSR" }, /* sample rate setting , */ \
{ 0x732, \
"DCMCC" }, /* Max boost coil current - step of 500 mA , */ \
{ 0x9c0, \
"CCFD" }, /* Selection CoolFlux Clock , */ \
{ 0x9d0, \
"ISEL" }, /* selection input 1 or 2 , */ \
{ 0xa02, \
"DOLS" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"DORS" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"SPKL" }, /* Selection speaker induction , */ \
{ 0xa91, \
"SPKR" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"DCFG" }, /* DCDC speaker current compensation gain , */ \
{ 0xf00, \
"VDDD" }, /* mask flag_por for interupt generation , */ \
{ 0xf10, \
"OTDD" }, /* mask flag_otpok for interupt generation , */ \
{ 0xf20, \
"OVDD" }, /* mask flag_ovpok for interupt generation , */ \
{ 0xf30, \
"UVDD" }, /* mask flag_uvpok for interupt generation , */ \
{ 0xf40, \
"OCDD" }, /* mask flag_ocp_alarm for interupt generation , */ \
{ 0xf50, \
"CLKD" }, /* mask flag_clocks_stable for interupt generation , */ \
{ 0xf60, \
"DCCD" }, /* mask flag_pwrokbst for interupt generation , */ \
{ 0xf70, \
"SPKD" }, /* mask flag_cf_speakererror for interupt generation , */ \
{ 0xf80, \
"WDD" }, /* mask flag_watchdog_reset for interupt generation , */ \
{ 0xf90, \
"LCLK" }, /* mask flag_lost_clk for interupt generation , */ \
{ 0xfe0, \
"INT" }, /* enabling interrupt , */ \
{ 0xff0, \
"INTP" }, /* Setting polarity interupt , */ \
{ 0x8f0f, \
"VERSION" }, /* (key1 protected) , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};
#define TFA9890_BITNAMETABLE \
static tfaBfName_t Tfa9890BitNames[] = { \
{ 0x402, \
"i2s_seti" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"chan_sel1" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"lr_sw_i2si2" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"input_sel" }, /* Input selection for amplifier , */ \
{ 0x481, \
"datao_sel" }, /* selection data out , */ \
{ 0x4a0, \
"disable_idp" }, /* idp protection , */ \
{ 0x4b0, \
"enbl_datao" }, /* Enable data output , */ \
{ 0x4c3, \
"i2s_fs" }, /* sample rate setting , */ \
{ 0x732, \
"ctrl_bstcur" }, /* Max boost coil current - step of 500 mA , */ \
{ 0x9c0, \
"sel_cf_clk" }, /* Selection CoolFlux Clock , */ \
{ 0x9d0, \
"intf_sel" }, /* selection input 1 or 2 , */ \
{ 0xa02, \
"sel_i2so_l" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"sel_i2so_r" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"ctrl_spkr_coil" }, /* Selection speaker induction , */ \
{ 0xa91, \
"ctrl_spr_res" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"ctrl_dcdc_spkr_i_comp_gain" }, /* DCDC speaker current compensation gain , */ \
{ 0xaf0, \
"ctrl_dcdc_spkr_i_comp_sign" }, /* DCDC speaker current compensation sign , */ \
{ 0xf00, \
"flag_por_mask" }, /* mask flag_por for interupt generation , */ \
{ 0xf10, \
"flag_otpok_mask" }, /* mask flag_otpok for interupt generation , */ \
{ 0xf20, \
"flag_ovpok_mask" }, /* mask flag_ovpok for interupt generation , */ \
{ 0xf30, \
"flag_uvpok_mask" }, /* mask flag_uvpok for interupt generation , */ \
{ 0xf40, \
"flag_ocp_alarm_mask" }, /* mask flag_ocp_alarm for interupt generation , */ \
{ 0xf50, \
"flag_clocks_stable_mask" }, /* mask flag_clocks_stable for interupt generation , */ \
{ 0xf60, \
"flag_pwrokbst_mask" }, /* mask flag_pwrokbst for interupt generation , */ \
{ 0xf70, \
"flag_cf_speakererror_mask" }, /* mask flag_cf_speakererror for interupt generation , */ \
{ 0xf80, \
"flag_watchdog_reset_mask" }, /* mask flag_watchdog_reset for interupt generation , */ \
{ 0xf90, \
"flag_lost_clk_mask" }, /* mask flag_lost_clk for interupt generation , */ \
{ 0xfe0, \
"enable_interrupt" }, /* enabling interrupt , */ \
{ 0xff0, \
"invert_int_polarity" }, /* Setting polarity interupt , */ \
{ 0x4700, \
"switch_fb" }, /* switch_fb , */ \
{ 0x4713, \
"se_hyst" }, /* se_hyst , */ \
{ 0x4754, \
"se_level" }, /* se_level , */ \
{ 0x47a5, \
"ktemp" }, /* temperature compensation trimming , */ \
{ 0x8f0f, \
"production_data6" }, /* (key1 protected) , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __TFA98XX_INC__
#define __TFA98XX_INC__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/list.h>
#include <linux/miscdevice.h>
#include "tfa_device.h"
#include "tfa_container.h"
#include "config.h"
/* max. length of a alsa mixer control name */
#define MAX_CONTROL_NAME 48
#define TFA98XX_MAX_REGISTER 0xff
#define TFA98XX_FLAG_SKIP_INTERRUPTS (1 << 0)
#define TFA98XX_FLAG_SAAM_AVAILABLE (1 << 1)
#define TFA98XX_FLAG_STEREO_DEVICE (1 << 2)
#define TFA98XX_FLAG_MULTI_MIC_INPUTS (1 << 3)
#define TFA98XX_FLAG_TAPDET_AVAILABLE (1 << 4)
#define TFA98XX_FLAG_CALIBRATION_CTL (1 << 5)
#define TFA98XX_FLAG_REMOVE_PLOP_NOISE (1 << 6)
#define TFA98XX_FLAG_LP_MODES (1 << 7)
#define TFA98XX_FLAG_TDM_DEVICE (1 << 8)
#define TFA98XX_FLAG_ADAPT_NOISE_MODE (1 << 9)
#define TFA98XX_NUM_RATES 10
/* DSP init status */
enum tfa98xx_dsp_init_state {
TFA98XX_DSP_INIT_STOPPED, /* DSP not running */
TFA98XX_DSP_INIT_RECOVER, /* DSP error detected at runtime */
TFA98XX_DSP_INIT_FAIL, /* DSP init failed */
TFA98XX_DSP_INIT_PENDING, /* DSP start requested */
TFA98XX_DSP_INIT_DONE, /* DSP running */
TFA98XX_DSP_INIT_INVALIDATED, /* DSP was running, requires re-init */
};
enum tfa98xx_dsp_fw_state {
TFA98XX_DSP_FW_NONE = 0,
TFA98XX_DSP_FW_PENDING,
TFA98XX_DSP_FW_FAIL,
TFA98XX_DSP_FW_OK,
};
enum tfa98xx_misc_device_id {
MISC_DEVICE_TFA98XX_REG,
MISC_DEVICE_TFA98XX_RW,
MISC_DEVICE_TFA98XX_RPC,
MISC_DEVICE_TFA98XX_PROFILE,
MISC_DEVICE_TFA98XX_IOCTL,
MISC_DEVICE_MAX
};
struct tfa98xx_miscdevice_info {
char devicename[255];
struct file_operations operations;
};
enum TFA_DEVICE_MUTE {
TFA98XX_DEVICE_MUTE_OFF = 0,
TFA98XX_DEVICE_MUTE_ON,
};
enum {
IOCTL_CMD_GET_MEMTRACK_DATA = 0,
IOCTL_CMD_GET_CNT_VERSION,
};
enum { TFA_KCONTROL_VALUE_DISABLED = 0, TFA_KCONTROL_VALUE_ENABLED };
struct livedata_cfg {
int address;
int track;
int scaler;
};
struct tfa98xx_firmware {
void *base;
struct tfa98xx_device *dev;
char name[9]; //TODO get length from tfa parameter defs
};
struct tfa98xx_baseprofile {
char basename[MAX_CONTROL_NAME]; /* profile basename */
int len; /* profile length */
int item_id; /* profile id */
int sr_rate_sup
[TFA98XX_NUM_RATES]; /* sample rates supported by this profile */
struct list_head list; /* list of all profiles */
};
enum tfa_reset_polarity { LOW = 0, HIGH = 1 };
struct tfa98xx {
struct regmap *regmap;
struct i2c_client *i2c;
struct regulator *vdd;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0)
struct snd_soc_component *component;
#else
struct snd_soc_codec *codec;
#endif
struct workqueue_struct *tfa98xx_wq;
struct delayed_work init_work;
struct delayed_work monitor_work;
struct delayed_work interrupt_work;
struct delayed_work tapdet_work;
struct delayed_work nmodeupdate_work;
struct mutex dsp_lock;
int dsp_init;
int dsp_fw_state;
int sysclk;
int rst_gpio;
u16 rev;
int audio_mode;
struct tfa98xx_firmware fw;
char *fw_name;
int rate;
wait_queue_head_t wq;
struct device *dev;
unsigned int init_count;
int pstream;
int cstream;
struct input_dev *input;
bool tapdet_enabled; /* service enabled */
bool tapdet_open; /* device file opened */
unsigned int tapdet_profiles; /* tapdet profile bitfield */
bool tapdet_poll; /* tapdet running on polling mode */
unsigned int rate_constraint_list[TFA98XX_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
int reset_gpio;
int power_gpio;
int irq_gpio;
int spk_sw_gpio;
enum tfa_reset_polarity reset_polarity;
struct list_head list;
struct tfa_device *tfa;
int vstep;
int profile;
int prof_vsteps
[TFACONT_MAXPROFS]; /* store vstep per profile (single device) */
#ifdef CONFIG_DEBUG_FS
struct dentry *dbg_dir;
#endif
u8 reg;
unsigned int flags;
bool set_mtp_cal;
uint16_t cal_data;
enum TFA_DEVICE_MUTE tfa_mute_mode;
struct device_node *spk_id_gpio_p;
struct miscdevice tfa98xx_reg;
struct miscdevice tfa98xx_rw;
struct miscdevice tfa98xx_rpc;
struct miscdevice tfa98xx_profile;
struct miscdevice tfa98xx_control;
};
/*for furture, we will move it to DTS to mark left and right channel*/
#define TFA_LEFT_DEVICE_ADDRESS (0x34)
#define TFA_RIGHT_DEVICE_ADDRESS (0x35)
#endif /* __TFA98XX_INC__ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* tfa98xx_parameters.h
*
* Created on: Jul 22, 2013
* Author: NLV02095
*/
#ifndef TFA98XXPARAMETERS_H_
#define TFA98XXPARAMETERS_H_
//#include "config.h"
// workaround for Visual Studio:
// fatal error C1083: Cannot open include file: 'config.h': No such file or directory
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#include "tfa_service.h"
#if (defined(WIN32) || defined(_X64))
/* These warnings are disabled because it is only given by Windows and there is no easy fix */
#pragma warning(disable : 4200)
#pragma warning(disable : 4214)
#endif
/*
* profiles & volumesteps
*
*/
#define TFA_MAX_PROFILES (64)
#define TFA_MAX_VSTEPS (64)
#define TFA_MAX_VSTEP_MSG_MARKER \
(100) /* This marker is used to indicate if all msgs need to be written to the device */
#define TFA_MAX_MSGS (10)
// the pack pragma is required to make that the size in memory
// matches the actual variable lenghts
// This is to assure that the binary files can be transported between
// different platforms.
#pragma pack(push, 1)
/*
* typedef for 24 bit value using 3 bytes
*/
typedef struct uint24 {
uint8_t b[3];
} uint24_t;
/*
* the generic header
* all char types are in ASCII
*/
typedef struct TfaHeader {
uint16_t id;
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint16_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
char customer[8]; // “name of customer”
char application[8]; // “application name”
char type[8]; // “application type name”
} TfaHeader_t;
typedef enum TfaSamplerate {
fs_8k, // 8kHz
fs_11k025, // 11.025kHz
fs_12k, // 12kHz
fs_16k, // 16kHz
fs_22k05, // 22.05kHz
fs_24k, // 24kHz
fs_32k, // 32kHz
fs_44k1, // 44.1kHz
fs_48k, // 48kHz
fs_96k, // 96kHz
fs_count // Should always be last item.
} TfaSamplerate_t;
// Keep in sync with TfaSamplerate_t !
static const int TfaSamplerateHz[fs_count] = { 8000, 11025, 12000, 16000,
22050, 24000, 32000, 44100,
48000, 96000 };
/*
* coolflux direct memory access
*/
typedef struct TfaDspMem {
uint8_t type; /* 0--3: p, x, y, iomem */
uint16_t address; /* target address */
uint8_t size; /* data size in words */
int words[]; /* payload in signed 32bit integer (two's complement) */
} TfaDspMem_t;
/*
* the biquad coefficients for the API together with index in filter
* the biquad_index is the actual index in the equalizer +1
*/
#define BIQUAD_COEFF_SIZE 6
/*
* Output fixed point coeffs structure
*/
typedef struct {
int a2;
int a1;
int b2;
int b1;
int b0;
} TfaBiquad_t;
typedef struct TfaBiquadOld {
uint8_t bytes[BIQUAD_COEFF_SIZE * sizeof(uint24_t)];
} TfaBiquadOld_t;
typedef struct TfaBiquadFloat {
float headroom;
float b0;
float b1;
float b2;
float a1;
float a2;
} TfaBiquadFloat_t;
/*
* EQ filter definitions
* Note: This is not in line with smartstudio (JV: 12/12/2016)
*/
typedef enum TfaFilterType {
fCustom, //User defined biquad coefficients
fFlat, //Vary only gain
fLowpass, //2nd order Butterworth low pass
fHighpass, //2nd order Butterworth high pass
fLowshelf,
fHighshelf,
fNotch,
fPeak,
fBandpass,
f1stLP,
f1stHP,
fElliptic
} TfaFilterType_t;
/*
* filter parameters for biquad (re-)calculation
*/
typedef struct TfaFilter {
TfaBiquadOld_t biquad;
uint8_t enabled;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float frequency;
float Q;
float gain;
} TfaFilter_t; //8 * float + int32 + byte == 37
/*
* biquad params for calculation
*/
#define TFA_BQ_EQ_INDEX 0
#define TFA_BQ_ANTI_ALIAS_INDEX 10
#define TFA_BQ_INTEGRATOR_INDEX 13
/*
* Loudspeaker Compensation filter definitions
*/
typedef struct TfaLsCompensationFilter {
TfaBiquad_t biquad;
uint8_t lsCompOn; // Loudspeaker compensation on/off; when 'off', the DSP code doesn't apply the bwExt => bwExtOn GUI flag should be gray to avoid confusion
uint8_t bwExtOn; // Bandwidth extension on/off
float fRes; // [Hz] speaker resonance frequency
float Qt; // Speaker resonance Q-factor
float fBwExt; // [Hz] Band width extension frequency
float samplingFreq; // [Hz] Sampling frequency
} TfaLsCompensationFilter_t;
/*
* Anti Aliasing Elliptic filter definitions
*/
typedef struct TfaAntiAliasFilter {
TfaBiquad_t biquad; /**< Output results fixed point coeffs */
uint8_t enabled;
float cutOffFreq; // cut off frequency
float samplingFreq; // sampling frequency
float rippleDb; // range: [0.1 3.0]
float rolloff; // range: [-1.0 1.0]
} TfaAntiAliasFilter_t;
/**
* Integrator filter input definitions
*/
typedef struct TfaIntegratorFilter {
TfaBiquad_t biquad; /**< Output results fixed point coeffs */
uint8_t type; /**< Butterworth filter type: high or low pass */
float cutOffFreq; /**< cut off frequency in Hertz; range: [100.0 4000.0] */
float samplingFreq; /**< sampling frequency in Hertz */
float leakage; /**< leakage factor; range [0.0 1.0] */
} TfaIntegratorFilter_t;
typedef struct TfaEqFilter {
TfaBiquad_t biquad;
uint8_t enabled;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
float samplingFreq; // sampling frequency
float Q; // range: [0.5 5.0]
float gainDb; // range: [-10.0 10.0]
} TfaEqFilter_t; //8 * float + int32 + byte == 37
typedef struct TfaContAntiAlias {
int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
uint8_t type;
float cutOffFreq; // cut off frequency
float samplingFreq;
float rippleDb; // integrator leakage
float rolloff;
uint8_t bytes[5 * 3]; // payload 5*24buts coeffs
} TfaContAntiAlias_t;
typedef struct TfaContIntegrator {
int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
uint8_t type;
float cutOffFreq; // cut off frequency
float samplingFreq;
float leakage; // integrator leakage
float reserved;
uint8_t bytes[5 * 3]; // payload 5*24buts coeffs
} TfaContIntegrator_t;
typedef struct TfaContEq {
int8_t index;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
float samplingFreq; // sampling frequency
float Q; // range: [0.5 5.0]
float gainDb; // range: [-10.0 10.0]
uint8_t bytes[5 * 3]; // payload 5*24buts coeffs
} TfaContEq_t; //8 * float + int32 + byte == 37
typedef union TfaContBiquad {
TfaContEq_t eq;
TfaContAntiAlias_t aa;
TfaContIntegrator_t in;
} TfaContBiquad_t;
#define TFA_BQ_EQ_INDEX 0
#define TFA_BQ_ANTI_ALIAS_INDEX 10
#define TFA_BQ_INTEGRATOR_INDEX 13
#define TFA98XX_MAX_EQ 10
typedef struct TfaEqualizer {
TfaFilter_t filter[TFA98XX_MAX_EQ];
} TfaEqualizer_t;
/*
* files
*/
#define HDR(c1, c2) (c2 << 8 | c1) // little endian
typedef enum TfaHeaderType {
paramsHdr = HDR('P', 'M'), /* containter file */
volstepHdr = HDR('V', 'P'),
patchHdr = HDR('P', 'A'),
speakerHdr = HDR('S', 'P'),
presetHdr = HDR('P', 'R'),
configHdr = HDR('C', 'O'),
equalizerHdr = HDR('E', 'Q'),
drcHdr = HDR('D', 'R'),
msgHdr = HDR('M', 'G'), /* generic message */
infoHdr = HDR('I', 'N')
} TfaHeaderType_t;
/*
* equalizer file
*/
#define TFA_EQ_VERSION '1'
#define TFA_EQ_SUBVERSION "00"
typedef struct TfaEqualizerFile {
TfaHeader_t hdr;
uint8_t samplerate; // ==enum samplerates, assure 8 bits
TfaFilter_t filter[TFA98XX_MAX_EQ]; // note: API index counts from 1..10
} TfaEqualizerFile_t;
/*
* patch file
*/
#define TFA_PA_VERSION '1'
#define TFA_PA_SUBVERSION "00"
typedef struct TfaPatchFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaPatch_t;
/*
* generic message file
* - the payload of this file includes the opcode and is send straight to the DSP
*/
#define TFA_MG_VERSION '3'
#define TFA_MG_SUBVERSION "00"
typedef struct TfaMsgFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaMsgFile_t;
/*
* NOTE the tfa98xx API defines the enum Tfa98xx_config_type that defines
* the subtypes as decribes below.
* tfa98xx_dsp_config_parameter_type() can be used to get the
* supported type for the active device..
*/
/*
* config file V1 sub 1
*/
#define TFA_CO_VERSION '1'
#define TFA_CO3_VERSION '3'
#define TFA_CO_SUBVERSION1 "01"
typedef struct TfaConfigS1File {
TfaHeader_t hdr;
uint8_t data[55 * 3];
} TfaConfigS1_t;
/*
* config file V1 sub 2
*/
#define TFA_CO_SUBVERSION2 "02"
typedef struct TfaConfigS2File {
TfaHeader_t hdr;
uint8_t data[67 * 3];
} TfaConfigS2_t;
/*
* config file V1 sub 3
*/
#define TFA_CO_SUBVERSION3 "03"
typedef struct TfaConfigS3File {
TfaHeader_t hdr;
uint8_t data[67 * 3];
} TfaConfigS3_t;
/*
* config file V1.0
*/
#define TFA_CO_SUBVERSION "00"
typedef struct TfaConfigFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaConfig_t;
/*
* preset file
*/
#define TFA_PR_VERSION '1'
#define TFA_PR_SUBVERSION "00"
typedef struct TfaPresetFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaPreset_t;
/*
* drc file
*/
#define TFA_DR_VERSION '1'
#define TFA_DR_SUBVERSION "00"
typedef struct TfaDrcFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaDrc_t;
/*
* drc file
* for tfa 2 there is also a xml-version
*/
#define TFA_DR3_VERSION '3'
#define TFA_DR3_SUBVERSION "00"
typedef struct TfaDrcFile2 {
TfaHeader_t hdr;
uint8_t version[3];
uint8_t data[];
} TfaDrc2_t;
/*
* volume step structures
*/
// VP01
#define TFA_VP1_VERSION '1'
#define TFA_VP1_SUBVERSION "01"
typedef struct TfaVolumeStep1 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
} TfaVolumeStep1_t;
// VP02
#define TFA_VP2_VERSION '2'
#define TFA_VP2_SUBVERSION "01"
typedef struct TfaVolumeStep2 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
TfaFilter_t filter[TFA98XX_MAX_EQ]; // note: API index counts from 1..10
} TfaVolumeStep2_t;
/*
* volumestep file
*/
#define TFA_VP_VERSION '1'
#define TFA_VP_SUBVERSION "00"
typedef struct TfaVolumeStepFile {
TfaHeader_t hdr;
uint8_t vsteps; // can also be calulated from size+type
uint8_t samplerate; // ==enum samplerates, assure 8 bits
uint8_t payload; //start of variable length contents:N times volsteps
} TfaVolumeStepFile_t;
/*
* volumestep2 file
*/
typedef struct TfaVolumeStep2File {
TfaHeader_t hdr;
uint8_t vsteps; // can also be calulated from size+type
uint8_t samplerate; // ==enum samplerates, assure 8 bits
TfaVolumeStep2_t
vstep[]; //start of variable length contents:N times volsteps
} TfaVolumeStep2File_t;
/*
* volumestepMax2 file
*/
typedef struct TfaVolumeStepMax2File {
TfaHeader_t hdr;
uint8_t version[3];
uint8_t NrOfVsteps;
uint8_t vstepsBin[];
} TfaVolumeStepMax2File_t;
/*
* volumestepMax2 file
* This volumestep should ONLY be used for the use of bin2hdr!
* This can only be used to find the messagetype of the vstep (without header)
*/
typedef struct TfaVolumeStepMax2_1File {
uint8_t version[3];
uint8_t NrOfVsteps;
uint8_t vstepsBin[];
} TfaVolumeStepMax2_1File_t;
struct TfaVolumeStepRegisterInfo {
uint8_t NrOfRegisters;
uint16_t registerInfo[];
};
struct TfaVolumeStepMessageInfo {
uint8_t NrOfMessages;
uint8_t MessageType;
uint24_t MessageLength;
uint8_t CmdId[3];
uint8_t ParameterData[];
};
/**************************old v2 *************************************************/
/*
* subv 00 volumestep file
*/
typedef struct TfaOldHeader {
uint16_t id;
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint16_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
} TfaOldHeader_t;
typedef struct TfaOldFilter {
double bq[5];
int32_t type;
double frequency;
double Q;
double gain;
uint8_t enabled;
} TfaOldFilter_t;
typedef struct TfaOldVolumeStep2 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
TfaOldFilter_t eq[10];
} TfaOldVolumeStep2_t;
typedef struct TfaOldVolumeStepFile {
TfaOldHeader_t hdr;
TfaOldVolumeStep2_t step[];
} TfaOldVolumeStep2File_t;
/**************************end old v2 *************************************************/
/*
* speaker file header
*/
struct TfaSpkHeader {
struct TfaHeader hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint16_t ohm;
};
/*
* speaker file
*/
#define TFA_SP_VERSION '1'
#define TFA_SP_SUBVERSION "00"
typedef struct TfaSpeakerFile {
TfaHeader_t hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint8_t ohm_primary;
uint8_t ohm_secondary;
uint8_t data[]; //payload TFA98XX_SPEAKERPARAMETER_LENGTH
} TfaSpeakerFile_t;
#define TFA_VP3_VERSION '3'
#define TFA_VP3_SUBVERSION "00"
struct TfaFWVer {
uint8_t Major;
uint8_t minor;
uint8_t minor_update : 6;
uint8_t Update : 2;
};
struct TfaFWMsg {
struct TfaFWVer fwVersion;
struct TfaMsg payload;
};
typedef struct TfaLiveData {
char name[25];
char addrs[25];
int tracker;
int scalefactor;
} TfaLiveData_t;
#define TFA_SP3_VERSION '3'
#define TFA_SP3_SUBVERSION "00"
struct TfaSpeakerFileMax2 {
TfaHeader_t hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint8_t ohm_primary;
uint8_t ohm_secondary;
struct TfaFWMsg FWmsg; //payload including FW ver and Cmd ID
};
/*
* parameter container file
*/
/*
* descriptors
* Note 1: append new DescriptorType at the end
* Note 2: add new descriptors to dsc_name[] in tfaContUtil.c
*/
typedef enum TfaDescriptorType {
dscDevice, // device list
dscProfile, // profile list
dscRegister, // register patch
dscString, // ascii, zero terminated string
dscFile, // filename + file contents
dscPatch, // patch file
dscMarker, // marker to indicate end of a list
dscMode,
dscSetInputSelect,
dscSetOutputSelect,
dscSetProgramConfig,
dscSetLagW,
dscSetGains,
dscSetvBatFactors,
dscSetSensesCal,
dscSetSensesDelay,
dscBitfield,
dscDefault, // used to reset bitfields to there default values
dscLiveData,
dscLiveDataString,
dscGroup,
dscCmd,
dscSetMBDrc,
dscFilter,
dscNoInit,
dscFeatures,
dscCfMem, // coolflux memory x,y,io
dscSetFwkUseCase,
dscSetVddpConfig,
dsc_last // trailer
} TfaDescriptorType_t;
#define TFA_BITFIELDDSCMSK 0x7fffffff
typedef struct TfaDescPtr {
uint32_t offset : 24;
uint32_t type : 8; // (== enum TfaDescriptorType, assure 8bits length)
} TfaDescPtr_t;
/*
* generic file descriptor
*/
typedef struct TfaFileDsc {
TfaDescPtr_t name;
uint32_t size; // file data length in bytes
uint8_t data[]; //payload
} TfaFileDsc_t;
/*
* device descriptor list
*/
typedef struct TfaDeviceList {
uint8_t length; // nr of items in the list
uint8_t bus; // bus
uint8_t dev; // device
uint8_t func; // subfunction or subdevice
uint32_t devid; // device hw fw id
TfaDescPtr_t name; // device name
TfaDescPtr_t list[]; // items list
} TfaDeviceList_t;
/*
* profile descriptor list
*/
typedef struct TfaProfileList {
uint32_t length : 8; // nr of items in the list + name
uint32_t group : 8; // profile group number
uint32_t ID : 16; // profile ID
TfaDescPtr_t name; // profile name
TfaDescPtr_t list[]; // items list (lenght-1 items)
} TfaProfileList_t;
#define TFA_PROFID 0x1234
/*
* livedata descriptor list
*/
typedef struct TfaLiveDataList {
uint32_t length : 8; // nr of items in the list
uint32_t ID : 24; // profile ID
TfaDescPtr_t name; // livedata name
TfaDescPtr_t list[]; // items list
} TfaLiveDataList_t;
#define TFA_LIVEDATAID 0x5678
/*
* Bitfield descriptor
*/
typedef struct TfaBitfield {
uint16_t value;
uint16_t field; // ==datasheet defined, 16 bits
} TfaBitfield_t;
/*
* Bitfield enumuration bits descriptor
*/
typedef struct TfaBfEnum {
unsigned int len : 4; // this is the actual length-1
unsigned int pos : 4;
unsigned int address : 8;
} TfaBfEnum_t;
/*
* Register patch descriptor
*/
typedef struct TfaRegpatch {
uint8_t address; // register address
uint16_t value; // value to write
uint16_t mask; // mask of bits to write
} TfaRegpatch_t;
/*
* Mode descriptor
*/
typedef struct TfaUseCase {
int value; // mode value, maps to enum Tfa98xx_Mode
} TfaMode_t;
/*
* NoInit descriptor
*/
typedef struct TfaNoInit {
uint8_t value; // noInit value
} TfaNoInit_t;
/*
* Features descriptor
*/
typedef struct TfaFeatures {
uint16_t value[3]; // features value
} TfaFeatures_t;
/*
* the container file
* - the size field is 32bits long (generic=16)
* - all char types are in ASCII
*/
#define TFA_PM_VERSION '1'
#define TFA_PM3_VERSION '3'
#define TFA_PM_SUBVERSION '1'
typedef struct TfaContainer {
char id[2]; // "XX" : XX=type
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint32_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
uint16_t rev; // "extra chars for rev nr"
char customer[8]; // “name of customer”
char application[8]; // “application name”
char type[8]; // “application type name”
uint16_t ndev; // "nr of device lists"
uint16_t nprof; // "nr of profile lists"
uint16_t nliveData; // "nr of livedata lists"
TfaDescPtr_t index[]; // start of item index table
} TfaContainer_t;
#pragma pack(pop)
#endif /* TFA98XXPARAMETERS_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
typedef struct TfaBfName {
unsigned short bfEnum;
char *bfName;
} tfaBfName_t;
typedef struct TfaIrqName {
unsigned short irqEnum;
char *irqName;
} tfaIrqName_t;
#include "tfa1_tfafieldnames.h"
#include "tfa2_tfafieldnames_N1C.h"
/* diffs for specific devices */
#include "tfa9887_tfafieldnames.h"
#include "tfa9890_tfafieldnames.h"
#include "tfa9891_tfafieldnames.h"
#include "tfa9872_tfafieldnames.h"
#include "tfa9912_tfafieldnames.h"
#include "tfa9896_tfafieldnames.h"
#include "tfa9873_tfafieldnames.h"
#include "tfa9873_tfafieldnames_B0.h"
#include "tfa9874_tfafieldnames.h"
#include "tfa9878_tfafieldnames.h"
#include "tfa9894_tfafieldnames.h"
#include "tfa9894_tfafieldnames_N2.h"
/* missing 'common' defs break the build but unused in TFA1 context */
#define TFA1_BF_AMPINSEL -1
#define TFA1_BF_MANSCONF -1
#define TFA1_BF_MANCOLD -1
#define TFA1_BF_INTSMUTE -1
#define TFA1_BF_CFSMR -1
#define TFA1_BF_CFSML -1
#define TFA1_BF_DCMCCAPI -1
#define TFA1_BF_DCMCCSB -1
#define TFA1_BF_USERDEF -1
#define TFA1_BF_MANSTATE -1
#define TFA1_BF_MANOPER -1
#define TFA1_BF_REFCKSEL -1
#define TFA1_BF_VOLSEC -1
#define TFA1_BF_FRACTDEL -1
#define TFA1_BF_ACKDMG -1
#define TFA1_BF_SSRIGHTE -1
#define TFA1_BF_SSLEFTE -1
#define TFA1_BF_R25CL -1
#define TFA1_BF_R25CR -1
#define TFA1_BF_SWPROFIL 0x8045 /*!< profile save */
#define TFA1_BF_SWVSTEP 0x80a5 /*!< vstep save */
/* missing 'common' defs break the build */
#define TFA2_BF_CFSM -1
/* MTP access uses registers
* defs are derived from corresponding bitfield names as used in the BF macros
*/
#define MTPKEY2 MTPK /* unlock key2 MTPK */
#define MTP0 MTPOTC /* MTP data */
#define MTP_CONTROL CIMTP /* copy i2c to mtp */
/* interrupt enable register uses HW name in TFA2 */
#define TFA2_BF_INTENVDDS TFA2_BF_IEVDDS
/* TFA9891 specific bit field names */
#define TFA1_BF_SAAMGAIN 0x2202
#define TFA2_BF_SAAMGAIN -1
/* TFA9872 specific bit field names */
#define TFA2_BF_IELP0 TFA9872_BF_IELP0
#define TFA2_BF_ISTLP0 TFA9872_BF_ISTLP0
#define TFA2_BF_IPOLP0 TFA9872_BF_IPOLP0
#define TFA2_BF_IELP1 TFA9872_BF_IELP1
#define TFA2_BF_ISTLP1 TFA9872_BF_ISTLP1
#define TFA2_BF_IPOLP1 TFA9872_BF_IPOLP1
#define TFA2_BF_LP0 TFA9872_BF_LP0
#define TFA2_BF_LP1 TFA9872_BF_LP1
#define TFA2_BF_R25C TFA9872_BF_R25C
#define TFA2_BF_SAMMODE TFA9872_BF_SAMMODE
/* interrupt bit field names of TFA2 and TFA1 do not match */
#define TFA1_BF_IEACS TFA1_BF_INTENACS
#define TFA1_BF_IPOACS TFA1_BF_INTPOLACS
#define TFA1_BF_ISTACS TFA1_BF_INTOACS
#define TFA1_BF_ISTVDDS TFA1_BF_INTOVDDS
#define TFA1_BF_ICLVDDS TFA1_BF_INTIVDDS
#define TFA1_BF_IPOVDDS TFA1_BF_INTPOLVDDS
#define TFA1_BF_IENOCLK TFA1_BF_INTENNOCLK
#define TFA1_BF_ISTNOCLK TFA1_BF_INTONOCLK
#define TFA1_BF_IPONOCLK TFA1_BF_INTPOLNOCLK
/* interrupt bit fields not available on TFA1 */
#define TFA1_BF_IECLKOOR -1
#define TFA1_BF_ISTCLKOOR -1
#define TFA1_BF_IEMWSRC -1
#define TFA1_BF_ISTMWSRC -1
#define TFA1_BF_IPOMWSRC -1
#define TFA1_BF_IEMWSMU -1
#define TFA1_BF_ISTMWSMU -1
#define TFA1_BF_IPOMWSMU -1
#define TFA1_BF_IEMWCFC -1
#define TFA1_BF_ISTMWCFC -1
#define TFA1_BF_IPOMWCFC -1
#define TFA1_BF_CLKOOR -1
#define TFA1_BF_MANWAIT1 -1
#define TFA1_BF_MANWAIT2 -1
#define TFA1_BF_MANMUTE -1
#define TFA1_BF_IPCLKOOR -1
#define TFA1_BF_ICLCLKOOR -1
#define TFA1_BF_IPOSWS -1
#define TFA1_BF_IESWS -1
#define TFA1_BF_ISTSWS -1
#define TFA1_BF_IESPKS -1
#define TFA1_BF_ISTSPKS -1
#define TFA1_BF_IPOSPKS -1
#define TFA1_BF_IECLKS -1
#define TFA1_BF_ISTCLKS -1
#define TFA1_BF_IPOCLKS -1
#define TFA1_BF_IEAMPS -1
#define TFA1_BF_ISTAMPS -1
#define TFA1_BF_IPOAMPS -1
#define TFA1_BF_IELP0 -1
#define TFA1_BF_ISTLP0 -1
#define TFA1_BF_IPOLP0 -1
#define TFA1_BF_IELP1 -1
#define TFA1_BF_ISTLP1 -1
#define TFA1_BF_IPOLP1 -1
#define TFA1_BF_LP0 -1
#define TFA1_BF_LP1 -1
#define TFA1_BF_R25C -1
#define TFA1_BF_SAMMODE -1
/* TDM STATUS fields not available on TFA1 */
#define TFA1_BF_TDMLUTER -1
#define TFA1_BF_TDMERR -1

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* tfaContainer.h
*
* Created on: Sep 11, 2013
* Author: wim
*/
#ifndef TFACONTAINER_H_
#define TFACONTAINER_H_
/* static limits */
#define TFACONT_MAXDEVS (4) /* maximum nr of devices */
#define TFACONT_MAXPROFS (16) /* maximum nr of profiles */
#include "tfa98xx_parameters.h"
/**
* Pass the container buffer, initialize and allocate internal memory.
*
* @param cnt pointer to the start of the buffer holding the container file
* @param length of the data in bytes
* @return
* - tfa_error_ok if normal
* - tfa_error_container invalid container data
* - tfa_error_bad_param invalid parameter
*
*/
enum tfa_error tfa_load_cnt(void *cnt, int length);
/**
* Return the descriptor string
* @param cnt pointer to the container struct
* @param dsc pointer to Tfa descriptor
* @return descriptor string
*/
char *tfaContGetString(TfaContainer_t *cnt, TfaDescPtr_t *dsc);
/**
* Gets the string for the given command type number
* @param type number representing a command
* @return string of a command
*/
char *tfaContGetCommandString(uint32_t type);
/**
* get the device type from the patch in this devicelist
* - find the patch file for this devidx
* - return the devid from the patch or 0 if not found
* @param cnt pointer to container file
* @param dev_idx device index
* @return descriptor string
*/
int tfa_cnt_get_devid(TfaContainer_t *cnt, int dev_idx);
/**
* Get the slave for the device if it exists.
* @param tfa the device struct pointer
* @param slave_addr the index of the device
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr);
void tfaContSetSlave(uint8_t slave_addr);
/**
* Get the index for a skave address.
* @param tfa the device struct pointer
* @return the device index
*/
int tfa_cont_get_idx(struct tfa_device *tfa);
/**
* Write reg and bitfield items in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa);
/**
* Write reg and bitfield items in the profilelist to the target.
* @param tfa the device struct pointer
* @param prof_idx the profile index
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx);
/**
* Write a patchfile in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa);
/**
* Write all param files in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa);
/**
* Get sample rate from passed profile index
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @return sample rate value
*/
unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa,
unsigned int prof_idx);
/**
* Get the device name string
* @param cnt the pointer to the container struct
* @param dev_idx the index of the device
* @return device name string or error string if not found
*/
char *tfaContDeviceName(TfaContainer_t *cnt, int dev_idx);
/**
* Get the application name from the container file application field
* @param tfa the device struct pointer
* @param name the input stringbuffer with size: sizeof(application field)+1
* @return actual string length
*/
int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name);
/**
* Get profile index of the calibration profile
* @param tfa the device struct pointer
* @return profile index, -2 if no calibration profile is found or -1 on error
*/
int tfaContGetCalProfile(struct tfa_device *tfa);
/**
* Is the profile a tap profile ?
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @return 1 if the profile is a tap profile or 0 if not
*/
int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx);
/**
* Get the name of the profile at certain index for a device in the container file
* @param cnt the pointer to the container struct
* @param dev_idx the index of the device
* @param prof_idx the index of the profile
* @return profile name string or error string if not found
*/
char *tfaContProfileName(TfaContainer_t *cnt, int dev_idx, int prof_idx);
/**
* Process all items in the profilelist
* NOTE an error return during processing will leave the device muted
* @param tfa the device struct pointer
* @param prof_idx index of the profile
* @param vstep_idx index of the vstep
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx,
int vstep_idx);
/**
* Specify the speaker configurations (cmd id) (Left, right, both, none)
* @param dev_idx index of the device
* @param configuration name string of the configuration
*/
void tfa98xx_set_spkr_select(int dev_idx, char *configuration);
enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa,
TfaFilter_t *filter);
/**
* Write all param files in the profilelist to the target
* this is used during startup when maybe ACS is set
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @param vstep_idx the index of the vstep
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx,
int vstep_idx);
enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx,
int vstep_idx);
enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size,
uint8_t data[]);
/**
* Get the device list dsc from the tfaContainer
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @return device list pointer
*/
TfaDeviceList_t *tfaContGetDevList(TfaContainer_t *cont, int dev_idx);
/**
* Get the Nth profile for the Nth device
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @param prof_idx the index of the profile
* @return profile list pointer
*/
TfaProfileList_t *tfaContGetDevProfList(TfaContainer_t *cont, int dev_idx,
int prof_idx);
/**
* Get the number of profiles for device from contaienr
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @return device list pointer
*/
int tfa_cnt_get_dev_nprof(struct tfa_device *tfa);
/**
* Get the Nth livedata for the Nth device
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @param livedata_idx the index of the livedata
* @return livedata list pointer
*/
TfaLiveDataList_t *tfaContGetDevLiveDataList(TfaContainer_t *cont, int dev_idx,
int livedata_idx);
/**
* Check CRC for container
* @param cont pointer to the tfaContainer
* @return error value 0 on error
*/
int tfaContCrcCheckContainer(TfaContainer_t *cont);
/**
* Get the device list pointer
* @param cnt pointer to the container struct
* @param dev_idx the index of the device
* @return pointer to device list
*/
TfaDeviceList_t *tfaContDevice(TfaContainer_t *cnt, int dev_idx);
/**
* Return the pointer to the first profile in a list from the tfaContainer
* @param cont pointer to the tfaContainer
* @return pointer to first profile in profile list
*/
TfaProfileList_t *tfaContGet1stProfList(TfaContainer_t *cont);
/**
* Return the pointer to the next profile in a list
* @param prof is the pointer to the profile list
* @return profile list pointer
*/
TfaProfileList_t *tfaContNextProfile(TfaProfileList_t *prof);
/**
* Return the pointer to the first livedata in a list from the tfaContainer
* @param cont pointer to the tfaContainer
* @return pointer to first livedata in profile list
*/
TfaLiveDataList_t *tfaContGet1stLiveDataList(TfaContainer_t *cont);
/**
* Return the pointer to the next livedata in a list
* @param livedata_idx is the pointer to the livedata list
* @return livedata list pointer
*/
TfaLiveDataList_t *tfaContNextLiveData(TfaLiveDataList_t *livedata_idx);
/**
* Write a bit field
* @param tfa the device struct pointer
* @param bf bitfield to write
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa,
TfaBitfield_t bf);
/**
* Write a parameter file to the device
* @param tfa the device struct pointer
* @param file filedescriptor pointer
* @param vstep_idx index to vstep
* @param vstep_msg_idx index to vstep message
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa, TfaFileDsc_t *file,
int vstep_idx, int vstep_msg_idx);
/**
* Get the max volume step associated with Nth profile for the Nth device
* @param tfa the device struct pointer
* @param prof_idx profile index
* @return the number of vsteps
*/
int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx);
/**
* Get the file contents associated with the device or profile
* Search within the device tree, if not found, search within the profile
* tree. There can only be one type of file within profile or device.
* @param tfa the device struct pointer
* @param prof_idx I2C profile index in the device
* @param type file type
* @return 0 NULL if file type is not found
* @return 1 file contents
*/
TfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx,
enum TfaHeaderType type);
/**
* Dump the contents of the file header
* @param hdr pointer to file header data
*/
void tfaContShowHeader(TfaHeader_t *hdr);
/**
* Read a bit field
* @param tfa the device struct pointer
* @param bf bitfield to read out
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa,
TfaBitfield_t *bf);
/**
* Get hw feature bits from container file
* @param tfa the device struct pointer
* @param hw_feature_register pointer to where hw features are stored
*/
void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register);
/**
* Get sw feature bits from container file
* @param tfa the device struct pointer
* @param sw_feature_register pointer to where sw features are stored
*/
void get_sw_features_from_cnt(struct tfa_device *tfa,
int sw_feature_register[2]);
/**
* Factory trimming for the Boost converter
* check if there is a correction needed
* @param tfa the device struct pointer
*/
enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa);
/**
* Search for filters settings and if found then write them to the device
* @param tfa the device struct pointer
* @param prof_idx profile to look in
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx);
/**
* Get the firmware version from the patch in the container file
* @param tfa the device struct pointer
* @return firmware version
*/
int tfa_cnt_get_patch_version(struct tfa_device *tfa);
int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length,
const char *buffer);
#endif /* TFACONTAINER_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/**\file
*
* The tfa_device interface controls a single I2C device instance by
* referencing to the device specific context provided by means of the
* tfa_device structure pointer.
* Multiple instances of tfa_device structures will be created and maintained
* by the caller.
*
* The API is functionally grouped as:
* - tfa_dev basic codec interface to probe, start/stop and control the device state
* - access to internal MTP storage
* - abstraction for interrupt bits and handling
* - container reading support
*/
#ifndef __TFA_DEVICE_H__
#define __TFA_DEVICE_H__
#include "config.h"
struct tfa_device;
/*
* hw/sw feature bit settings in MTP
*/
enum featureSupport {
supportNotSet, /**< default means not set yet */
supportNo, /**< no support */
supportYes /**< supported */
};
/*
* supported Digital Audio Interfaces bitmap
*/
enum Tfa98xx_DAI {
Tfa98xx_DAI_I2S = 0x01, /**< I2S only */
Tfa98xx_DAI_TDM = 0x02, /**< TDM, I2S */
Tfa98xx_DAI_PDM = 0x04, /**< PDM */
};
/*
* device ops function structure
*/
struct tfa_device_ops {
enum Tfa98xx_Error (*dsp_msg)(struct tfa_device *tfa, int length,
const char *buf);
enum Tfa98xx_Error (*dsp_msg_read)(struct tfa_device *tfa, int length,
unsigned char *bytes);
enum Tfa98xx_Error (*reg_read)(struct tfa_device *tfa,
unsigned char subaddress,
unsigned short *value);
enum Tfa98xx_Error (*reg_write)(struct tfa_device *tfa,
unsigned char subaddress,
unsigned short value);
enum Tfa98xx_Error (*mem_read)(struct tfa_device *tfa,
unsigned int start_offset, int num_words,
int *pValues);
enum Tfa98xx_Error (*mem_write)(struct tfa_device *tfa,
unsigned short address, int value,
int memtype);
enum Tfa98xx_Error (*tfa_init)(
struct tfa_device *
tfa); /**< init typically for loading optimal settings */
enum Tfa98xx_Error (*dsp_reset)(
struct tfa_device *tfa,
int state); /**< reset the coolflux dsp */
enum Tfa98xx_Error (*dsp_system_stable)(
struct tfa_device *tfa,
int *ready); /**< ready when clocks are stable to allow DSP subsystem access */
enum Tfa98xx_Error (*dsp_write_tables)(
struct tfa_device *tfa,
int sample_rate); /**< write the device/type specific delaytables */
enum Tfa98xx_Error (*auto_copy_mtp_to_iic)(
struct tfa_device *tfa); /**< Set auto_copy_mtp_to_iic */
enum Tfa98xx_Error (*factory_trimmer)(
struct tfa_device
*tfa); /**< Factory trimming for the Boost converter */
int (*set_swprof)(
struct tfa_device *tfa,
unsigned short
new_value); /**< Set the sw profile in the struct and the hw register */
int (*get_swprof)(
struct tfa_device
*tfa); /**< Get the sw profile from the hw register */
int (*set_swvstep)(
struct tfa_device *tfa,
unsigned short
new_value); /**< Set the sw vstep in the struct and the hw register */
int (*get_swvstep)(
struct tfa_device
*tfa); /**< Get the sw vstep from the hw register */
int (*get_mtpb)(
struct tfa_device *tfa); /**< get status of MTB busy bit*/
enum Tfa98xx_Error (*set_mute)(struct tfa_device *tfa,
int mute); /**< set mute */
enum Tfa98xx_Error (*faim_protect)(
struct tfa_device *tfa,
int state); /**< Protect FAIM from being corrupted */
enum Tfa98xx_Error (*set_osc_powerdown)(
struct tfa_device *tfa,
int state); /**< Allow to change internal osc. gating settings */
enum Tfa98xx_Error (*update_lpm)(
struct tfa_device *tfa,
int state); /**< Allow to change lowpowermode settings */
};
/**
* Device states and modifier flags to allow a device/type independent fine
* grained control of the internal state.\n
* Values below 0x10 are referred to as base states which can be or-ed with
* state modifiers, from 0x10 and higher.
*
*/
enum tfa_state {
TFA_STATE_UNKNOWN, /**< unknown or invalid */
TFA_STATE_POWERDOWN, /**< PLL in powerdown, Algo is up/warm */
TFA_STATE_INIT_HW, /**< load I2C/PLL hardware setting (~wait2srcsettings) */
TFA_STATE_INIT_CF, /**< coolflux HW access possible (~initcf) */
TFA_STATE_INIT_FW, /**< DSP framework active (~patch loaded) */
TFA_STATE_OPERATING, /**< Amp and Algo running */
TFA_STATE_FAULT, /**< An alarm or error occurred */
TFA_STATE_RESET, /**< I2C reset and ACS set */
/* --sticky state modifiers-- */
TFA_STATE_MUTE = 0x10, /**< Algo & Amp mute */
TFA_STATE_UNMUTE = 0x20, /**< Algo & Amp unmute */
TFA_STATE_CLOCK_ALWAYS =
0x40, /**< PLL connect to internal oscillator */
TFA_STATE_CLOCK_AUDIO =
0x80, /**< PLL connect to audio clock (BCK/FS) */
TFA_STATE_LOW_POWER = 0x100, /**< lowest possible power state */
};
/**
* This is the main tfa device context structure, it will carry all information
* that is needed to handle a single I2C device instance.
* All functions dealing with the device will need access to the fields herein.
*/
struct tfa_device {
int dev_idx; /**< device container index */
int in_use;
int buffer_size; /**< lowest level max buffer size */
int has_msg; /**< support direct dsp messaging */
int dynamicTDMmode; /**tracking dynamic TDM setting from alsa input stream*/
int bitwidth; /**bitwdith from alsa input stream*/
unsigned char slave_address; /**< I2C slave address (not shifted) */
unsigned short rev; /**< full revid of this device */
unsigned char tfa_family; /**< tfa1/tfa2 */
enum featureSupport supportDrc;
enum featureSupport supportFramework;
enum featureSupport support_saam;
int sw_feature_bits[2]; /**< cached copy of sw feature bits */
int hw_feature_bits; /**< cached copy of hw feature bits */
int profile; /**< active profile */
int vstep; /**< active vstep */
unsigned char spkr_count;
unsigned char spkr_select;
unsigned char support_tcoef; /**< legacy tfa9887, will be removed */
enum Tfa98xx_DAI daimap; /**< supported audio interface types */
int mohm[3]; /**< speaker calibration values in milli ohms -1 is error */
struct tfa_device_ops dev_ops;
uint16_t interrupt_enable[3];
uint16_t interrupt_status[3];
int ext_dsp; /**< respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
int bus; /* TODO fix ext_dsp and bus handling */
int tfadsp_event; /**< enum tfadsp_event_en is for external registry */
int verbose; /**< verbosity level for debug print output */
enum tfa_state
state; /**< last known state or-ed with optional state_modifier */
struct TfaContainer *cnt; /**< the loaded container file */
struct TfaVolumeStepRegisterInfo
*p_regInfo; /**< remember vstep for partial updates */
int partial_enable; /**< enable partial updates */
void *data; /**< typically pointing to Linux driver structure owning this device */
int convert_dsp32; /**< convert 24 bit DSP messages to 32 bit */
int sync_iv_delay; /**< synchronize I/V delay at cold start */
int is_probus_device; /**< probus device: device without internal DSP */
int advance_keys_handling;
int needs_reset; /**< add the reset trigger for SetAlgoParams and SetMBDrc commands */
struct kmem_cache *cachep; /**< Memory allocator handle */
char fw_itf_ver[4]; /* Firmware ITF version */
};
/**
* The tfa_dev_probe is called before accessing any device accessing functions.
* Access to the tfa device register 3 is attempted and will record the
* returned id for further use. If no device responds the function will abort.
* The recorded id will by used by the query functions to fill the remaining
* relevant data fields of the device structure.
* Data such as MTP features that requires device access will only be read when
* explicitly called and the result will be then cached in the struct.
*
* A structure pointer passed to this device needs to refer to existing memory
* space allocated by the caller.
*
* @param slave = I2C slave address of the target device (not shifted)
* @param tfa struct = points to memory that holds the context for this device
* instance
*
* @return
* - 0 if the I2C device responded to a read of register address 3\n
* when the device responds but with an unknown id a warning will be printed
* - -1 if no response from the I2C device
*
*/
int tfa_dev_probe(int slave, struct tfa_device *tfa);
/**
* Start this instance at the profile and vstep as provided.
* The profile and vstep will be loaded first in case the current value differs
* from the requested values.
* Note that this call will not change the mute state of the tfa, which means
* that of this instance was called in muted state the caller will have to
* unmute in order to get audio.
*
* @param tfa struct = pointer to context of this device instance
* @param profile the selected profile to run
* @param vstep the selected vstep to use
* @return tfa_error enum
*/
enum tfa_error tfa_dev_start(struct tfa_device *tfa, int profile, int vstep);
/**
* Stop audio for this instance as gracefully as possible.
* Audio will be muted and the PLL will be shutdown together with any other
* device/type specific settings needed to prevent audio artifacts or
* workarounds.
*
* Note that this call will change state of the tfa to mute and powered down.
*
* @param tfa struct = pointer to context of this device instance
* @return tfa_error enum
*/
enum tfa_error tfa_dev_stop(struct tfa_device *tfa);
/**
* This interface allows a device/type independent fine grained control of the
* internal state of the instance.
* Whenever a base state is requested an attempt is made to actively bring the device
* into this state. However this may depend on external conditions beyond control of
* this software layer. Therefore in case the state cannot be set an erro will
* be returned and the current state remains unchanged.
* The base states, lower values below 0x10, are all mutually exclusive, they higher ones
* can also function as a sticky modifier which means for example that operating
* state could be in either muted or unmuted state. Or in case of init_cf it can be
* internal clock (always) or external audio clock.
* This function is intended to be used for device mute/unmute synchronization
* when called from higher layers. Mostly internal calls will use this to control
* the startup and profile transitions in a device/type independent way.
*
* @param tfa struct = pointer to context of this device instance
* @param state struct = desired device state after function return
* @return tfa_error enum
*/
enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state,
int is_calibration);
/**
* Retrieve the current state of this instance in an active way.
* The state field in tfa structure will reflect the result unless an error is
* returned.
* Note that the hardware state may change on external events an as such this
* field should be treated as volatile.
*
* @param tfa struct = pointer to context of this device instance
* @return tfa_error enum
*
*/
enum tfa_state tfa_dev_get_state(struct tfa_device *tfa);
/**
* Deduce the width from machine driver and decide TDM setting to be
* programmed to the TFA amplifier dynamically
* @param tfa struct = pointer to context of this device instance
* @param width = parmeters read from top layer to decide the applicable TDM settings
* @return tfa_error enum
- 0 if the width received is correct (16/32/24)
* - others if width received is not correct
*/
int tfa_dev_set_tdm_bitwidth(struct tfa_device *tfa, int width);
/*****************************************************************************/
/*****************************************************************************/
/**
* MTP support functions
*/
enum tfa_mtp {
TFA_MTP_OTC, /**< */
TFA_MTP_EX, /**< */
TFA_MTP_RE25, /**< */
TFA_MTP_RE25_PRIM, /**< */
TFA_MTP_RE25_SEC, /**< */
TFA_MTP_LOCK, /**< */
};
/**
*
*/
int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item);
/**
*
*/
enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item,
int value);
//irq
/* tfa2 interrupt support
* !!! enum tfa9912_irq !!!*/
/*
* interrupt bit function to clear
*/
int tfa_irq_clear(struct tfa_device *tfa, int bit);
/*
* return state of irq or -1 if illegal bit
*/
int tfa_irq_get(struct tfa_device *tfa, int bit);
/*
* interrupt bit function that operates on the shadow regs in the handle
*/
int tfa_irq_ena(struct tfa_device *tfa, int bit, int state);
/*
* interrupt bit function that sets the polarity
*/
int tfa_irq_set_pol(struct tfa_device *tfa, int bit, int state);
/*
* mask interrupts by disabling them
*/
int tfa_irq_mask(struct tfa_device *tfa);
/*
* unmask interrupts by enabling them again
*/
int tfa_irq_unmask(struct tfa_device *tfa);
//cnt read
//debug?
/* IRQ handle for tfa987x device */
int tfa987x_irq_enable(struct tfa_device *tfa, int bit, int status);
void tfa987x_irq_mask(struct tfa_device *tfa);
void tfa987x_irq_unmask(struct tfa_device *tfa);
int tfa987x_irq_clear(struct tfa_device *tfa, int bit);
int tfa987x_irq_handle(struct tfa_device *tfa);
#endif /* __TFA_DEVICE_H__ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef TFA98XX_INTERNALS_H
#define TFA98XX_INTERNALS_H
#include "config.h"
#include "tfa_service.h" //TODO cleanup for enum Tfa98xx_Status_ID
/*
* tfadsp_fw_api.c
*/
/**
* Return a text version of the firmware status ID code
* @param status the given status ID code
* @return the firmware status ID string
*/
const char *tfadsp_fw_status_string(enum Tfa98xx_Status_ID status);
int tfadsp_fw_start(struct tfa_device *tfa, int prof_idx, int vstep_idx);
int tfadsp_fw_get_api_version(struct tfa_device *tfa, uint8_t *buffer);
#define FW_MAXTAG 150
int tfadsp_fw_get_tag(struct tfa_device *tfa, uint8_t *buffer);
int tfadsp_fw_get_status_change(struct tfa_device *tfa, uint8_t *buffer);
int tfadsp_fw_set_re25(struct tfa_device *tfa, int prim, int sec);
int tfadsp_fw_get_re25(struct tfa_device *tfa, uint8_t *buffer);
/*
* the order matches the ACK bits order in TFA98XX_CF_STATUS
*/
enum tfa_fw_event { /* not all available on each device */
tfa_fw_i2c_cmd_ack,
tfa_fw_reset_start,
tfa_fw_short_on_mips,
tfa_fw_soft_mute_ready,
tfa_fw_volume_ready,
tfa_fw_error_damage,
tfa_fw_calibrate_done,
tfa_fw_max
};
/* the following type mappings are compiler specific */
#define subaddress_t unsigned char
/* module Ids */
#define MODULE_FRAMEWORK 0
#define MODULE_SPEAKERBOOST 1
#define MODULE_BIQUADFILTERBANK 2
#define MODULE_TAPTRIGGER 5
#define MODULE_SETRE 9
/* RPC commands */
/* SET */
#define FW_PAR_ID_SET_MEMORY 0x03
#define FW_PAR_ID_SET_SENSES_DELAY 0x04
#define FW_PAR_ID_SETSENSESCAL 0x05
#define FW_PAR_ID_SET_INPUT_SELECTOR 0x06
#define FW_PAR_ID_SET_OUTPUT_SELECTOR 0x08
#define FW_PAR_ID_SET_PROGRAM_CONFIG 0x09
#define FW_PAR_ID_SET_GAINS 0x0A
#define FW_PAR_ID_SET_MEMTRACK 0x0B
#define FW_PAR_ID_SET_FWKUSECASE 0x11
#define TFA1_FW_PAR_ID_SET_CURRENT_DELAY 0x03
#define TFA1_FW_PAR_ID_SET_CURFRAC_DELAY 0x06
/* GET */
#define FW_PAR_ID_GET_MEMORY 0x83
#define FW_PAR_ID_GLOBAL_GET_INFO 0x84
#define FW_PAR_ID_GET_FEATURE_INFO 0x85
#define FW_PAR_ID_GET_MEMTRACK 0x8B
#define FW_PAR_ID_GET_TAG 0xFF
#define FW_PAR_ID_GET_API_VERSION 0xFE
#define FW_PAR_ID_GET_STATUS_CHANGE 0x8D
/* Load a full model into SpeakerBoost. */
/* SET */
#define SB_PARAM_SET_ALGO_PARAMS 0x00
#define SB_PARAM_SET_LAGW 0x01
#define SB_PARAM_SET_ALGO_PARAMS_WITHOUT_RESET 0x02
#define SB_PARAM_SET_RE25C 0x05
#define SB_PARAM_SET_LSMODEL 0x06
#define SB_PARAM_SET_MBDRC 0x07
#define SB_PARAM_SET_MBDRC_WITHOUT_RESET 0x08
#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A
#define SB_PARAM_SET_DRC 0x0F
/* GET */
#define SB_PARAM_GET_ALGO_PARAMS 0x80
#define SB_PARAM_GET_LAGW 0x81
#define SB_PARAM_GET_RE25C 0x85
#define SB_PARAM_GET_LSMODEL 0x86
#define SB_PARAM_GET_MBDRC 0x87
#define SB_PARAM_GET_MBDRC_DYNAMICS 0x89
#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A
#define SB_PARAM_GET_TAG 0xFF
#define SB_PARAM_SET_EQ 0x0A /* 2 Equaliser Filters. */
#define SB_PARAM_SET_PRESET 0x0D /* Load a preset */
#define SB_PARAM_SET_CONFIG 0x0E /* Load a config */
#define SB_PARAM_SET_AGCINS 0x10
#define SB_PARAM_SET_CURRENT_DELAY 0x03
#define SB_PARAM_GET_STATE 0xC0
#define SB_PARAM_GET_XMODEL 0xC1 /* Gets current Excursion Model. */
#define SB_PARAM_GET_XMODEL_COEFFS 0x8C /* Get coefficients for XModel */
#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A /* Get excursion filters */
#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A /* Set excursion filters */
/* SET: TAPTRIGGER */
#define TAP_PARAM_SET_ALGO_PARAMS 0x01
#define TAP_PARAM_SET_DECIMATION_PARAMS 0x02
/* GET: TAPTRIGGER*/
#define TAP_PARAM_GET_ALGO_PARAMS 0x81
#define TAP_PARAM_GET_TAP_RESULTS 0x84
/* sets the speaker calibration impedance (@25 degrees celsius) */
#define SB_PARAM_SET_RE0 0x89
#define BFB_PAR_ID_SET_COEFS 0x00
#define BFB_PAR_ID_GET_COEFS 0x80
#define BFB_PAR_ID_GET_CONFIG 0x81
/* for compatibility */
#define FW_PARAM_GET_STATE FW_PAR_ID_GLOBAL_GET_INFO
#define FW_PARAM_GET_FEATURE_BITS FW_PAR_ID_GET_FEATURE_BITS
/* RPC Status results */
#define STATUS_OK 0
#define STATUS_INVALID_MODULE_ID 2
#define STATUS_INVALID_PARAM_ID 3
#define STATUS_INVALID_INFO_ID 4
/* the maximum message length in the communication with the DSP */
#define TFA2_MAX_PARAM_SIZE (507 * 3) /* TFA2 */
#define TFA1_MAX_PARAM_SIZE (145 * 3) /* TFA1 */
#define ROUND_DOWN(a, n) (((a) / (n)) * (n))
/* feature bits */
#define FEATURE1_TCOEF 0x100 /* bit8 set means tCoefA expected */
#define FEATURE1_DRC 0x200 /* bit9 NOT set means DRC expected */
/* DSP firmware xmem defines */
#define TFA1_FW_XMEM_CALIBRATION_DONE 231
#define TFA2_FW_XMEM_CALIBRATION_DONE 516
#define TFA1_FW_XMEM_COUNT_BOOT 0xa1
#define TFA2_FW_XMEM_COUNT_BOOT 512
#define TFA2_FW_XMEM_CMD_COUNT 520
/* note that the following defs rely on the handle variable */
#define TFA_FW_XMEM_CALIBRATION_DONE TFA_FAM_FW(tfa, XMEM_CALIBRATION_DONE)
#define TFA_FW_XMEM_COUNT_BOOT TFA_FAM_FW(tfa, XMEM_COUNT_BOOT)
#define TFA_FW_XMEM_CMD_COUNT TFA_FAM_FW(tfa, XMEM_CMD_COUNT)
#define TFA2_FW_ReZ_SCALE 65536
#define TFA1_FW_ReZ_SCALE 16384
#endif /* TFA98XX_INTERNALS_H */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* tfa_ext.h
*
* Created on: Jun 8, 2016
* Author: wim
*/
#ifndef TFA_SRC_TFA_EXT_H_
#define TFA_SRC_TFA_EXT_H_
#include "tfa_device.h"
/*
* events
*/
/** Maximum value for enumerator */
#define LVM_MAXENUM (0xffff)
/**
This enum type specifies the different events that may trigger a callback.
*/
enum tfadsp_event_en {
TFADSP_CMD_ACK = 1, /**< Command handling is completed */
TFADSP_SOFT_MUTE_READY = 8, /**< Muting completed */
TFADSP_VOLUME_READY = 16, /**< Volume change completed */
TFADSP_DAMAGED_SPEAKER = 32, /**< Damaged speaker was detected */
TFADSP_CALIBRATE_DONE = 64, /**< Calibration is completed */
TFADSP_SPARSESIG_DETECTED = 128, /**< Sparse signal detected */
TFADSP_CMD_READY = 256, /**< Ready to receive commands */
TFADSP_EXT_PWRUP = 0x8000, /**< DSP API has started, powered up */
TFADSP_EXT_PWRDOWN = 0x8001, /**< DSP API stopped, power down */
TFADSP_EVENT_DUMMY = LVM_MAXENUM
};
typedef int (*tfa_event_handler_t)(struct tfa_device *tfa,
enum tfadsp_event_en tfadsp_event);
typedef int (*dsp_send_message_t)(struct tfa_device *tfa, int length,
const char *buf);
typedef int (*dsp_read_message_t)(struct tfa_device *tfa, int length,
char *buf);
typedef int (*dsp_write_reg_t)(struct tfa_device *tfa, unsigned char subaddress,
unsigned short value);
int tfa_ext_register(dsp_write_reg_t tfa_write_reg,
dsp_send_message_t tfa_send_message,
dsp_read_message_t tfa_read_message,
tfa_event_handler_t *tfa_event_handler);
#endif /* TFA_SRC_TFA_EXT_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
internal functions for TFA layer (not shared with SRV and HAL layer!)
*/
#ifndef __TFA_INTERNAL_H__
#define __TFA_INTERNAL_H__
#include "tfa_dsp_fw.h"
#include "tfa_ext.h"
#if __GNUC__ >= 4
#define TFA_INTERNAL __attribute__((visibility("hidden")))
#else
#define TFA_INTERNAL
#endif
#define TFA98XX_GENERIC_SLAVE_ADDRESS 0x1C
TFA_INTERNAL enum Tfa98xx_Error tfa98xx_check_rpc_status(struct tfa_device *tfa,
int *pRpcStatus);
TFA_INTERNAL enum Tfa98xx_Error tfa98xx_wait_result(struct tfa_device *tfa,
int waitRetryCount);
#endif /* __TFA_INTERNAL_H__ */

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/*
* Copyright 2015-2018 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _TFA_PLATFORM_INTERFACE_DEFINITION_H_
#define _TFA_PLATFORM_INTERFACE_DEFINITION_H_
#define AFE_MODULE_ID_TFADSP_RX (0x1000B911)
#define AFE_MODULE_ID_TFADSP_TX (0x1000B912)
#define AFE_PARAM_ID_TFADSP_TX_SET_ENABLE (0x1000B920)
#define AFE_PARAM_ID_TFADSP_RX_CFG (0x1000B921)
#define AFE_PARAM_ID_TFADSP_RX_GET_RESULT (0x1000B922)
#define AFE_PARAM_ID_TFADSP_RX_SET_BYPASS (0x1000B923)
#if defined(CONFIG_MACH_XIAOMI_MUNCH)
#define TFA_USING_TERTIARY_MI2S
#else
#define TFA_USING_PRIMARY_MI2S
#endif
#if defined(TFA_USING_SECONDARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_SECONDARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_SECONDARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "SEC_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "SEC_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "SECONDARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_SECONDARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_SECONDARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Secondary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Secondary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "SEC_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_TERTIARY_TDM)
//PLATFORM_RX_VI_FB_RX_MUX_TEXT, NULL, PLATFORM_RX_VI_FB_MUX_NAME},
//PLATFORM_RX_VI_FB_MUX_NAME, PLATFORM_RX_VI_FB_TX_MUX_TEXT, PLATFORM_RX_VI_FB_TX_MUX_TEXT},
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_TERTIARY_TDM_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_TERTIARY_TDM_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "TERT_TDM_RX_0"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "TERT_TDM_TX_0"
#define PLATFORM_RX_VI_FB_MUX_NAME "TERTIARY_TDM_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_TERT_TDM_TX_0
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_TERT_TDM_RX_0
#define TFA_TX_HOSTLESS_CODEC_NAME "Tertiary TDM0 Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Tertiary TDM0 Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "TERT_TDM_TX_0_HOSTLESS"
#elif defined(TFA_USING_TERTIARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_TERTIARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_TERTIARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "TERT_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "TERT_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "TERTIARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_TERTIARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_TERTIARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Tertiary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Tertiary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "TERT_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_QUATERNARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUATERNARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUATERNARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUAT_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUAT_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "QUATERNARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUATERNARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUATERNARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Quaternary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Quaternary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUAT_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_QUINARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUINARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUINARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUIN_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUIN_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "QUINARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUINARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUINARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Quinary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Quinary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUIN_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_PRIMARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_PRIMARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_PRIMARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "PRI_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "PRI_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "PRI_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_PRI_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_PRI_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Primary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Primary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "PRI_MI2S_TX_HOSTLESS"
#else
#error you should define which mi2s will be used for TFA device.
#endif
#endif /* _TFA_PLATFORM_INTERFACE_DEFINITION_H_ */

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techpack/audio/asoc/codecs/tfa9874/inc/tfa_service.h Normal file
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#ifndef _VERSIONS_H
#define TFA98XX_GIT_VERSIONS "v6.5.2_xxxxxxxxxx"
#define _VERSIONS_H
#endif

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "dbgprint.h"
#include "tfa_service.h"
#include "tfa98xx_tfafieldnames.h"
/* support for error code translation into text */
static char latest_errorstr[64];
const char *tfa98xx_get_error_string(enum Tfa98xx_Error error)
{
const char *pErrStr;
switch (error) {
case Tfa98xx_Error_Ok:
pErrStr = "Ok";
break;
case Tfa98xx_Error_DSP_not_running:
pErrStr = "DSP_not_running";
break;
case Tfa98xx_Error_Bad_Parameter:
pErrStr = "Bad_Parameter";
break;
case Tfa98xx_Error_NotOpen:
pErrStr = "NotOpen";
break;
case Tfa98xx_Error_InUse:
pErrStr = "InUse";
break;
case Tfa98xx_Error_RpcBusy:
pErrStr = "RpcBusy";
break;
case Tfa98xx_Error_RpcModId:
pErrStr = "RpcModId";
break;
case Tfa98xx_Error_RpcParamId:
pErrStr = "RpcParamId";
break;
case Tfa98xx_Error_RpcInvalidCC:
pErrStr = "RpcInvalidCC";
break;
case Tfa98xx_Error_RpcInvalidSeq:
pErrStr = "RpcInvalidSeq";
break;
case Tfa98xx_Error_RpcInvalidParam:
pErrStr = "RpcInvalidParam";
break;
case Tfa98xx_Error_RpcBufferOverflow:
pErrStr = "RpcBufferOverflow";
break;
case Tfa98xx_Error_RpcCalibBusy:
pErrStr = "RpcCalibBusy";
break;
case Tfa98xx_Error_RpcCalibFailed:
pErrStr = "RpcCalibFailed";
break;
case Tfa98xx_Error_Not_Supported:
pErrStr = "Not_Supported";
break;
case Tfa98xx_Error_I2C_Fatal:
pErrStr = "I2C_Fatal";
break;
case Tfa98xx_Error_I2C_NonFatal:
pErrStr = "I2C_NonFatal";
break;
case Tfa98xx_Error_StateTimedOut:
pErrStr = "WaitForState_TimedOut";
break;
default:
sprintf(latest_errorstr, "Unspecified error (%d)", (int)error);
pErrStr = latest_errorstr;
}
return pErrStr;
}
/*****************************************************************************/
/* bitfield lookups */
/*
* generic table lookup functions
*/
/**
* lookup bf in table
* return 'unkown' if not found
*/
static char *tfa_bf2name(tfaBfName_t *table, uint16_t bf)
{
int n = 0;
do {
if ((table[n].bfEnum & 0xfff0) == (bf & 0xfff0)) {
return table[n].bfName;
}
} while (table[n++].bfEnum != 0xffff);
return table[n - 1].bfName; /* last name says unkown */
}
/**
* lookup name in table
* return 0xffff if not found
*/
static uint16_t tfa_name2bf(tfaBfName_t *table, const char *name)
{
int n = 0;
do {
if (strcasecmp(name, table[n].bfName) == 0)
return table[n].bfEnum;
} while (table[n++].bfEnum != 0xffff);
return 0xffff;
}
/*
* tfa2 bitfield name table
*/
TFA2_NAMETABLE
TFA2_BITNAMETABLE
/*
* tfa1 bitfield name tables
*/
TFA1_NAMETABLE
TFA9896_NAMETABLE
TFA9872_NAMETABLE
TFA9874_NAMETABLE
TFA9890_NAMETABLE
TFA9891_NAMETABLE
TFA9887_NAMETABLE
TFA1_BITNAMETABLE
TFA9912_NAMETABLE
TFA9894_NAMETABLE
TFA9896_BITNAMETABLE
TFA9872_BITNAMETABLE
TFA9874_BITNAMETABLE
TFA9912_BITNAMETABLE
TFA9890_BITNAMETABLE
TFA9891_BITNAMETABLE
TFA9887_BITNAMETABLE
TFA9894_BITNAMETABLE
char *tfaContBitName(uint16_t num, unsigned short rev)
{
char *name;
/* end of list for the unknown string */
int tableLength = sizeof(Tfa1DatasheetNames) / sizeof(tfaBfName_t);
const char *unknown = Tfa1DatasheetNames[tableLength - 1].bfName;
switch (rev & 0xff) {
case 0x88:
name = tfa_bf2name(Tfa2BitNames, num);
break;
case 0x97:
name = tfa_bf2name(Tfa1BitNames, num);
break;
case 0x96:
name = tfa_bf2name(Tfa9896BitNames, num);
break;
case 0x72:
name = tfa_bf2name(Tfa9872BitNames, num);
break;
case 0x74:
name = tfa_bf2name(Tfa9874BitNames, num);
break;
case 0x92:
name = tfa_bf2name(Tfa9891BitNames, num);
break;
case 0x91:
case 0x80:
case 0x81:
name = tfa_bf2name(Tfa9890BitNames, num); /* my tabel 1st */
if (strcmp(unknown, name) == 0)
name = tfa_bf2name(Tfa1BitNames,
num); /* try generic table */
break;
case 0x12:
name = tfa_bf2name(Tfa9887BitNames, num); /* my tabel 1st */
if (strcmp(unknown, name) == 0)
name = tfa_bf2name(Tfa1BitNames,
num); /* try generic table */
break;
case 0x13:
name = tfa_bf2name(Tfa9912BitNames, num);
break;
case 0x94:
name = tfa_bf2name(Tfa9894BitNames, num);
break;
default:
PRINT_ERROR("unknown REVID:0x%0x\n", rev);
tableLength = sizeof(Tfa1BitNames) /
sizeof(tfaBfName_t); /* end of list */
name = (char *)unknown;
break;
}
return name;
}
char *tfaContDsName(uint16_t num, unsigned short rev)
{
char *name;
/* end of list for the unknown string */
int tableLength = sizeof(Tfa1DatasheetNames) / sizeof(tfaBfName_t);
const char *unknown = Tfa1DatasheetNames[tableLength - 1].bfName;
switch (rev & 0xff) {
case 0x88:
name = tfa_bf2name(Tfa2DatasheetNames, num);
break;
case 0x97:
name = tfa_bf2name(Tfa1DatasheetNames, num);
break;
case 0x96:
name = tfa_bf2name(Tfa9896DatasheetNames, num);
break;
case 0x72:
name = tfa_bf2name(Tfa9872DatasheetNames, num);
break;
case 0x74:
name = tfa_bf2name(Tfa9874DatasheetNames, num);
break;
case 0x92:
name = tfa_bf2name(Tfa9891DatasheetNames, num);
break;
case 0x91:
case 0x80:
case 0x81:
name = tfa_bf2name(Tfa9890DatasheetNames,
num); /* my tabel 1st */
if (strcmp(unknown, name) == 0)
name = tfa_bf2name(Tfa1DatasheetNames,
num); /* try generic table */
break;
case 0x12:
name = tfa_bf2name(Tfa9887DatasheetNames,
num); /* my tabel 1st */
if (strcmp(unknown, name) == 0)
name = tfa_bf2name(Tfa1DatasheetNames,
num); /* try generic table */
break;
case 0x13:
name = tfa_bf2name(Tfa9912DatasheetNames, num);
break;
case 0x94:
name = tfa_bf2name(Tfa9894DatasheetNames, num);
break;
default:
PRINT_ERROR("unknown REVID:0x%0x\n", rev);
tableLength = sizeof(Tfa1DatasheetNames) /
sizeof(tfaBfName_t); /* end of list */
name = (char *)unknown;
break;
}
return name;
}
char *tfaContBfName(uint16_t num, unsigned short rev)
{
char *name;
/* end of list for the unknown string */
int tableLength = sizeof(Tfa1DatasheetNames) / sizeof(tfaBfName_t);
const char *unknown = Tfa1DatasheetNames[tableLength - 1].bfName;
/* if datasheet name does not exist look for bitfieldname */
name = tfaContDsName(num, rev);
if (strcmp(unknown, name) == 0)
name = tfaContBitName(num, rev);
return name;
}
uint16_t tfaContBfEnum(const char *name, unsigned short rev)
{
uint16_t bfnum;
switch (rev & 0xff) {
case 0x88:
bfnum = tfa_name2bf(Tfa2DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa2BitNames,
name); /* try long bitname table */
break;
case 0x97:
bfnum = tfa_name2bf(Tfa1DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa1BitNames,
name); /* try generic table */
break;
case 0x96:
bfnum = tfa_name2bf(Tfa9896DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa9896BitNames,
name); /* try generic table */
break;
case 0x72:
bfnum = tfa_name2bf(Tfa9872DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa9872BitNames,
name); /* try long bitname table */
break;
case 0x74:
bfnum = tfa_name2bf(Tfa9874DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa9874BitNames,
name); /* try long bitname table */
break;
case 0x92:
bfnum = tfa_name2bf(Tfa9891DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa9891BitNames,
name); /* try long bitname table */
break;
case 0x91:
case 0x80:
case 0x81:
bfnum = tfa_name2bf(Tfa9890DatasheetNames,
name); /* my tabel 1st */
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa1DatasheetNames,
name); /* try generic table */
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa1BitNames,
name); /* try 2nd generic table */
break;
case 0x12:
bfnum = tfa_name2bf(Tfa9887DatasheetNames,
name); /* my tabel 1st */
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa1DatasheetNames,
name); /* try generic table */
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa1BitNames,
name); /* try 2nd generic table */
break;
case 0x13:
bfnum = tfa_name2bf(Tfa9912DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa9912BitNames,
name); /* try long bitname table */
break;
case 0x94:
bfnum = tfa_name2bf(Tfa9894DatasheetNames, name);
if (bfnum == 0xffff)
bfnum = tfa_name2bf(Tfa9894BitNames,
name); /* try long bitname table */
break;
default:
PRINT_ERROR("unknown REVID:0x%0x\n", rev);
bfnum = 0xffff;
break;
}
return bfnum;
}
/*
* check all lists for a hit
* this is for the parser to know if it's an existing bitname
*/
uint16_t tfaContBfEnumAny(const char *name)
{
uint16_t bfnum;
/* datasheet names first */
bfnum = tfa_name2bf(Tfa2DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa1DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9891DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9890DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9887DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9872DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9874DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9896DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9912DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9894DatasheetNames, name);
if (bfnum != 0xffff)
return bfnum;
/* and then bitfield names */
bfnum = tfa_name2bf(Tfa2BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa1BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9891BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9890BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9887BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9872BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9874BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9896BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9912BitNames, name);
if (bfnum != 0xffff)
return bfnum;
bfnum = tfa_name2bf(Tfa9894BitNames, name);
return bfnum;
}

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techpack/audio/asoc/codecs/tfa98xx/Kbuild Executable file
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# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.19
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
TFA_INC := -I$(AUDIO_ROOT)/asoc/codecs/tfa98xx/inc
# for TFA9874 Amplifer
ifdef CONFIG_SND_SOC_TFA9874
TFA98XX_OBJS += src/tfa98xx.o
TFA98XX_OBJS += src/tfa_container.o
TFA98XX_OBJS += src/tfa_dsp.o
TFA98XX_OBJS += src/tfa_init.o
#TFA98XX_OBJS += src/tfa_debug.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC) \
$(TFA_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__\
-DDEBUG
ifeq ($(CONFIG_MACH_XIAOMI_LMI),y)
CDEFINES += -DTFA_NON_DSP_SOLUTION
CDEFINES += -DNXP_SPEAKERBOOST_V3
endif
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_TFA9874) += tfa98xx_dlkm.o
tfa98xx_dlkm-y := $(TFA98XX_OBJS)

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
Linux kernel specific definitions used by code shared with
Linux/Windows user space.
*/
#ifndef __CONFIG_LINUX_KERNEL_INC__
#define __CONFIG_LINUX_KERNEL_INC__
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/crc32.h>
#include <linux/ftrace.h>
#define _ASSERT(e)
#define PRINT_ASSERT(e) \
if ((e)) \
printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
#if defined(CONFIG_TRACING) && defined(DEBUG)
#define tfa98xx_trace_printk(...) trace_printk(__VA_ARGS__)
#else
#define tfa98xx_trace_printk(...)
#endif
#endif /* __CONFIG_LINUX_KERNEL_INC__ */

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _DBGPRINT_H
#define _DBGPRINT_H
/* Debugging macro's. */
#ifndef DEBUG
#define DEBUG
#endif
#ifndef ASSERT
//#define ASSERT
#endif
//TODO wwwim
#ifndef _ASSERT
#define _ASSERT(e)
#endif
#ifndef PREFIX
#define PREFIX "tfa98xx: "
#define DRIVER_NAME "tfa98xx"
#endif
#ifdef __KERNEL__
#ifdef DEBUG
#define _DEBUG(level, fmt, va...) \
do { \
if (unlikely(debug >= (level))) \
printk(KERN_INFO PREFIX "%s:%d: " fmt, __func__, \
__LINE__, ##va); \
} while (0)
#else
#define _DEBUG(level, fmt, va...) \
do { \
} while (0)
#endif
#define MSG(fmt, va...) \
printk(KERN_INFO PREFIX "%s:%d: " fmt, __func__, __LINE__, ##va)
#define _ERRORMSG(fmt, va...) \
printk(KERN_ERR PREFIX "ERROR %s:%d: " fmt, __func__, __LINE__, ##va)
#define DEBUG0(x...) MSG(x)
#define DEBUG1(x...) _DEBUG(1, x)
#define DEBUG2(x...) _DEBUG(2, x)
#define DEBUG3(x...) _DEBUG(3, x)
#define ERRORMSG(x...) _ERRORMSG(x)
#define PRINT(x...) printk(x)
#define PRINT_ERROR(x...) printk(KERN_INFO PREFIX " **ERROR** " x)
#define PRINT_ASSERT(e) \
if ((e)) \
printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
#define PRINT_ENTRY DEBUG2("+[%s]\n", __func__)
#define PRINT_EXIT DEBUG2("-[%s]\n", __func__)
#ifdef ASSERT
#define assert(cond, action) \
do { \
if (unlikely(!(cond))) { \
DEBUG0("Assert: %s\n", #cond); \
action; \
} \
} while (0)
#else
#define assert(cond, action) \
do { \
} while (0)
#endif
#else /* __KERNEL__ */
#if defined(WIN32) || defined(_X64)
#include <stdio.h>
/* user mode */
#ifdef DEBUG
#define _DEBUGMSG(level, fmt, ...) \
printf(PREFIX "%s:%d: " fmt, __FUNCTION__, __LINE__, __VA_ARGS__);
#else
#define _DEBUGMSG(level, fmt, ...) \
do { \
} while (0)
#endif
#define _ERRORMSG(fmt, ...) \
printf(PREFIX "%s:%s:%d: " fmt, __FILE__, __FUNCTION__, __LINE__, \
__VA_ARGS__)
#define DEBUG0(...) MSG(__VA_ARGS__)
#define DEBUG1(...) _DEBUGMSG(1, __VA_ARGS__)
#define DEBUG2(...) _DEBUGMSG(2, __VA_ARGS__)
#define DEBUG3(...) _DEBUGMSG(3, __VA_ARGS__)
#define ERRORMSG(fmt, ...) _ERRORMSG(fmt, __VA_ARGS__)
#define PRINT(...) printf(__VA_ARGS__)
/*
# define PRINT(...) { FILE *stream; \
if((stream = freopen("nxp_tfa.txt", "ab+", stdout)) == NULL) exit(-1); \
printf(__VA_ARGS__); \
freopen( "CON", "ab+", stdout ); \
}
*/
#define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__)
#define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__)
#define PRINT_ASSERT(e) \
if ((e)) \
fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#elif defined(__CODE_RED)
#include "app_global.h"
#ifdef DEBUG
#define _DEBUG(level, fmt, va...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, va))
//printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va);
#else
#define _DEBUG(level, fmt, va...) \
do { \
} while (0)
#endif
#define MSG(fmt, ...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__))
//printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va)
//TB_TRACE_INF(TbTracePfx2(APP_PFX,TB_FUNC,"path=%s, chan=%u, muted=%s, vol=%d\n",
// path->isRecording ? "recording" : "playback",
// i,
// channelVol.currentMuteValue ? "YES" : "NO",
// channelVol.currentVolumeValue
// ));
//# define _ERRORMSG(fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va))
#define ERRORMSG(...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__))
//fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va)
#define DEBUG0(x...) MSG(x)
#define DEBUG1(x...) _DEBUG(1, x)
#define DEBUG2(x...) _DEBUG(2, x)
#define DEBUG3(x...) _DEBUG(3, x)
//# define ERRORMSG(x...) _ERRORMSG(x)
#define PRINT(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
//printf(x)
#define PRINT_ERROR(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
//fprintf(stderr,__VA_ARGS__)
#define PRINT_FILE(file, x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
//fprintf(file,__VA_ARGS__)
#define PRINT_ASSERT(e)
//TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,Tfa98xx_GetErrorString(e)))
//if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#else
#include <stdio.h>
/* user mode */
#ifdef DEBUG
#define _DEBUG(level, fmt, va...) \
printf(PREFIX "%s:%d: " fmt, __func__, __LINE__, ##va);
#else
#define _DEBUG(level, fmt, va...) \
do { \
} while (0)
#endif
#define MSG(fmt, va...) \
printf(PREFIX "%s:%s:%d: " fmt, __FILE__, __func__, __LINE__, ##va)
#define _ERRORMSG(fmt, va...) \
fprintf(stderr, PREFIX "ERROR %s:%s:%d: " fmt, __FILE__, __func__, \
__LINE__, ##va)
#define DEBUG0(x...) MSG(x)
#define DEBUG1(x...) _DEBUG(1, x)
#define DEBUG2(x...) _DEBUG(2, x)
#define DEBUG3(x...) _DEBUG(3, x)
#define ERRORMSG(x...) _ERRORMSG(x)
#define PRINT(x...) printf(x)
#define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__)
#define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__)
#define PRINT_ASSERT(e) \
if ((e)) \
fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n", \
__FUNCTION__, __FILE__, __LINE__, e)
//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#endif /* WIN32 */
#endif /* user */
#endif /* _DBGPRINT_H --------------- */

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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SPK_ID_H_
#define __SPK_ID_H_
#include <linux/types.h>
#include <linux/of.h>
#define PIN_PULL_DOWN 0
#define PIN_PULL_UP 1
#define PIN_FLOAT 2
#define VENDOR_ID_NONE 0
#define VENDOR_ID_AAC 1
#define VENDOR_ID_SSI 2
#define VENDOR_ID_GOER 3
#define VENDOR_ID_UNKNOWN 4
extern int spk_id_get_pin_3state(struct device_node *np);
#endif

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/*
* Copyright 2015-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TFA_H_
#define TFA_H_
/* set the limit for the container file length */
#define TFA_MAX_CNT_LENGTH (256 * 1024)
extern struct tfa_device **devs;
/**
* tfa error return codes
*/
enum tfa_error {
tfa_error_ok, /**< no error */
tfa_error_device, /**< no response from device */
tfa_error_bad_param, /**< parameter no accepted */
tfa_error_noclock, /**< required clock not present */
tfa_error_timeout, /**< a timeout occurred */
tfa_error_dsp, /**< a DSP error was returned */
tfa_error_container, /**< no or wrong container file */
tfa_error_max /**< impossible value, max enum */
};
enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx);
struct tfa_device **tfa_devs_create(int count);
void tfa_devs_destroy(int count);
struct tfa_device **tfa_get_device_struct(void);
/*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/
#ifdef __KERNEL__
int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep,
u8 pcm_format);
#else
int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep);
#endif
/*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/
void tfa_lp_mode_interrupt(struct tfa_device *tfa);
#endif /* TFA_H_ */

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/** Filename: Tfa9887_TfaFieldnames.h
* This file was generated automatically on 04/14/15 at 10:23:40.
* Source file: TFA9897N1B_I2C_list_URT_source_v34_87Only.xls
*/
#define TFA9887_I2CVERSION 34
#define TFA9895_I2CVERSION 34
#define TFA9887_NAMETABLE \
static tfaBfName_t Tfa9887DatasheetNames[] = { \
{ 0x402, \
"I2SF" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"CHS12" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"CHS3" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"CHSA" }, /* Input selection for amplifier , */ \
{ 0x4b0, \
"I2SDOE" }, /* Enable data output , */ \
{ 0x4c3, \
"I2SSR" }, /* sample rate setting , */ \
{ 0x500, \
"BSSBY" }, /* , */ \
{ 0x511, \
"BSSCR" }, /* 00 = 0.56 dB/Sample , */ \
{ 0x532, \
"BSST" }, /* 000 = 2.92V , */ \
{ 0x5f0, \
"I2SDOC" }, /* selection data out , */ \
{ 0xa02, \
"DOLS" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"DORS" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"SPKL" }, /* Selection speaker induction , */ \
{ 0xa91, \
"SPKR" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"DCFG" }, /* DCDC speaker current compensation gain , */ \
{ 0x4134, \
"PWMDEL" }, /* PWM DelayBits to set the delay , */ \
{ 0x4180, \
"PWMSH" }, /* PWM Shape , */ \
{ 0x4190, \
"PWMRE" }, /* PWM Bitlength in noise shaper , */ \
{ 0x48e1, \
"TCC" }, /* sample & hold track time: , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};
#define TFA9887_BITNAMETABLE \
static tfaBfName_t Tfa9887BitNames[] = { \
{ 0x402, \
"i2s_seti" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"chan_sel1" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"lr_sw_i2si2" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"input_sel" }, /* Input selection for amplifier , */ \
{ 0x4b0, \
"enbl_datao" }, /* Enable data output , */ \
{ 0x4c3, \
"i2s_fs" }, /* sample rate setting , */ \
{ 0x500, \
"bypass_clipper" }, /* , */ \
{ 0x511, \
"vbat_prot_attacktime[1:0]" }, /* 00 = 0.56 dB/Sample , */ \
{ 0x532, \
"vbat_prot_thlevel[2:0]" }, /* 000 = 2.92V , */ \
{ 0x5d0, \
"reset_min_vbat" }, /* to reset the clipper via I2C in case the CF is bypassed, */ \
{ 0x5f0, \
"datao_sel" }, /* selection data out , */ \
{ 0xa02, \
"sel_i2so_l" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"sel_i2so_r" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"ctrl_spkr_coil" }, /* Selection speaker induction , */ \
{ 0xa91, \
"ctrl_spr_res" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"ctrl_dcdc_spkr_i_comp_gain" }, /* DCDC speaker current compensation gain , */ \
{ 0xaf0, \
"ctrl_dcdc_spkr_i_comp_sign" }, /* DCDC speaker current compensation sign , */ \
{ 0x4100, \
"bypass_hp" }, /* bypass_hp, to bypass the hp filter byhind the CoolFlux, */ \
{ 0x4110, \
"hard_mute" }, /* hard mute setting in HW , */ \
{ 0x4120, \
"soft_mute" }, /* Soft mute setting in HW , */ \
{ 0x4134, \
"PWM_Delay[4:0]" }, /* PWM DelayBits to set the delay , */ \
{ 0x4180, \
"PWM_Shape" }, /* PWM Shape , */ \
{ 0x4190, \
"PWM_BitLength" }, /* PWM Bitlength in noise shaper , */ \
{ 0x4800, \
"ctrl_negin" }, /* , */ \
{ 0x4810, \
"ctrl_cs_sein" }, /* , */ \
{ 0x4820, \
"ctrl_coincidencecs" }, /* HIGH => Prevent dcdc switching during clk_cs_clksh, */ \
{ 0x4876, \
"delay_se_neg[6:0]" }, /* delayshiftse2 , */ \
{ 0x48e1, \
"ctrl_cs_ttrack[1:0]" }, /* sample & hold track time: , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};

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/** Filename: Tfa9890_TfaFieldnames.h
* This file was generated automatically on 04/07/15 at 14:46:37.
* Source file: TFA9897N1B_I2C_list_URT_source_v34_90Only.xls
*/
#define TFA9890_I2CVERSION 34
#define TFA9890_NAMETABLE \
static tfaBfName_t Tfa9890DatasheetNames[] = { \
{ 0x402, \
"I2SF" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"CHS12" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"CHS3" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"CHSA" }, /* Input selection for amplifier , */ \
{ 0x481, \
"I2SDOC" }, /* selection data out , */ \
{ 0x4a0, \
"DISP" }, /* idp protection , */ \
{ 0x4b0, \
"I2SDOE" }, /* Enable data output , */ \
{ 0x4c3, \
"I2SSR" }, /* sample rate setting , */ \
{ 0x732, \
"DCMCC" }, /* Max boost coil current - step of 500 mA , */ \
{ 0x9c0, \
"CCFD" }, /* Selection CoolFlux Clock , */ \
{ 0x9d0, \
"ISEL" }, /* selection input 1 or 2 , */ \
{ 0xa02, \
"DOLS" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"DORS" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"SPKL" }, /* Selection speaker induction , */ \
{ 0xa91, \
"SPKR" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"DCFG" }, /* DCDC speaker current compensation gain , */ \
{ 0xf00, \
"VDDD" }, /* mask flag_por for interupt generation , */ \
{ 0xf10, \
"OTDD" }, /* mask flag_otpok for interupt generation , */ \
{ 0xf20, \
"OVDD" }, /* mask flag_ovpok for interupt generation , */ \
{ 0xf30, \
"UVDD" }, /* mask flag_uvpok for interupt generation , */ \
{ 0xf40, \
"OCDD" }, /* mask flag_ocp_alarm for interupt generation , */ \
{ 0xf50, \
"CLKD" }, /* mask flag_clocks_stable for interupt generation , */ \
{ 0xf60, \
"DCCD" }, /* mask flag_pwrokbst for interupt generation , */ \
{ 0xf70, \
"SPKD" }, /* mask flag_cf_speakererror for interupt generation , */ \
{ 0xf80, \
"WDD" }, /* mask flag_watchdog_reset for interupt generation , */ \
{ 0xf90, \
"LCLK" }, /* mask flag_lost_clk for interupt generation , */ \
{ 0xfe0, \
"INT" }, /* enabling interrupt , */ \
{ 0xff0, \
"INTP" }, /* Setting polarity interupt , */ \
{ 0x8f0f, \
"VERSION" }, /* (key1 protected) , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};
#define TFA9890_BITNAMETABLE \
static tfaBfName_t Tfa9890BitNames[] = { \
{ 0x402, \
"i2s_seti" }, /* I2SFormat data 1 input: , */ \
{ 0x431, \
"chan_sel1" }, /* ChannelSelection data1 input (In CoolFlux) , */ \
{ 0x450, \
"lr_sw_i2si2" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \
{ 0x461, \
"input_sel" }, /* Input selection for amplifier , */ \
{ 0x481, \
"datao_sel" }, /* selection data out , */ \
{ 0x4a0, \
"disable_idp" }, /* idp protection , */ \
{ 0x4b0, \
"enbl_datao" }, /* Enable data output , */ \
{ 0x4c3, \
"i2s_fs" }, /* sample rate setting , */ \
{ 0x732, \
"ctrl_bstcur" }, /* Max boost coil current - step of 500 mA , */ \
{ 0x9c0, \
"sel_cf_clk" }, /* Selection CoolFlux Clock , */ \
{ 0x9d0, \
"intf_sel" }, /* selection input 1 or 2 , */ \
{ 0xa02, \
"sel_i2so_l" }, /* Output selection dataout left channel , */ \
{ 0xa32, \
"sel_i2so_r" }, /* Output selection dataout right channel , */ \
{ 0xa62, \
"ctrl_spkr_coil" }, /* Selection speaker induction , */ \
{ 0xa91, \
"ctrl_spr_res" }, /* Selection speaker impedance , */ \
{ 0xab3, \
"ctrl_dcdc_spkr_i_comp_gain" }, /* DCDC speaker current compensation gain , */ \
{ 0xaf0, \
"ctrl_dcdc_spkr_i_comp_sign" }, /* DCDC speaker current compensation sign , */ \
{ 0xf00, \
"flag_por_mask" }, /* mask flag_por for interupt generation , */ \
{ 0xf10, \
"flag_otpok_mask" }, /* mask flag_otpok for interupt generation , */ \
{ 0xf20, \
"flag_ovpok_mask" }, /* mask flag_ovpok for interupt generation , */ \
{ 0xf30, \
"flag_uvpok_mask" }, /* mask flag_uvpok for interupt generation , */ \
{ 0xf40, \
"flag_ocp_alarm_mask" }, /* mask flag_ocp_alarm for interupt generation , */ \
{ 0xf50, \
"flag_clocks_stable_mask" }, /* mask flag_clocks_stable for interupt generation , */ \
{ 0xf60, \
"flag_pwrokbst_mask" }, /* mask flag_pwrokbst for interupt generation , */ \
{ 0xf70, \
"flag_cf_speakererror_mask" }, /* mask flag_cf_speakererror for interupt generation , */ \
{ 0xf80, \
"flag_watchdog_reset_mask" }, /* mask flag_watchdog_reset for interupt generation , */ \
{ 0xf90, \
"flag_lost_clk_mask" }, /* mask flag_lost_clk for interupt generation , */ \
{ 0xfe0, \
"enable_interrupt" }, /* enabling interrupt , */ \
{ 0xff0, \
"invert_int_polarity" }, /* Setting polarity interupt , */ \
{ 0x4700, \
"switch_fb" }, /* switch_fb , */ \
{ 0x4713, \
"se_hyst" }, /* se_hyst , */ \
{ 0x4754, \
"se_level" }, /* se_level , */ \
{ 0x47a5, \
"ktemp" }, /* temperature compensation trimming , */ \
{ 0x8f0f, \
"production_data6" }, /* (key1 protected) , */ \
{ 0xffff, "Unknown bitfield enum" } /* not found */ \
};

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __TFA98XX_INC__
#define __TFA98XX_INC__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/list.h>
#include <linux/miscdevice.h>
#include "tfa_device.h"
#include "tfa_container.h"
#include "config.h"
/* max. length of a alsa mixer control name */
#define MAX_CONTROL_NAME 48
#define TFA98XX_MAX_REGISTER 0xff
#define TFA98XX_FLAG_SKIP_INTERRUPTS (1 << 0)
#define TFA98XX_FLAG_SAAM_AVAILABLE (1 << 1)
#define TFA98XX_FLAG_STEREO_DEVICE (1 << 2)
#define TFA98XX_FLAG_MULTI_MIC_INPUTS (1 << 3)
#define TFA98XX_FLAG_TAPDET_AVAILABLE (1 << 4)
#define TFA98XX_FLAG_CALIBRATION_CTL (1 << 5)
#define TFA98XX_FLAG_REMOVE_PLOP_NOISE (1 << 6)
#define TFA98XX_FLAG_LP_MODES (1 << 7)
#define TFA98XX_FLAG_TDM_DEVICE (1 << 8)
#define TFA98XX_NUM_RATES 9
/* DSP init status */
enum tfa98xx_dsp_init_state {
TFA98XX_DSP_INIT_STOPPED, /* DSP not running */
TFA98XX_DSP_INIT_RECOVER, /* DSP error detected at runtime */
TFA98XX_DSP_INIT_FAIL, /* DSP init failed */
TFA98XX_DSP_INIT_PENDING, /* DSP start requested */
TFA98XX_DSP_INIT_DONE, /* DSP running */
TFA98XX_DSP_INIT_INVALIDATED, /* DSP was running, requires re-init */
};
enum tfa98xx_dsp_fw_state {
TFA98XX_DSP_FW_NONE = 0,
TFA98XX_DSP_FW_PENDING,
TFA98XX_DSP_FW_FAIL,
TFA98XX_DSP_FW_OK,
};
enum tfa98xx_misc_device_id {
MISC_DEVICE_TFA98XX_REG,
MISC_DEVICE_TFA98XX_RW,
MISC_DEVICE_TFA98XX_RPC,
MISC_DEVICE_TFA98XX_PROFILE,
MISC_DEVICE_TFA98XX_IOCTL,
MISC_DEVICE_MAX
};
struct tfa98xx_miscdevice_info {
char devicename[255];
struct file_operations operations;
};
enum TFA_DEVICE_TYPE {
TFA_DEVICE_TYPE_9894,
TFA_DEVICE_TYPE_9874_PRIMARY,
TFA_DEVICE_TYPE_9874_SECONDARY,
TFA_DEVICE_TYPE_MAX
};
enum TFA_DEVICE_MUTE {
TFA98XX_DEVICE_MUTE_OFF = 0,
TFA98XX_DEVICE_MUTE_ON,
};
enum {
IOCTL_CMD_GET_MEMTRACK_DATA = 0,
IOCTL_CMD_GET_CNT_VERSION,
};
enum {
MEMTRACK_ITEM_SPEAKER_F0 = 0,
MEMTRACK_ITEM_SPEAKER_TEMPERATURE,
MEMTRACK_ITEM_SPEAKER_IMPEDANCE,
MEMTRACK_ITEM_MAX
};
struct livedata_cfg {
int address;
int track;
int scaler;
};
struct tfa98xx_firmware {
void *base;
struct tfa98xx_device *dev;
char name[9]; //TODO get length from tfa parameter defs
};
struct tfa98xx_baseprofile {
char basename[MAX_CONTROL_NAME]; /* profile basename */
int len; /* profile length */
int item_id; /* profile id */
int sr_rate_sup
[TFA98XX_NUM_RATES]; /* sample rates supported by this profile */
struct list_head list; /* list of all profiles */
};
struct tfa98xx {
struct regmap *regmap;
struct i2c_client *i2c;
struct regulator *vdd;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0)
struct snd_soc_component *component;
#else
struct snd_soc_codec *codec;
#endif
struct workqueue_struct *tfa98xx_wq;
struct delayed_work init_work;
struct delayed_work monitor_work;
struct delayed_work interrupt_work;
struct delayed_work tapdet_work;
struct mutex dsp_lock;
int dsp_init;
int dsp_fw_state;
int sysclk;
int rst_gpio;
u16 rev;
int audio_mode;
struct tfa98xx_firmware fw;
char *fw_name;
int rate;
/*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/
u8 pcm_format;
/*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/
wait_queue_head_t wq;
struct device *dev;
unsigned int init_count;
int pstream;
int cstream;
struct input_dev *input;
bool tapdet_enabled; /* service enabled */
bool tapdet_open; /* device file opened */
unsigned int tapdet_profiles; /* tapdet profile bitfield */
bool tapdet_poll; /* tapdet running on polling mode */
unsigned int rate_constraint_list[TFA98XX_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
int reset_gpio;
int power_gpio;
int irq_gpio;
struct list_head list;
struct tfa_device *tfa;
int vstep;
int profile;
int prof_vsteps
[TFACONT_MAXPROFS]; /* store vstep per profile (single device) */
#ifdef CONFIG_DEBUG_FS
struct dentry *dbg_dir;
#endif
u8 reg;
unsigned int flags;
bool set_mtp_cal;
uint16_t cal_data;
enum TFA_DEVICE_MUTE tfa_mute_mode;
struct device_node *spk_id_gpio_p;
struct miscdevice tfa98xx_reg;
struct miscdevice tfa98xx_rw;
struct miscdevice tfa98xx_rpc;
struct miscdevice tfa98xx_profile;
struct miscdevice tfa98xx_control;
};
#endif /* __TFA98XX_INC__ */

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/*
* Copyright 2013-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* tfa98xx_parameters.h
*
* Created on: Jul 22, 2013
* Author: NLV02095
*/
#ifndef TFA98XXPARAMETERS_H_
#define TFA98XXPARAMETERS_H_
//#include "config.h"
// workaround for Visual Studio:
// fatal error C1083: Cannot open include file: 'config.h': No such file or directory
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#include "tfa_service.h"
#if (defined(WIN32) || defined(_X64))
/* These warnings are disabled because it is only given by Windows and there is no easy fix */
#pragma warning(disable : 4200)
#pragma warning(disable : 4214)
#endif
/*
* profiles & volumesteps
*
*/
#define TFA_MAX_PROFILES (64)
#define TFA_MAX_VSTEPS (64)
#define TFA_MAX_VSTEP_MSG_MARKER \
(100) /* This marker is used to indicate if all msgs need to be written to the device */
#define TFA_MAX_MSGS (10)
// the pack pragma is required to make that the size in memory
// matches the actual variable lenghts
// This is to assure that the binary files can be transported between
// different platforms.
#pragma pack(push, 1)
/*
* typedef for 24 bit value using 3 bytes
*/
typedef struct uint24 {
uint8_t b[3];
} uint24_t;
/*
* the generic header
* all char types are in ASCII
*/
typedef struct nxpTfaHeader {
uint16_t id;
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint16_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
char customer[8]; // “name of customer”
char application[8]; // “application name”
char type[8]; // “application type name”
} nxpTfaHeader_t;
typedef enum nxpTfaSamplerate {
fs_8k, // 8kHz
fs_11k025, // 11.025kHz
fs_12k, // 12kHz
fs_16k, // 16kHz
fs_22k05, // 22.05kHz
fs_24k, // 24kHz
fs_32k, // 32kHz
fs_44k1, // 44.1kHz
fs_48k, // 48kHz
fs_96k, // 96kHz
fs_count // Should always be last item.
} nxpTfaSamplerate_t;
// Keep in sync with nxpTfaSamplerate_t !
static const int nxpTfaSamplerateHz[fs_count] = { 8000, 11025, 12000, 16000,
22050, 24000, 32000, 44100,
48000, 96000 };
/*
* coolflux direct memory access
*/
typedef struct nxpTfaDspMem {
uint8_t type; /* 0--3: p, x, y, iomem */
uint16_t address; /* target address */
uint8_t size; /* data size in words */
int words[]; /* payload in signed 32bit integer (two's complement) */
} nxpTfaDspMem_t;
/*
* the biquad coefficients for the API together with index in filter
* the biquad_index is the actual index in the equalizer +1
*/
#define BIQUAD_COEFF_SIZE 6
/*
* Output fixed point coeffs structure
*/
typedef struct {
int a2;
int a1;
int b2;
int b1;
int b0;
} nxpTfaBiquad_t;
typedef struct nxpTfaBiquadOld {
uint8_t bytes[BIQUAD_COEFF_SIZE * sizeof(uint24_t)];
} nxpTfaBiquadOld_t;
typedef struct nxpTfaBiquadFloat {
float headroom;
float b0;
float b1;
float b2;
float a1;
float a2;
} nxpTfaBiquadFloat_t;
/*
* EQ filter definitions
* Note: This is not in line with smartstudio (JV: 12/12/2016)
*/
typedef enum nxpTfaFilterType {
fCustom, //User defined biquad coefficients
fFlat, //Vary only gain
fLowpass, //2nd order Butterworth low pass
fHighpass, //2nd order Butterworth high pass
fLowshelf,
fHighshelf,
fNotch,
fPeak,
fBandpass,
f1stLP,
f1stHP,
fElliptic
} nxpTfaFilterType_t;
/*
* filter parameters for biquad (re-)calculation
*/
typedef struct nxpTfaFilter {
nxpTfaBiquadOld_t biquad;
uint8_t enabled;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float frequency;
float Q;
float gain;
} nxpTfaFilter_t; //8 * float + int32 + byte == 37
/*
* biquad params for calculation
*/
#define TFA_BQ_EQ_INDEX 0
#define TFA_BQ_ANTI_ALIAS_INDEX 10
#define TFA_BQ_INTEGRATOR_INDEX 13
/*
* Loudspeaker Compensation filter definitions
*/
typedef struct nxpTfaLsCompensationFilter {
nxpTfaBiquad_t biquad;
uint8_t lsCompOn; // Loudspeaker compensation on/off; when 'off', the DSP code doesn't apply the bwExt => bwExtOn GUI flag should be gray to avoid confusion
uint8_t bwExtOn; // Bandwidth extension on/off
float fRes; // [Hz] speaker resonance frequency
float Qt; // Speaker resonance Q-factor
float fBwExt; // [Hz] Band width extension frequency
float samplingFreq; // [Hz] Sampling frequency
} nxpTfaLsCompensationFilter_t;
/*
* Anti Aliasing Elliptic filter definitions
*/
typedef struct nxpTfaAntiAliasFilter {
nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */
uint8_t enabled;
float cutOffFreq; // cut off frequency
float samplingFreq; // sampling frequency
float rippleDb; // range: [0.1 3.0]
float rolloff; // range: [-1.0 1.0]
} nxpTfaAntiAliasFilter_t;
/**
* Integrator filter input definitions
*/
typedef struct nxpTfaIntegratorFilter {
nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */
uint8_t type; /**< Butterworth filter type: high or low pass */
float cutOffFreq; /**< cut off frequency in Hertz; range: [100.0 4000.0] */
float samplingFreq; /**< sampling frequency in Hertz */
float leakage; /**< leakage factor; range [0.0 1.0] */
} nxpTfaIntegratorFilter_t;
typedef struct nxpTfaEqFilter {
nxpTfaBiquad_t biquad;
uint8_t enabled;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
float samplingFreq; // sampling frequency
float Q; // range: [0.5 5.0]
float gainDb; // range: [-10.0 10.0]
} nxpTfaEqFilter_t; //8 * float + int32 + byte == 37
typedef struct nxpTfaContAntiAlias {
int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
uint8_t type;
float cutOffFreq; // cut off frequency
float samplingFreq;
float rippleDb; // integrator leakage
float rolloff;
uint8_t bytes[5 * 3]; // payload 5*24buts coeffs
} nxpTfaContAntiAlias_t;
typedef struct nxpTfaContIntegrator {
int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
uint8_t type;
float cutOffFreq; // cut off frequency
float samplingFreq;
float leakage; // integrator leakage
float reserved;
uint8_t bytes[5 * 3]; // payload 5*24buts coeffs
} nxpTfaContIntegrator_t;
typedef struct nxpTfaContEq {
int8_t index;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
float samplingFreq; // sampling frequency
float Q; // range: [0.5 5.0]
float gainDb; // range: [-10.0 10.0]
uint8_t bytes[5 * 3]; // payload 5*24buts coeffs
} nxpTfaContEq_t; //8 * float + int32 + byte == 37
typedef union nxpTfaContBiquad {
nxpTfaContEq_t eq;
nxpTfaContAntiAlias_t aa;
nxpTfaContIntegrator_t in;
} nxpTfaContBiquad_t;
#define TFA_BQ_EQ_INDEX 0
#define TFA_BQ_ANTI_ALIAS_INDEX 10
#define TFA_BQ_INTEGRATOR_INDEX 13
#define TFA98XX_MAX_EQ 10
typedef struct nxpTfaEqualizer {
nxpTfaFilter_t filter[TFA98XX_MAX_EQ];
} nxpTfaEqualizer_t;
/*
* files
*/
#define HDR(c1, c2) (c2 << 8 | c1) // little endian
typedef enum nxpTfaHeaderType {
paramsHdr = HDR('P', 'M'), /* containter file */
volstepHdr = HDR('V', 'P'),
patchHdr = HDR('P', 'A'),
speakerHdr = HDR('S', 'P'),
presetHdr = HDR('P', 'R'),
configHdr = HDR('C', 'O'),
equalizerHdr = HDR('E', 'Q'),
drcHdr = HDR('D', 'R'),
msgHdr = HDR('M', 'G'), /* generic message */
infoHdr = HDR('I', 'N')
} nxpTfaHeaderType_t;
/*
* equalizer file
*/
#define NXPTFA_EQ_VERSION '1'
#define NXPTFA_EQ_SUBVERSION "00"
typedef struct nxpTfaEqualizerFile {
nxpTfaHeader_t hdr;
uint8_t samplerate; // ==enum samplerates, assure 8 bits
nxpTfaFilter_t
filter[TFA98XX_MAX_EQ]; // note: API index counts from 1..10
} nxpTfaEqualizerFile_t;
/*
* patch file
*/
#define NXPTFA_PA_VERSION '1'
#define NXPTFA_PA_SUBVERSION "00"
typedef struct nxpTfaPatchFile {
nxpTfaHeader_t hdr;
uint8_t data[];
} nxpTfaPatch_t;
/*
* generic message file
* - the payload of this file includes the opcode and is send straight to the DSP
*/
#define NXPTFA_MG_VERSION '3'
#define NXPTFA_MG_SUBVERSION "00"
typedef struct nxpTfaMsgFile {
nxpTfaHeader_t hdr;
uint8_t data[];
} nxpTfaMsgFile_t;
/*
* NOTE the tfa98xx API defines the enum Tfa98xx_config_type that defines
* the subtypes as decribes below.
* tfa98xx_dsp_config_parameter_type() can be used to get the
* supported type for the active device..
*/
/*
* config file V1 sub 1
*/
#define NXPTFA_CO_VERSION '1'
#define NXPTFA_CO3_VERSION '3'
#define NXPTFA_CO_SUBVERSION1 "01"
typedef struct nxpTfaConfigS1File {
nxpTfaHeader_t hdr;
uint8_t data[55 * 3];
} nxpTfaConfigS1_t;
/*
* config file V1 sub 2
*/
#define NXPTFA_CO_SUBVERSION2 "02"
typedef struct nxpTfaConfigS2File {
nxpTfaHeader_t hdr;
uint8_t data[67 * 3];
} nxpTfaConfigS2_t;
/*
* config file V1 sub 3
*/
#define NXPTFA_CO_SUBVERSION3 "03"
typedef struct nxpTfaConfigS3File {
nxpTfaHeader_t hdr;
uint8_t data[67 * 3];
} nxpTfaConfigS3_t;
/*
* config file V1.0
*/
#define NXPTFA_CO_SUBVERSION "00"
typedef struct nxpTfaConfigFile {
nxpTfaHeader_t hdr;
uint8_t data[];
} nxpTfaConfig_t;
/*
* preset file
*/
#define NXPTFA_PR_VERSION '1'
#define NXPTFA_PR_SUBVERSION "00"
typedef struct nxpTfaPresetFile {
nxpTfaHeader_t hdr;
uint8_t data[];
} nxpTfaPreset_t;
/*
* drc file
*/
#define NXPTFA_DR_VERSION '1'
#define NXPTFA_DR_SUBVERSION "00"
typedef struct nxpTfaDrcFile {
nxpTfaHeader_t hdr;
uint8_t data[];
} nxpTfaDrc_t;
/*
* drc file
* for tfa 2 there is also a xml-version
*/
#define NXPTFA_DR3_VERSION '3'
#define NXPTFA_DR3_SUBVERSION "00"
typedef struct nxpTfaDrcFile2 {
nxpTfaHeader_t hdr;
uint8_t version[3];
uint8_t data[];
} nxpTfaDrc2_t;
/*
* volume step structures
*/
// VP01
#define NXPTFA_VP1_VERSION '1'
#define NXPTFA_VP1_SUBVERSION "01"
typedef struct nxpTfaVolumeStep1 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
} nxpTfaVolumeStep1_t;
// VP02
#define NXPTFA_VP2_VERSION '2'
#define NXPTFA_VP2_SUBVERSION "01"
typedef struct nxpTfaVolumeStep2 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
nxpTfaFilter_t
filter[TFA98XX_MAX_EQ]; // note: API index counts from 1..10
} nxpTfaVolumeStep2_t;
/*
* volumestep file
*/
#define NXPTFA_VP_VERSION '1'
#define NXPTFA_VP_SUBVERSION "00"
typedef struct nxpTfaVolumeStepFile {
nxpTfaHeader_t hdr;
uint8_t vsteps; // can also be calulated from size+type
uint8_t samplerate; // ==enum samplerates, assure 8 bits
uint8_t payload; //start of variable length contents:N times volsteps
} nxpTfaVolumeStepFile_t;
/*
* volumestep2 file
*/
typedef struct nxpTfaVolumeStep2File {
nxpTfaHeader_t hdr;
uint8_t vsteps; // can also be calulated from size+type
uint8_t samplerate; // ==enum samplerates, assure 8 bits
nxpTfaVolumeStep2_t
vstep[]; //start of variable length contents:N times volsteps
} nxpTfaVolumeStep2File_t;
/*
* volumestepMax2 file
*/
typedef struct nxpTfaVolumeStepMax2File {
nxpTfaHeader_t hdr;
uint8_t version[3];
uint8_t NrOfVsteps;
uint8_t vstepsBin[];
} nxpTfaVolumeStepMax2File_t;
/*
* volumestepMax2 file
* This volumestep should ONLY be used for the use of bin2hdr!
* This can only be used to find the messagetype of the vstep (without header)
*/
typedef struct nxpTfaVolumeStepMax2_1File {
uint8_t version[3];
uint8_t NrOfVsteps;
uint8_t vstepsBin[];
} nxpTfaVolumeStepMax2_1File_t;
struct nxpTfaVolumeStepRegisterInfo {
uint8_t NrOfRegisters;
uint16_t registerInfo[];
};
struct nxpTfaVolumeStepMessageInfo {
uint8_t NrOfMessages;
uint8_t MessageType;
uint24_t MessageLength;
uint8_t CmdId[3];
uint8_t ParameterData[];
};
/**************************old v2 *************************************************/
/*
* subv 00 volumestep file
*/
typedef struct nxpTfaOldHeader {
uint16_t id;
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint16_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
} nxpTfaOldHeader_t;
typedef struct nxpOldTfaFilter {
double bq[5];
int32_t type;
double frequency;
double Q;
double gain;
uint8_t enabled;
} nxpTfaOldFilter_t;
typedef struct nxpTfaOldVolumeStep2 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
nxpTfaOldFilter_t eq[10];
} nxpTfaOldVolumeStep2_t;
typedef struct nxpTfaOldVolumeStepFile {
nxpTfaOldHeader_t hdr;
nxpTfaOldVolumeStep2_t step[];
} nxpTfaOldVolumeStep2File_t;
/**************************end old v2 *************************************************/
/*
* speaker file header
*/
struct nxpTfaSpkHeader {
struct nxpTfaHeader hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint16_t ohm;
};
/*
* speaker file
*/
#define NXPTFA_SP_VERSION '1'
#define NXPTFA_SP_SUBVERSION "00"
typedef struct nxpTfaSpeakerFile {
nxpTfaHeader_t hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint8_t ohm_primary;
uint8_t ohm_secondary;
uint8_t data[]; //payload TFA98XX_SPEAKERPARAMETER_LENGTH
} nxpTfaSpeakerFile_t;
#define NXPTFA_VP3_VERSION '3'
#define NXPTFA_VP3_SUBVERSION "00"
struct nxpTfaFWVer {
uint8_t Major;
uint8_t minor;
uint8_t minor_update : 6;
uint8_t Update : 2;
};
struct nxpTfaFWMsg {
struct nxpTfaFWVer fwVersion;
struct nxpTfaMsg payload;
};
typedef struct nxpTfaLiveData {
char name[25];
char addrs[25];
int tracker;
int scalefactor;
} nxpTfaLiveData_t;
#define NXPTFA_SP3_VERSION '3'
#define NXPTFA_SP3_SUBVERSION "00"
struct nxpTfaSpeakerFileMax2 {
nxpTfaHeader_t hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint8_t ohm_primary;
uint8_t ohm_secondary;
struct nxpTfaFWMsg FWmsg; //payload including FW ver and Cmd ID
};
/*
* parameter container file
*/
/*
* descriptors
* Note 1: append new DescriptorType at the end
* Note 2: add new descriptors to dsc_name[] in tfaContUtil.c
*/
typedef enum nxpTfaDescriptorType {
dscDevice, // device list
dscProfile, // profile list
dscRegister, // register patch
dscString, // ascii, zero terminated string
dscFile, // filename + file contents
dscPatch, // patch file
dscMarker, // marker to indicate end of a list
dscMode,
dscSetInputSelect,
dscSetOutputSelect,
dscSetProgramConfig,
dscSetLagW,
dscSetGains,
dscSetvBatFactors,
dscSetSensesCal,
dscSetSensesDelay,
dscBitfield,
dscDefault, // used to reset bitfields to there default values
dscLiveData,
dscLiveDataString,
dscGroup,
dscCmd,
dscSetMBDrc,
dscFilter,
dscNoInit,
dscFeatures,
dscCfMem, // coolflux memory x,y,io
dscSetFwkUseCase,
dscSetVddpConfig,
dsc_last // trailer
} nxpTfaDescriptorType_t;
#define TFA_BITFIELDDSCMSK 0x7fffffff
typedef struct nxpTfaDescPtr {
uint32_t offset : 24;
uint32_t type : 8; // (== enum nxpTfaDescriptorType, assure 8bits length)
} nxpTfaDescPtr_t;
/*
* generic file descriptor
*/
typedef struct nxpTfaFileDsc {
nxpTfaDescPtr_t name;
uint32_t size; // file data length in bytes
uint8_t data[]; //payload
} nxpTfaFileDsc_t;
/*
* device descriptor list
*/
typedef struct nxpTfaDeviceList {
uint8_t length; // nr of items in the list
uint8_t bus; // bus
uint8_t dev; // device
uint8_t func; // subfunction or subdevice
uint32_t devid; // device hw fw id
nxpTfaDescPtr_t name; // device name
nxpTfaDescPtr_t list[]; // items list
} nxpTfaDeviceList_t;
/*
* profile descriptor list
*/
typedef struct nxpTfaProfileList {
uint32_t length : 8; // nr of items in the list + name
uint32_t group : 8; // profile group number
uint32_t ID : 16; // profile ID
nxpTfaDescPtr_t name; // profile name
nxpTfaDescPtr_t list[]; // items list (lenght-1 items)
} nxpTfaProfileList_t;
#define TFA_PROFID 0x1234
/*
* livedata descriptor list
*/
typedef struct nxpTfaLiveDataList {
uint32_t length : 8; // nr of items in the list
uint32_t ID : 24; // profile ID
nxpTfaDescPtr_t name; // livedata name
nxpTfaDescPtr_t list[]; // items list
} nxpTfaLiveDataList_t;
#define TFA_LIVEDATAID 0x5678
/*
* Bitfield descriptor
*/
typedef struct nxpTfaBitfield {
uint16_t value;
uint16_t field; // ==datasheet defined, 16 bits
} nxpTfaBitfield_t;
/*
* Bitfield enumuration bits descriptor
*/
typedef struct nxpTfaBfEnum {
unsigned int len : 4; // this is the actual length-1
unsigned int pos : 4;
unsigned int address : 8;
} nxpTfaBfEnum_t;
/*
* Register patch descriptor
*/
typedef struct nxpTfaRegpatch {
uint8_t address; // register address
uint16_t value; // value to write
uint16_t mask; // mask of bits to write
} nxpTfaRegpatch_t;
/*
* Mode descriptor
*/
typedef struct nxpTfaUseCase {
int value; // mode value, maps to enum Tfa98xx_Mode
} nxpTfaMode_t;
/*
* NoInit descriptor
*/
typedef struct nxpTfaNoInit {
uint8_t value; // noInit value
} nxpTfaNoInit_t;
/*
* Features descriptor
*/
typedef struct nxpTfaFeatures {
uint16_t value[3]; // features value
} nxpTfaFeatures_t;
/*
* the container file
* - the size field is 32bits long (generic=16)
* - all char types are in ASCII
*/
#define NXPTFA_PM_VERSION '1'
#define NXPTFA_PM3_VERSION '3'
#define NXPTFA_PM_SUBVERSION '1'
typedef struct nxpTfaContainer {
char id[2]; // "XX" : XX=type
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint32_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
uint16_t rev; // "extra chars for rev nr"
char customer[8]; // “name of customer”
char application[8]; // “application name”
char type[8]; // “application type name”
uint16_t ndev; // "nr of device lists"
uint16_t nprof; // "nr of profile lists"
uint16_t nliveData; // "nr of livedata lists"
nxpTfaDescPtr_t index[]; // start of item index table
} nxpTfaContainer_t;
#pragma pack(pop)
#endif /* TFA98XXPARAMETERS_H_ */

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
typedef struct TfaBfName {
unsigned short bfEnum;
char *bfName;
} tfaBfName_t;
typedef struct TfaIrqName {
unsigned short irqEnum;
char *irqName;
} tfaIrqName_t;
#include "tfa1_tfafieldnames.h"
#include "tfa2_tfafieldnames_N1C.h"
/* diffs for specific devices */
#include "tfa9887_tfafieldnames.h"
#include "tfa9890_tfafieldnames.h"
#include "tfa9891_tfafieldnames.h"
#include "tfa9872_tfafieldnames.h"
#include "tfa9912_tfafieldnames.h"
#include "tfa9896_tfafieldnames.h"
#include "tfa9874_tfafieldnames.h"
#include "tfa9894_tfafieldnames.h"
/* missing 'common' defs break the build but unused in TFA1 context */
#define TFA1_BF_AMPINSEL -1
#define TFA1_BF_MANSCONF -1
#define TFA1_BF_MANCOLD -1
#define TFA1_BF_INTSMUTE -1
#define TFA1_BF_CFSMR -1
#define TFA1_BF_CFSML -1
#define TFA1_BF_DCMCCAPI -1
#define TFA1_BF_DCMCCSB -1
#define TFA1_BF_USERDEF -1
#define TFA1_BF_MANSTATE -1
#define TFA1_BF_MANOPER -1
#define TFA1_BF_REFCKSEL -1
#define TFA1_BF_VOLSEC -1
#define TFA1_BF_FRACTDEL -1
#define TFA1_BF_ACKDMG -1
#define TFA1_BF_SSRIGHTE -1
#define TFA1_BF_SSLEFTE -1
#define TFA1_BF_R25CL -1
#define TFA1_BF_R25CR -1
#define TFA1_BF_SWPROFIL 0x8045 /*!< profile save */
#define TFA1_BF_SWVSTEP 0x80a5 /*!< vstep save */
#define TFA1_BF_TDMNBCK -1
#define TFA1_BF_TDMSSIZE -1
/* missing 'common' defs break the build */
#define TFA2_BF_CFSM -1
/* MTP access uses registers
* defs are derived from corresponding bitfield names as used in the BF macros
*/
#define MTPKEY2 MTPK /* unlock key2 MTPK */
#define MTP0 MTPOTC /* MTP data */
#define MTP_CONTROL CIMTP /* copy i2c to mtp */
/* interrupt enable register uses HW name in TFA2 */
#define TFA2_BF_INTENVDDS TFA2_BF_IEVDDS
/* TFA9891 specific bit field names */
#define TFA1_BF_SAAMGAIN 0x2202
#define TFA2_BF_SAAMGAIN -1
/* TFA9872 specific bit field names */
#define TFA2_BF_IELP0 TFA9872_BF_IELP0
#define TFA2_BF_ISTLP0 TFA9872_BF_ISTLP0
#define TFA2_BF_IPOLP0 TFA9872_BF_IPOLP0
#define TFA2_BF_IELP1 TFA9872_BF_IELP1
#define TFA2_BF_ISTLP1 TFA9872_BF_ISTLP1
#define TFA2_BF_IPOLP1 TFA9872_BF_IPOLP1
#define TFA2_BF_LP0 TFA9872_BF_LP0
#define TFA2_BF_LP1 TFA9872_BF_LP1
#define TFA2_BF_R25C TFA9872_BF_R25C
#define TFA2_BF_SAMMODE TFA9872_BF_SAMMODE
/* interrupt bit field names of TFA2 and TFA1 do not match */
#define TFA1_BF_IEACS TFA1_BF_INTENACS
#define TFA1_BF_IPOACS TFA1_BF_INTPOLACS
#define TFA1_BF_ISTACS TFA1_BF_INTOACS
#define TFA1_BF_ISTVDDS TFA1_BF_INTOVDDS
#define TFA1_BF_ICLVDDS TFA1_BF_INTIVDDS
#define TFA1_BF_IPOVDDS TFA1_BF_INTPOLVDDS
#define TFA1_BF_IENOCLK TFA1_BF_INTENNOCLK
#define TFA1_BF_ISTNOCLK TFA1_BF_INTONOCLK
#define TFA1_BF_IPONOCLK TFA1_BF_INTPOLNOCLK
/* interrupt bit fields not available on TFA1 */
#define TFA1_BF_IECLKOOR -1
#define TFA1_BF_ISTCLKOOR -1
#define TFA1_BF_IEMWSRC -1
#define TFA1_BF_ISTMWSRC -1
#define TFA1_BF_IPOMWSRC -1
#define TFA1_BF_IEMWSMU -1
#define TFA1_BF_ISTMWSMU -1
#define TFA1_BF_IPOMWSMU -1
#define TFA1_BF_IEMWCFC -1
#define TFA1_BF_ISTMWCFC -1
#define TFA1_BF_IPOMWCFC -1
#define TFA1_BF_CLKOOR -1
#define TFA1_BF_MANWAIT1 -1
#define TFA1_BF_MANWAIT2 -1
#define TFA1_BF_MANMUTE -1
#define TFA1_BF_IPCLKOOR -1
#define TFA1_BF_ICLCLKOOR -1
#define TFA1_BF_IPOSWS -1
#define TFA1_BF_IESWS -1
#define TFA1_BF_ISTSWS -1
#define TFA1_BF_IESPKS -1
#define TFA1_BF_ISTSPKS -1
#define TFA1_BF_IPOSPKS -1
#define TFA1_BF_IECLKS -1
#define TFA1_BF_ISTCLKS -1
#define TFA1_BF_IPOCLKS -1
#define TFA1_BF_IEAMPS -1
#define TFA1_BF_ISTAMPS -1
#define TFA1_BF_IPOAMPS -1
#define TFA1_BF_IELP0 -1
#define TFA1_BF_ISTLP0 -1
#define TFA1_BF_IPOLP0 -1
#define TFA1_BF_IELP1 -1
#define TFA1_BF_ISTLP1 -1
#define TFA1_BF_IPOLP1 -1
#define TFA1_BF_LP0 -1
#define TFA1_BF_LP1 -1
#define TFA1_BF_R25C -1
#define TFA1_BF_SAMMODE -1
/* TDM STATUS fields not available on TFA1 */
#define TFA1_BF_TDMLUTER -1
#define TFA1_BF_TDMERR -1

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/*
* Copyright 2013-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* tfaContainer.h
*
* Created on: Sep 11, 2013
* Author: wim
*/
#ifndef TFACONTAINER_H_
#define TFACONTAINER_H_
/* static limits */
#define TFACONT_MAXDEVS (4) /* maximum nr of devices */
#define TFACONT_MAXPROFS (16) /* maximum nr of profiles */
#include "tfa98xx_parameters.h"
/**
* Pass the container buffer, initialize and allocate internal memory.
*
* @param cnt pointer to the start of the buffer holding the container file
* @param length of the data in bytes
* @return
* - tfa_error_ok if normal
* - tfa_error_container invalid container data
* - tfa_error_bad_param invalid parameter
*
*/
enum tfa_error tfa_load_cnt(void *cnt, int length);
/**
* Return the descriptor string
* @param cnt pointer to the container struct
* @param dsc pointer to nxpTfa descriptor
* @return descriptor string
*/
char *tfaContGetString(nxpTfaContainer_t *cnt, nxpTfaDescPtr_t *dsc);
/**
* Gets the string for the given command type number
* @param type number representing a command
* @return string of a command
*/
char *tfaContGetCommandString(uint32_t type);
/**
* get the device type from the patch in this devicelist
* - find the patch file for this devidx
* - return the devid from the patch or 0 if not found
* @param cnt pointer to container file
* @param dev_idx device index
* @return descriptor string
*/
int tfa_cnt_get_devid(nxpTfaContainer_t *cnt, int dev_idx);
/**
* Get the slave for the device if it exists.
* @param tfa the device struct pointer
* @param slave_addr the index of the device
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr);
void tfaContSetSlave(uint8_t slave_addr);
/**
* Get the index for a skave address.
* @param tfa the device struct pointer
* @return the device index
*/
int tfa_cont_get_idx(struct tfa_device *tfa);
/**
* Write reg and bitfield items in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa);
/**
* Write reg and bitfield items in the profilelist to the target.
* @param tfa the device struct pointer
* @param prof_idx the profile index
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx);
/**
* Write a patchfile in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa);
/**
* Write all param files in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa);
/**
* Get sample rate from passed profile index
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @return sample rate value
*/
unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa,
unsigned int prof_idx);
/**
* Get the device name string
* @param cnt the pointer to the container struct
* @param dev_idx the index of the device
* @return device name string or error string if not found
*/
char *tfaContDeviceName(nxpTfaContainer_t *cnt, int dev_idx);
/**
* Get the application name from the container file application field
* @param tfa the device struct pointer
* @param name the input stringbuffer with size: sizeof(application field)+1
* @return actual string length
*/
int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name);
/**
* Get profile index of the calibration profile
* @param tfa the device struct pointer
* @return profile index, -2 if no calibration profile is found or -1 on error
*/
int tfaContGetCalProfile(struct tfa_device *tfa);
/**
* Is the profile a tap profile ?
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @return 1 if the profile is a tap profile or 0 if not
*/
int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx);
/**
* Get the name of the profile at certain index for a device in the container file
* @param cnt the pointer to the container struct
* @param dev_idx the index of the device
* @param prof_idx the index of the profile
* @return profile name string or error string if not found
*/
char *tfaContProfileName(nxpTfaContainer_t *cnt, int dev_idx, int prof_idx);
/**
* Process all items in the profilelist
* NOTE an error return during processing will leave the device muted
* @param tfa the device struct pointer
* @param prof_idx index of the profile
* @param vstep_idx index of the vstep
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx,
int vstep_idx);
/**
* Specify the speaker configurations (cmd id) (Left, right, both, none)
* @param dev_idx index of the device
* @param configuration name string of the configuration
*/
void tfa98xx_set_spkr_select(int dev_idx, char *configuration);
enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa,
nxpTfaFilter_t *filter);
/**
* Write all param files in the profilelist to the target
* this is used during startup when maybe ACS is set
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @param vstep_idx the index of the vstep
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx,
int vstep_idx);
enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx,
int vstep_idx);
enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size,
uint8_t data[]);
/**
* Get the device list dsc from the tfaContainer
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @return device list pointer
*/
nxpTfaDeviceList_t *tfaContGetDevList(nxpTfaContainer_t *cont, int dev_idx);
/**
* Get the Nth profile for the Nth device
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @param prof_idx the index of the profile
* @return profile list pointer
*/
nxpTfaProfileList_t *tfaContGetDevProfList(nxpTfaContainer_t *cont, int dev_idx,
int prof_idx);
/**
* Get the number of profiles for device from contaienr
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @return device list pointer
*/
int tfa_cnt_get_dev_nprof(struct tfa_device *tfa);
/**
* Get the Nth livedata for the Nth device
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @param livedata_idx the index of the livedata
* @return livedata list pointer
*/
nxpTfaLiveDataList_t *tfaContGetDevLiveDataList(nxpTfaContainer_t *cont,
int dev_idx, int livedata_idx);
/**
* Check CRC for container
* @param cont pointer to the tfaContainer
* @return error value 0 on error
*/
int tfaContCrcCheckContainer(nxpTfaContainer_t *cont);
/**
* Get the device list pointer
* @param cnt pointer to the container struct
* @param dev_idx the index of the device
* @return pointer to device list
*/
nxpTfaDeviceList_t *tfaContDevice(nxpTfaContainer_t *cnt, int dev_idx);
/**
* Return the pointer to the first profile in a list from the tfaContainer
* @param cont pointer to the tfaContainer
* @return pointer to first profile in profile list
*/
nxpTfaProfileList_t *tfaContGet1stProfList(nxpTfaContainer_t *cont);
/**
* Return the pointer to the next profile in a list
* @param prof is the pointer to the profile list
* @return profile list pointer
*/
nxpTfaProfileList_t *tfaContNextProfile(nxpTfaProfileList_t *prof);
/**
* Return the pointer to the first livedata in a list from the tfaContainer
* @param cont pointer to the tfaContainer
* @return pointer to first livedata in profile list
*/
nxpTfaLiveDataList_t *tfaContGet1stLiveDataList(nxpTfaContainer_t *cont);
/**
* Return the pointer to the next livedata in a list
* @param livedata_idx is the pointer to the livedata list
* @return livedata list pointer
*/
nxpTfaLiveDataList_t *tfaContNextLiveData(nxpTfaLiveDataList_t *livedata_idx);
/**
* Write a bit field
* @param tfa the device struct pointer
* @param bf bitfield to write
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa,
nxpTfaBitfield_t bf);
/**
* Write a parameter file to the device
* @param tfa the device struct pointer
* @param file filedescriptor pointer
* @param vstep_idx index to vstep
* @param vstep_msg_idx index to vstep message
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa,
nxpTfaFileDsc_t *file, int vstep_idx,
int vstep_msg_idx);
/**
* Get the max volume step associated with Nth profile for the Nth device
* @param tfa the device struct pointer
* @param prof_idx profile index
* @return the number of vsteps
*/
int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx);
/**
* Get the file contents associated with the device or profile
* Search within the device tree, if not found, search within the profile
* tree. There can only be one type of file within profile or device.
* @param tfa the device struct pointer
* @param prof_idx I2C profile index in the device
* @param type file type
* @return 0 NULL if file type is not found
* @return 1 file contents
*/
nxpTfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx,
enum nxpTfaHeaderType type);
/**
* Dump the contents of the file header
* @param hdr pointer to file header data
*/
void tfaContShowHeader(nxpTfaHeader_t *hdr);
/**
* Read a bit field
* @param tfa the device struct pointer
* @param bf bitfield to read out
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa,
nxpTfaBitfield_t *bf);
/**
* Get hw feature bits from container file
* @param tfa the device struct pointer
* @param hw_feature_register pointer to where hw features are stored
*/
void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register);
/**
* Get sw feature bits from container file
* @param tfa the device struct pointer
* @param sw_feature_register pointer to where sw features are stored
*/
void get_sw_features_from_cnt(struct tfa_device *tfa,
int sw_feature_register[2]);
/**
* Factory trimming for the Boost converter
* check if there is a correction needed
* @param tfa the device struct pointer
*/
enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa);
/**
* Search for filters settings and if found then write them to the device
* @param tfa the device struct pointer
* @param prof_idx profile to look in
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx);
/**
* Get the firmware version from the patch in the container file
* @param tfa the device struct pointer
* @return firmware version
*/
int tfa_cnt_get_patch_version(struct tfa_device *tfa);
int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length,
const char *buffer);
#endif /* TFACONTAINER_H_ */

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**\file
*
* The tfa_device interface controls a single I2C device instance by
* referencing to the device specific context provided by means of the
* tfa_device structure pointer.
* Multiple instances of tfa_device structures will be created and maintained
* by the caller.
*
* The API is functionally grouped as:
* - tfa_dev basic codec interface to probe, start/stop and control the device state
* - access to internal MTP storage
* - abstraction for interrupt bits and handling
* - container reading support
*/
#ifndef __TFA_DEVICE_H__
#define __TFA_DEVICE_H__
#include "config.h"
struct tfa_device;
/*
* hw/sw feature bit settings in MTP
*/
enum featureSupport {
supportNotSet, /**< default means not set yet */
supportNo, /**< no support */
supportYes /**< supported */
};
/*
* supported Digital Audio Interfaces bitmap
*/
enum Tfa98xx_DAI {
Tfa98xx_DAI_I2S = 0x01, /**< I2S only */
Tfa98xx_DAI_TDM = 0x02, /**< TDM, I2S */
Tfa98xx_DAI_PDM = 0x04, /**< PDM */
};
/*
* device ops function structure
*/
struct tfa_device_ops {
enum Tfa98xx_Error (*dsp_msg)(struct tfa_device *tfa, int length,
const char *buf);
enum Tfa98xx_Error (*dsp_msg_read)(struct tfa_device *tfa, int length,
unsigned char *bytes);
enum Tfa98xx_Error (*reg_read)(struct tfa_device *tfa,
unsigned char subaddress,
unsigned short *value);
enum Tfa98xx_Error (*reg_write)(struct tfa_device *tfa,
unsigned char subaddress,
unsigned short value);
enum Tfa98xx_Error (*mem_read)(struct tfa_device *tfa,
unsigned int start_offset, int num_words,
int *pValues);
enum Tfa98xx_Error (*mem_write)(struct tfa_device *tfa,
unsigned short address, int value,
int memtype);
enum Tfa98xx_Error (*tfa_init)(
struct tfa_device *
tfa); /**< init typically for loading optimal settings */
enum Tfa98xx_Error (*dsp_reset)(
struct tfa_device *tfa,
int state); /**< reset the coolflux dsp */
enum Tfa98xx_Error (*dsp_system_stable)(
struct tfa_device *tfa,
int *ready); /**< ready when clocks are stable to allow DSP subsystem access */
enum Tfa98xx_Error (*dsp_write_tables)(
struct tfa_device *tfa,
int sample_rate); /**< write the device/type specific delaytables */
enum Tfa98xx_Error (*auto_copy_mtp_to_iic)(
struct tfa_device *tfa); /**< Set auto_copy_mtp_to_iic */
enum Tfa98xx_Error (*factory_trimmer)(
struct tfa_device
*tfa); /**< Factory trimming for the Boost converter */
int (*set_swprof)(
struct tfa_device *tfa,
unsigned short
new_value); /**< Set the sw profile in the struct and the hw register */
int (*get_swprof)(
struct tfa_device
*tfa); /**< Get the sw profile from the hw register */
int (*set_swvstep)(
struct tfa_device *tfa,
unsigned short
new_value); /**< Set the sw vstep in the struct and the hw register */
int (*get_swvstep)(
struct tfa_device
*tfa); /**< Get the sw vstep from the hw register */
int (*get_mtpb)(
struct tfa_device *tfa); /**< get status of MTB busy bit*/
enum Tfa98xx_Error (*set_mute)(struct tfa_device *tfa,
int mute); /**< set mute */
enum Tfa98xx_Error (*faim_protect)(
struct tfa_device *tfa,
int state); /**< Protect FAIM from being corrupted */
enum Tfa98xx_Error (*set_osc_powerdown)(
struct tfa_device *tfa,
int state); /**< Allow to change internal osc. gating settings */
};
/**
* Device states and modifier flags to allow a device/type independent fine
* grained control of the internal state.\n
* Values below 0x10 are referred to as base states which can be or-ed with
* state modifiers, from 0x10 and higher.
*
*/
enum tfa_state {
TFA_STATE_UNKNOWN, /**< unknown or invalid */
TFA_STATE_POWERDOWN, /**< PLL in powerdown, Algo is up/warm */
TFA_STATE_INIT_HW, /**< load I2C/PLL hardware setting (~wait2srcsettings) */
TFA_STATE_INIT_CF, /**< coolflux HW access possible (~initcf) */
TFA_STATE_INIT_FW, /**< DSP framework active (~patch loaded) */
TFA_STATE_OPERATING, /**< Amp and Algo running */
TFA_STATE_FAULT, /**< An alarm or error occurred */
TFA_STATE_RESET, /**< I2C reset and ACS set */
/* --sticky state modifiers-- */
TFA_STATE_MUTE = 0x10, /**< Algo & Amp mute */
TFA_STATE_UNMUTE = 0x20, /**< Algo & Amp unmute */
TFA_STATE_CLOCK_ALWAYS =
0x40, /**< PLL connect to internal oscillator */
TFA_STATE_CLOCK_AUDIO =
0x80, /**< PLL connect to audio clock (BCK/FS) */
TFA_STATE_LOW_POWER = 0x100, /**< lowest possible power state */
};
/**
* This is the main tfa device context structure, it will carry all information
* that is needed to handle a single I2C device instance.
* All functions dealing with the device will need access to the fields herein.
*/
struct tfa_device {
int dev_idx; /**< device container index */
int in_use;
int buffer_size; /**< lowest level max buffer size */
int has_msg; /**< support direct dsp messaging */
unsigned char slave_address; /**< I2C slave address (not shifted) */
unsigned short rev; /**< full revid of this device */
unsigned char tfa_family; /**< tfa1/tfa2 */
enum featureSupport supportDrc;
enum featureSupport supportFramework;
enum featureSupport support_saam;
int sw_feature_bits[2]; /**< cached copy of sw feature bits */
int hw_feature_bits; /**< cached copy of hw feature bits */
int profile; /**< active profile */
int vstep; /**< active vstep */
unsigned char spkr_count;
unsigned char spkr_select;
unsigned char support_tcoef; /**< legacy tfa9887, will be removed */
enum Tfa98xx_DAI daimap; /**< supported audio interface types */
int mohm[3]; /**< speaker calibration values in milli ohms -1 is error */
struct tfa_device_ops dev_ops;
uint16_t interrupt_enable[3];
uint16_t interrupt_status[3];
int ext_dsp; /**< respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
int bus; /* TODO fix ext_dsp and bus handling */
int tfadsp_event; /**< enum tfadsp_event_en is for external registry */
int verbose; /**< verbosity level for debug print output */
enum tfa_state
state; /**< last known state or-ed with optional state_modifier */
struct nxpTfaContainer *cnt; /**< the loaded container file */
struct nxpTfaVolumeStepRegisterInfo
*p_regInfo; /**< remember vstep for partial updates */
int partial_enable; /**< enable partial updates */
void *data; /**< typically pointing to Linux driver structure owning this device */
int convert_dsp32; /**< convert 24 bit DSP messages to 32 bit */
int sync_iv_delay; /**< synchronize I/V delay at cold start */
int is_probus_device; /**< probus device: device without internal DSP */
int needs_reset; /**< add the reset trigger for SetAlgoParams and SetMBDrc commands */
struct kmem_cache *cachep; /**< Memory allocator handle */
};
/**
* The tfa_dev_probe is called before accessing any device accessing functions.
* Access to the tfa device register 3 is attempted and will record the
* returned id for further use. If no device responds the function will abort.
* The recorded id will by used by the query functions to fill the remaining
* relevant data fields of the device structure.
* Data such as MTP features that requires device access will only be read when
* explicitly called and the result will be then cached in the struct.
*
* A structure pointer passed to this device needs to refer to existing memory
* space allocated by the caller.
*
* @param slave = I2C slave address of the target device (not shifted)
* @param tfa struct = points to memory that holds the context for this device
* instance
*
* @return
* - 0 if the I2C device responded to a read of register address 3\n
* when the device responds but with an unknown id a warning will be printed
* - -1 if no response from the I2C device
*
*/
int tfa_dev_probe(int slave, struct tfa_device *tfa);
/**
* Start this instance at the profile and vstep as provided.
* The profile and vstep will be loaded first in case the current value differs
* from the requested values.
* Note that this call will not change the mute state of the tfa, which means
* that of this instance was called in muted state the caller will have to
* unmute in order to get audio.
*
* @param tfa struct = pointer to context of this device instance
* @param profile the selected profile to run
* @param vstep the selected vstep to use
* @return tfa_error enum
*/
/*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/
#ifdef __KERNEL__
enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile,
int vstep, u8 pcm_format);
#else
enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile,
int vstep);
#endif
/*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/
/**
* Stop audio for this instance as gracefully as possible.
* Audio will be muted and the PLL will be shutdown together with any other
* device/type specific settings needed to prevent audio artifacts or
* workarounds.
*
* Note that this call will change state of the tfa to mute and powered down.
*
* @param tfa struct = pointer to context of this device instance
* @return tfa_error enum
*/
enum tfa_error tfa_dev_stop(struct tfa_device *tfa);
/**
* This interface allows a device/type independent fine grained control of the
* internal state of the instance.
* Whenever a base state is requested an attempt is made to actively bring the device
* into this state. However this may depend on external conditions beyond control of
* this software layer. Therefore in case the state cannot be set an erro will
* be returned and the current state remains unchanged.
* The base states, lower values below 0x10, are all mutually exclusive, they higher ones
* can also function as a sticky modifier which means for example that operating
* state could be in either muted or unmuted state. Or in case of init_cf it can be
* internal clock (always) or external audio clock.
* This function is intended to be used for device mute/unmute synchronization
* when called from higher layers. Mostly internal calls will use this to control
* the startup and profile transitions in a device/type independent way.
*
* @param tfa struct = pointer to context of this device instance
* @param state struct = desired device state after function return
* @return tfa_error enum
*/
enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state,
int is_calibration);
/**
* Retrieve the current state of this instance in an active way.
* The state field in tfa structure will reflect the result unless an error is
* returned.
* Note that the hardware state may change on external events an as such this
* field should be treated as volatile.
*
* @param tfa struct = pointer to context of this device instance
* @return tfa_error enum
*
*/
enum tfa_state tfa_dev_get_state(struct tfa_device *tfa);
/*****************************************************************************/
/*****************************************************************************/
/**
* MTP support functions
*/
enum tfa_mtp {
TFA_MTP_OTC, /**< */
TFA_MTP_EX, /**< */
TFA_MTP_RE25, /**< */
TFA_MTP_RE25_PRIM, /**< */
TFA_MTP_RE25_SEC, /**< */
TFA_MTP_LOCK, /**< */
};
/**
*
*/
int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item);
/**
*
*/
enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item,
int value);
//irq
/* tfa2 interrupt support
* !!! enum tfa9912_irq !!!*/
/*
* interrupt bit function to clear
*/
int tfa_irq_clear(struct tfa_device *tfa, int bit);
/*
* return state of irq or -1 if illegal bit
*/
int tfa_irq_get(struct tfa_device *tfa, int bit);
/*
* interrupt bit function that operates on the shadow regs in the handle
*/
int tfa_irq_ena(struct tfa_device *tfa, int bit, int state);
/*
* interrupt bit function that sets the polarity
*/
int tfa_irq_set_pol(struct tfa_device *tfa, int bit, int state);
/*
* mask interrupts by disabling them
*/
int tfa_irq_mask(struct tfa_device *tfa);
/*
* unmask interrupts by enabling them again
*/
int tfa_irq_unmask(struct tfa_device *tfa);
//cnt read
//debug?
#endif /* __TFA_DEVICE_H__ */

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TFA98XX_INTERNALS_H
#define TFA98XX_INTERNALS_H
#include "config.h"
#include "tfa_service.h" //TODO cleanup for enum Tfa98xx_Status_ID
/*
* tfadsp_fw_api.c
*/
/**
* Return a text version of the firmware status ID code
* @param status the given status ID code
* @return the firmware status ID string
*/
const char *tfadsp_fw_status_string(enum Tfa98xx_Status_ID status);
int tfadsp_fw_start(struct tfa_device *tfa, int prof_idx, int vstep_idx);
int tfadsp_fw_get_api_version(struct tfa_device *tfa, uint8_t *buffer);
#define FW_MAXTAG 150
int tfadsp_fw_get_tag(struct tfa_device *tfa, uint8_t *buffer);
int tfadsp_fw_get_status_change(struct tfa_device *tfa, uint8_t *buffer);
int tfadsp_fw_set_re25(struct tfa_device *tfa, int prim, int sec);
int tfadsp_fw_get_re25(struct tfa_device *tfa, uint8_t *buffer);
/*
* the order matches the ACK bits order in TFA98XX_CF_STATUS
*/
enum tfa_fw_event { /* not all available on each device */
tfa_fw_i2c_cmd_ack,
tfa_fw_reset_start,
tfa_fw_short_on_mips,
tfa_fw_soft_mute_ready,
tfa_fw_volume_ready,
tfa_fw_error_damage,
tfa_fw_calibrate_done,
tfa_fw_max
};
/* the following type mappings are compiler specific */
#define subaddress_t unsigned char
/* module Ids */
#define MODULE_FRAMEWORK 0
#define MODULE_SPEAKERBOOST 1
#define MODULE_BIQUADFILTERBANK 2
#define MODULE_TAPTRIGGER 5
#define MODULE_SETRE 9
/* RPC commands */
/* SET */
#define FW_PAR_ID_SET_MEMORY 0x03
#define FW_PAR_ID_SET_SENSES_DELAY 0x04
#define FW_PAR_ID_SETSENSESCAL 0x05
#define FW_PAR_ID_SET_INPUT_SELECTOR 0x06
#define FW_PAR_ID_SET_OUTPUT_SELECTOR 0x08
#define FW_PAR_ID_SET_PROGRAM_CONFIG 0x09
#define FW_PAR_ID_SET_GAINS 0x0A
#define FW_PAR_ID_SET_MEMTRACK 0x0B
#define FW_PAR_ID_SET_FWKUSECASE 0x11
#define TFA1_FW_PAR_ID_SET_CURRENT_DELAY 0x03
#define TFA1_FW_PAR_ID_SET_CURFRAC_DELAY 0x06
/* GET */
#define FW_PAR_ID_GET_MEMORY 0x83
#define FW_PAR_ID_GLOBAL_GET_INFO 0x84
#define FW_PAR_ID_GET_FEATURE_INFO 0x85
#define FW_PAR_ID_GET_MEMTRACK 0x8B
#define FW_PAR_ID_GET_TAG 0xFF
#define FW_PAR_ID_GET_API_VERSION 0xFE
#define FW_PAR_ID_GET_STATUS_CHANGE 0x8D
/* Load a full model into SpeakerBoost. */
/* SET */
#define SB_PARAM_SET_ALGO_PARAMS 0x00
#define SB_PARAM_SET_LAGW 0x01
#define SB_PARAM_SET_ALGO_PARAMS_WITHOUT_RESET 0x02
#define SB_PARAM_SET_RE25C 0x05
#define SB_PARAM_SET_LSMODEL 0x06
#define SB_PARAM_SET_MBDRC 0x07
#define SB_PARAM_SET_MBDRC_WITHOUT_RESET 0x08
#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A
#define SB_PARAM_SET_DRC 0x0F
/* GET */
#define SB_PARAM_GET_ALGO_PARAMS 0x80
#define SB_PARAM_GET_LAGW 0x81
#define SB_PARAM_GET_RE25C 0x85
#define SB_PARAM_GET_LSMODEL 0x86
#define SB_PARAM_GET_MBDRC 0x87
#define SB_PARAM_GET_MBDRC_DYNAMICS 0x89
#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A
#define SB_PARAM_GET_TAG 0xFF
#define SB_PARAM_SET_EQ 0x0A /* 2 Equaliser Filters. */
#define SB_PARAM_SET_PRESET 0x0D /* Load a preset */
#define SB_PARAM_SET_CONFIG 0x0E /* Load a config */
#define SB_PARAM_SET_AGCINS 0x10
#define SB_PARAM_SET_CURRENT_DELAY 0x03
#define SB_PARAM_GET_STATE 0xC0
#define SB_PARAM_GET_XMODEL 0xC1 /* Gets current Excursion Model. */
#define SB_PARAM_GET_XMODEL_COEFFS 0x8C /* Get coefficients for XModel */
#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A /* Get excursion filters */
#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A /* Set excursion filters */
/* SET: TAPTRIGGER */
#define TAP_PARAM_SET_ALGO_PARAMS 0x01
#define TAP_PARAM_SET_DECIMATION_PARAMS 0x02
/* GET: TAPTRIGGER*/
#define TAP_PARAM_GET_ALGO_PARAMS 0x81
#define TAP_PARAM_GET_TAP_RESULTS 0x84
/* sets the speaker calibration impedance (@25 degrees celsius) */
#define SB_PARAM_SET_RE0 0x89
#define BFB_PAR_ID_SET_COEFS 0x00
#define BFB_PAR_ID_GET_COEFS 0x80
#define BFB_PAR_ID_GET_CONFIG 0x81
/* for compatibility */
#define FW_PARAM_GET_STATE FW_PAR_ID_GLOBAL_GET_INFO
#define FW_PARAM_GET_FEATURE_BITS FW_PAR_ID_GET_FEATURE_BITS
/* RPC Status results */
#define STATUS_OK 0
#define STATUS_INVALID_MODULE_ID 2
#define STATUS_INVALID_PARAM_ID 3
#define STATUS_INVALID_INFO_ID 4
/* the maximum message length in the communication with the DSP */
#define TFA2_MAX_PARAM_SIZE (507 * 3) /* TFA2 */
#define TFA1_MAX_PARAM_SIZE (145 * 3) /* TFA1 */
#define ROUND_DOWN(a, n) (((a) / (n)) * (n))
/* feature bits */
#define FEATURE1_TCOEF 0x100 /* bit8 set means tCoefA expected */
#define FEATURE1_DRC 0x200 /* bit9 NOT set means DRC expected */
/* DSP firmware xmem defines */
#define TFA1_FW_XMEM_CALIBRATION_DONE 231
#define TFA2_FW_XMEM_CALIBRATION_DONE 516
#define TFA1_FW_XMEM_COUNT_BOOT 0xa1
#define TFA2_FW_XMEM_COUNT_BOOT 512
#define TFA2_FW_XMEM_CMD_COUNT 520
/* note that the following defs rely on the handle variable */
#define TFA_FW_XMEM_CALIBRATION_DONE TFA_FAM_FW(tfa, XMEM_CALIBRATION_DONE)
#define TFA_FW_XMEM_COUNT_BOOT TFA_FAM_FW(tfa, XMEM_COUNT_BOOT)
#define TFA_FW_XMEM_CMD_COUNT TFA_FAM_FW(tfa, XMEM_CMD_COUNT)
#define TFA2_FW_ReZ_SCALE 65536
#define TFA1_FW_ReZ_SCALE 16384
#endif /* TFA98XX_INTERNALS_H */

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/*
* Copyright 2016-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* tfa_ext.h
*
* Created on: Jun 8, 2016
* Author: wim
*/
#ifndef TFA_SRC_TFA_EXT_H_
#define TFA_SRC_TFA_EXT_H_
#include "tfa_device.h"
/*
* events
*/
/** Maximum value for enumerator */
#define LVM_MAXENUM (0xffff)
/**
This enum type specifies the different events that may trigger a callback.
*/
enum tfadsp_event_en {
TFADSP_CMD_ACK = 1, /**< Command handling is completed */
TFADSP_SOFT_MUTE_READY = 8, /**< Muting completed */
TFADSP_VOLUME_READY = 16, /**< Volume change completed */
TFADSP_DAMAGED_SPEAKER = 32, /**< Damaged speaker was detected */
TFADSP_CALIBRATE_DONE = 64, /**< Calibration is completed */
TFADSP_SPARSESIG_DETECTED = 128, /**< Sparse signal detected */
TFADSP_CMD_READY = 256, /**< Ready to receive commands */
TFADSP_EXT_PWRUP = 0x8000, /**< DSP API has started, powered up */
TFADSP_EXT_PWRDOWN = 0x8001, /**< DSP API stopped, power down */
TFADSP_EVENT_DUMMY = LVM_MAXENUM
};
typedef int (*tfa_event_handler_t)(struct tfa_device *tfa,
enum tfadsp_event_en tfadsp_event);
typedef int (*dsp_send_message_t)(struct tfa_device *tfa, int length,
const char *buf);
typedef int (*dsp_read_message_t)(struct tfa_device *tfa, int length,
char *buf);
typedef int (*dsp_write_reg_t)(struct tfa_device *tfa, unsigned char subaddress,
unsigned short value);
int tfa_ext_register(dsp_write_reg_t tfa_write_reg,
dsp_send_message_t tfa_send_message,
dsp_read_message_t tfa_read_message,
tfa_event_handler_t *tfa_event_handler);
#endif /* TFA_SRC_TFA_EXT_H_ */

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/*
* Copyright 2014-2017 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
internal functions for TFA layer (not shared with SRV and HAL layer!)
*/
#ifndef __TFA_INTERNAL_H__
#define __TFA_INTERNAL_H__
#include "tfa_dsp_fw.h"
#include "tfa_ext.h"
#if __GNUC__ >= 4
#define TFA_INTERNAL __attribute__((visibility("hidden")))
#else
#define TFA_INTERNAL
#endif
#define TFA98XX_GENERIC_SLAVE_ADDRESS 0x1C
TFA_INTERNAL enum Tfa98xx_Error tfa98xx_check_rpc_status(struct tfa_device *tfa,
int *pRpcStatus);
TFA_INTERNAL enum Tfa98xx_Error tfa98xx_wait_result(struct tfa_device *tfa,
int waitRetryCount);
#endif /* __TFA_INTERNAL_H__ */

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/*
* Copyright 2015-2018 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _TFA_PLATFORM_INTERFACE_DEFINITION_H_
#define _TFA_PLATFORM_INTERFACE_DEFINITION_H_
#define AFE_MODULE_ID_TFADSP_RX (0x1000B911)
#define AFE_MODULE_ID_TFADSP_TX (0x1000B912)
#define AFE_PARAM_ID_TFADSP_TX_SET_ENABLE (0x1000B920)
#define AFE_PARAM_ID_TFADSP_RX_CFG (0x1000B921)
#define AFE_PARAM_ID_TFADSP_RX_GET_RESULT (0x1000B922)
#define AFE_PARAM_ID_TFADSP_RX_SET_BYPASS (0x1000B923)
#define TFA_USING_PRIMARY_MI2S
#if defined(TFA_USING_SECONDARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_SECONDARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_SECONDARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "SEC_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "SEC_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "SECONDARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_SECONDARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_SECONDARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Secondary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Secondary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "SEC_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_TERTIARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_TERTIARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_TERTIARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "TERT_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "TERT_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "TERTIARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_TERTIARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_TERTIARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Tertiary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Tertiary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "TERT_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_QUATERNARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUATERNARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUATERNARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUAT_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUAT_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "QUATERNARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUATERNARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUATERNARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Quaternary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Quaternary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUAT_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_QUINARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUINARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUINARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUIN_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUIN_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "QUINARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUINARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUINARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Quinary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Quinary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUIN_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_PRIMARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_PRIMARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_PRIMARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "PRI_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "PRI_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "PRI_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_PRI_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_PRI_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Primary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Primary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "PRI_MI2S_TX_HOSTLESS"
#else
#error you should define which mi2s will be used for TFA device.
#endif
#endif /* _TFA_PLATFORM_INTERFACE_DEFINITION_H_ */

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techpack/audio/asoc/codecs/tfa98xx/inc/tfa_service.h Normal file
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techpack/audio/asoc/codecs/tfa98xx/inc/versions.h Normal file
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#ifndef _VERSIONS_H
#define TFA98XX_GIT_VERSIONS "v6.5.2_xxxxxxxxxx"
#define _VERSIONS_H
#endif

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