TechPanelGM/kernel_xiaomi_sm8250
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dt-bindings: clk: lpasscc-scuba: Add support for LPASS AONCC and AUDIOCC

Browse Source 
Add bindings for LPASS AON, AUDIO clock controllers on scuba platform
for clients to be able to request for clocks from these clock controllers.

Change-Id: I5d09794c3bfdc1f1874b2edfadfac60863b44b81
Signed-off-by: Smeet Raj <quic_smeeraj@quicinc.com>
This commit is contained in:
Smeet Raj
2024-09-27 09:50:46 +05:30
parent 740cf694a7
commit 99c1e1b071
2 changed files with 127 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
include/dt-bindings/clock/qcom,scuba-lpassaoncc.h Normal file
View File

@@ -0,0 +1,57 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AON_CC_SCUBA_H
#define _DT_BINDINGS_CLK_QCOM_LPASS_AON_CC_SCUBA_H
/* LPASS_AON_CC clocks */
#define LPASS_AON_CC_AHB_TIMEOUT_CLK 0
#define LPASS_AON_CC_AON_H_CLK 1
#define LPASS_AON_CC_AUDIO_HM_H_CLK 2
#define LPASS_AON_CC_AUDIO_HM_SLEEP_CLK 3
#define LPASS_AON_CC_BUS_ALT_CLK 4
#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
#define LPASS_AON_CC_CDIV_VA_DIV_CLK_SRC 6
#define LPASS_AON_CC_CPR_CLK 7
#define LPASS_AON_CC_CPR_CLK_SRC 8
#define LPASS_AON_CC_CSR_H_CLK 9
#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 10
#define LPASS_AON_CC_MCC_ACCESS_CLK 11
#define LPASS_AON_CC_PDC_GDS_CLK 12
#define LPASS_AON_CC_PDC_H_CLK 13
#define LPASS_AON_CC_PLL 14
#define LPASS_AON_CC_PLL_OUT_AUX 15
#define LPASS_AON_CC_PLL_OUT_AUX2 16
#define LPASS_AON_CC_Q6_AHBM_CLK 17
#define LPASS_AON_CC_Q6_AHBS_CLK 18
#define LPASS_AON_CC_Q6_ATBM_CLK 19
#define LPASS_AON_CC_Q6_XO_CLK 20
#define LPASS_AON_CC_Q6_XO_CLK_SRC 21
#define LPASS_AON_CC_Q6_XPU2_CLIENT_CLK 22
#define LPASS_AON_CC_Q6_XPU2_CONFIG_CLK 23
#define LPASS_AON_CC_QSM_XO_CLK 24
#define LPASS_AON_CC_RO_CLK 25
#define LPASS_AON_CC_RO_PLL 26
#define LPASS_AON_CC_RO_PLL_OUT_EVEN 27
#define LPASS_AON_CC_RO_PLL_OUT_MAIN 28
#define LPASS_AON_CC_RSC_HCLK_CLK 29
#define LPASS_AON_CC_SLEEP_CLK 30
#define LPASS_AON_CC_SSC_H_CLK 31
#define LPASS_AON_CC_TX_MCLK_2X_CLK 32
#define LPASS_AON_CC_TX_MCLK_CLK 33
#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 34
#define LPASS_AON_CC_VA_2X_CLK 35
#define LPASS_AON_CC_VA_CLK 36
#define LPASS_AON_CC_VA_MEM0_CLK 37
#define LPASS_AON_CC_VA_RCG_CLK_SRC 38
#define LPASS_AON_CC_VA_XPU2_CLIENT_CLK 39
#define LPASS_AON_CC_VS_VDDCX_CLK 40
#define LPASS_AON_CC_VS_VDDCX_CLK_SRC 41
#define LPASS_AON_CC_VS_VDDMX_CLK 42
#define LPASS_AON_CC_VS_VDDMX_CLK_SRC 43
#define LPASS_QDSP6SS_SLEEP_CLK 44
#define LPASS_QDSP6SS_XO_CLK 45
#endif

70
include/dt-bindings/clock/qcom,scuba-lpassaudiocc.h Normal file
View File

@@ -0,0 +1,70 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SCUBA_H
#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SCUBA_H
/* LPASS_AUDIO_CC clocks */
#define AUD_SLIMBUS_CLK_SRC 0
#define LPASS_AUDIO_CC_AUD_SLIMBUS_CLK 1
#define LPASS_AUDIO_CC_AUD_SLIMBUS_CORE_CLK 2
#define LPASS_AUDIO_CC_AUD_SLIMBUS_NPL_CLK 3
#define LPASS_AUDIO_CC_BUS_CLK 4
#define LPASS_AUDIO_CC_BUS_TIMEOUT_CLK 5
#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 6
#define LPASS_AUDIO_CC_CDIV_WSA_MCLK_DIV_CLK_SRC 7
#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 8
#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 9
#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 10
#define LPASS_AUDIO_CC_CODEC_MEM3_CLK 11
#define LPASS_AUDIO_CC_CODEC_MEM_CLK 12
#define LPASS_AUDIO_CC_DIG_PLL 13
#define LPASS_AUDIO_CC_DIG_PLL_OUT_AUX 14
#define LPASS_AUDIO_CC_EXT_IF1_CLK_SRC 15
#define LPASS_AUDIO_CC_EXT_IF1_EBIT_CLK 16
#define LPASS_AUDIO_CC_EXT_IF1_IBIT_CLK 17
#define LPASS_AUDIO_CC_EXT_IF2_CLK_SRC 18
#define LPASS_AUDIO_CC_EXT_IF2_EBIT_CLK 19
#define LPASS_AUDIO_CC_EXT_IF2_IBIT_CLK 20
#define LPASS_AUDIO_CC_EXT_IF3_CLK_SRC 21
#define LPASS_AUDIO_CC_EXT_IF3_EBIT_CLK 22
#define LPASS_AUDIO_CC_EXT_IF3_IBIT_CLK 23
#define LPASS_AUDIO_CC_EXT_IF4_CLK_SRC 24
#define LPASS_AUDIO_CC_EXT_IF4_EBIT_CLK 25
#define LPASS_AUDIO_CC_EXT_IF4_IBIT_CLK 26
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 27
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 28
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 29
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 30
#define LPASS_AUDIO_CC_LPAIF_PCMOE_CLK 31
#define LPASS_AUDIO_CC_LPAIF_PCMOE_CLK_SRC 32
#define LPASS_AUDIO_CC_PLL 33
#define LPASS_AUDIO_CC_PLL_OUT_AUX 34
#define LPASS_AUDIO_CC_PLL_OUT_AUX2 35
#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 36
#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 37
#define LPASS_AUDIO_CC_RX_MCLK_CLK 38
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 39
#define LPASS_AUDIO_CC_SAMPLING_CLK 40
#define LPASS_AUDIO_CC_WSA_MCLK_2X_CLK 41
#define LPASS_AUDIO_CC_WSA_MCLK_CLK 42
#define LPASS_AUDIO_CC_WSA_MCLK_CLK_SRC 43
#define LPASS_AUDIO_CC_XPU2_CLIENT_CLK 44
#define LPASS_AON_CC_PLL_OUT_ODD_CLK 45
/* LPASS_AUDIO_CC resets */
#define LPASS_AUDIO_CC_EXT_IF1_BCR 0
#define LPASS_AUDIO_CC_EXT_IF2_BCR 1
#define LPASS_AUDIO_CC_EXT_IF3_BCR 2
#define LPASS_AUDIO_CC_EXT_IF4_BCR 3
#define LPASS_AUDIO_CC_EXT_MCLK0_BCR 4
#define LPASS_AUDIO_CC_EXT_MCLK1_BCR 5
#define LPASS_AUDIO_CC_PCM_DATA_OE_BCR 6
#define LPASS_AUDIO_CC_QCA_SLIMBUS_BCR 7
#define LPASS_AUDIO_CC_RX_MCLK_BCR 8
#define LPASS_AUDIO_CC_TX_MCLK_BCR 9
#define LPASS_AUDIO_CC_WSA_MCLK_BCR 10
#endif