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arm64: tlb: Ensure we execute an ISB following walk cache invalidation

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commit 51696d346c49c6cf4f29e9b20d6e15832a2e3408 upstream.

05f2d2f83b ("arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable")
added a new TLB invalidation helper which is used when freeing
intermediate levels of page table used for kernel mappings, but is
missing the required ISB instruction after completion of the TLBI
instruction.

Add the missing barrier.

Cc: <stable@vger.kernel.org>
Fixes: 05f2d2f83b ("arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable")
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Will Deacon
2019-08-22 15:03:45 +01:00
committed by Greg Kroah-Hartman
parent fc7d6bfdd7
commit 8cfe3b8aa3
1 changed files with 1 additions and 0 deletions
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arch/arm64/include/asm/tlbflush.h
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@@ -224,6 +224,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
__tlbi(vaae1is, addr);
dsb(ish);
isb();
}
#endif