msm: kgsl: Add apb_pclk to the clock list and increase max clock count

KGSL needs to enable apb_pclk for QDSS register access.
Add apb_pclk to the clock list. Increment KGSL_MAX_CLKS
and MAX_GMU_CLKS to support apb_clk.

Change-Id: I9a98fa7ef09f98bdd0897a9cd1dd51b6468a5a51
Signed-off-by: Harshitha Sai Neelati <hsaine@codeaurora.org>

drivers/gpu/msm/kgsl_gmu_core.h

@@ -21,7 +21,7 @@
 #error "CNOC levels cannot exceed GX levels"
 #endif
 
-#define MAX_GMU_CLKS 6
+#define MAX_GMU_CLKS 7
 
 /*
  * These are the different ways the GMU can boot. GMU_WARM_BOOT is waking up

drivers/gpu/msm/kgsl_pwrctrl.c

@@ -51,6 +51,7 @@ static const char * const clocks[] = {
 	"gmu_clk",
 	"ahb_clk",
 	"smmu_vote",
+	"apb_pclk",
 };
 
 static unsigned long ib_votes[KGSL_MAX_BUSLEVELS];

drivers/gpu/msm/kgsl_pwrctrl.h

@@ -23,7 +23,7 @@
 #define KGSL_GPU_CFG_PATH_LOW	1
 #define KGSL_GPU_CFG_PATH_HIGH	2
 
-#define KGSL_MAX_CLKS 17
+#define KGSL_MAX_CLKS 18
 #define KGSL_MAX_REGULATORS 2
 
 #define KGSL_MAX_PWRLEVELS 10