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mhi: core: Make sure reg_write_q stores visible to other cores

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mhi_reg_write_enqueue API stores reg, val and valid which can go
out of order. In case valid is set to true before val is set,
offload worker running on another core ends up writing stale value
to register. Another possibility is valid being set to true but not
visible to other cores. When offload worker gets a chance to run,
this results into skipping register write. Fix these issues by
adding smp_wmb() between stores of val and valid and another after
valid is set.

Change-Id: I3b930e7fad4252d34386de525491f94997b34f36
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
This commit is contained in:
Hemant Kumar
2020-04-17 15:48:58 -07:00
parent 84b56d3ab5
commit 6fb52b6c40
1 changed files with 14 additions and 0 deletions
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14
drivers/bus/mhi/core/mhi_main.c
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@@ -118,7 +118,21 @@ static void mhi_reg_write_enqueue(struct mhi_controller *mhi_cntrl,
mhi_cntrl->reg_write_q[q_index].reg_addr = reg_addr;
mhi_cntrl->reg_write_q[q_index].val = val;
/*
* prevent reordering to make sure val is set before valid is set to
* true. This prevents offload worker running on another core to write
* stale value to register with valid set to true.
*/
smp_wmb();
mhi_cntrl->reg_write_q[q_index].valid = true;
/*
* make sure valid value is visible to other cores to prevent offload
* worker from skipping the reg write.
*/
smp_wmb();
}
void mhi_write_reg_offload(struct mhi_controller *mhi_cntrl,