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Merge remote-tracking branch 'qcom_sm8250/lineage-20' into lineage-20

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Change-Id: I6d6e6fa0e8a40b75433926b887253f77da823bb3
This commit is contained in:
Sebastiano Barezzi
2023-05-14 17:50:36 +02:00
parent 1ffa0dc3d4 cb78c3f502
commit 231d12aa69
1480 changed files with 241204 additions and 11274 deletions
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21
Documentation/admin-guide/hw-vuln/spectre.rst
View File

@@ -479,8 +479,16 @@ Spectre variant 2
On Intel Skylake-era systems the mitigation covers most, but not all,
cases. See :ref:`[3] <spec_ref3>` for more details.
On CPUs with hardware mitigation for Spectre variant 2 (e.g. Enhanced
IBRS on x86), retpoline is automatically disabled at run time.
On CPUs with hardware mitigation for Spectre variant 2 (e.g. IBRS
or enhanced IBRS on x86), retpoline is automatically disabled at run time.
Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
boot, by setting the IBRS bit, and they're automatically protected against
Spectre v2 variant attacks, including cross-thread branch target injections
on SMT systems (STIBP). In other words, eIBRS enables STIBP too.
Legacy IBRS systems clear the IBRS bit on exit to userspace and
therefore explicitly enable STIBP for that
The retpoline mitigation is turned on by default on vulnerable
CPUs. It can be forced on or off by the administrator
@@ -504,9 +512,12 @@ Spectre variant 2
For Spectre variant 2 mitigation, individual user programs
can be compiled with return trampolines for indirect branches.
This protects them from consuming poisoned entries in the branch
target buffer left by malicious software. Alternatively, the
programs can disable their indirect branch speculation via prctl()
(See :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
target buffer left by malicious software.
On legacy IBRS systems, at return to userspace, implicit STIBP is disabled
because the kernel clears the IBRS bit. In this case, the userspace programs
can disable indirect branch speculation via prctl() (See
:ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
On x86, this will turn on STIBP to guard against attacks from the
sibling thread when the user program is running, and use IBPB to
flush the branch target buffer when switching to/from the program.

30
Documentation/arm64/tagged-address-abi.rst
View File

@@ -45,14 +45,24 @@ how the user addresses are used by the kernel:
1. User addresses not accessed by the kernel but used for address space
management (e.g. ``mprotect()``, ``madvise()``). The use of valid
tagged pointers in this context is allowed with the exception of
``brk()``, ``mmap()`` and the ``new_address`` argument to
``mremap()`` as these have the potential to alias with existing
user addresses.
tagged pointers in this context is allowed with these exceptions:
NOTE: This behaviour changed in v5.6 and so some earlier kernels may
incorrectly accept valid tagged pointers for the ``brk()``,
``mmap()`` and ``mremap()`` system calls.
- ``brk()``, ``mmap()`` and the ``new_address`` argument to
``mremap()`` as these have the potential to alias with existing
user addresses.
NOTE: This behaviour changed in v5.6 and so some earlier kernels may
incorrectly accept valid tagged pointers for the ``brk()``,
``mmap()`` and ``mremap()`` system calls.
- The ``range.start``, ``start`` and ``dst`` arguments to the
``UFFDIO_*`` ``ioctl()``s used on a file descriptor obtained from
``userfaultfd()``, as fault addresses subsequently obtained by reading
the file descriptor will be untagged, which may otherwise confuse
tag-unaware programs.
NOTE: This behaviour changed in v5.14 and so some earlier kernels may
incorrectly accept valid tagged pointers for this system call.
2. User addresses accessed by the kernel (e.g. ``write()``). This ABI
relaxation is disabled by default and the application thread needs to
@@ -113,6 +123,12 @@ ABI relaxation:
- ``shmat()`` and ``shmdt()``.
- ``brk()`` (since kernel v5.6).
- ``mmap()`` (since kernel v5.6).
- ``mremap()``, the ``new_address`` argument (since kernel v5.6).
Any attempt to use non-zero tagged pointers may result in an error code
being returned, a (fatal) signal being raised, or other modes of
failure.

4
Documentation/dev-tools/gdb-kernel-debugging.rst
View File

@@ -39,6 +39,10 @@ Setup
this mode. In this case, you should build the kernel with
CONFIG_RANDOMIZE_BASE disabled if the architecture supports KASLR.
- Build the gdb scripts (required on kernels v5.1 and above)::
make scripts_gdb
- Enable the gdb stub of QEMU/KVM, either
- at VM startup time by appending "-s" to the QEMU command line

4
Documentation/networking/00-INDEX
View File

@@ -94,8 +94,8 @@ gianfar.txt
- Gianfar Ethernet Driver.
i40e.txt
- README for the Intel Ethernet Controller XL710 Driver (i40e).
i40evf.txt
- Short note on the Driver for the Intel(R) XL710 X710 Virtual Function
iavf.txt
- README for the Intel Ethernet Adaptive Virtual Function Driver (iavf).
ieee802154.txt
- Linux IEEE 802.15.4 implementation, API and drivers
igb.txt

16
Documentation/networking/i40evf.txt → Documentation/networking/iavf.txt
View File

@@ -2,7 +2,7 @@ Linux* Base Driver for Intel(R) Network Connection
==================================================
Intel Ethernet Adaptive Virtual Function Linux driver.
Copyright(c) 2013-2017 Intel Corporation.
Copyright(c) 2013-2018 Intel Corporation.
Contents
========
@@ -11,20 +11,21 @@ Contents
- Known Issues/Troubleshooting
- Support
This file describes the i40evf Linux* Base Driver.
This file describes the iavf Linux* Base Driver. This driver
was formerly called i40evf.
The i40evf driver supports the below mentioned virtual function
The iavf driver supports the below mentioned virtual function
devices and can only be activated on kernels running the i40e or
newer Physical Function (PF) driver compiled with CONFIG_PCI_IOV.
The i40evf driver requires CONFIG_PCI_MSI to be enabled.
The iavf driver requires CONFIG_PCI_MSI to be enabled.
The guest OS loading the i40evf driver must support MSI-X interrupts.
The guest OS loading the iavf driver must support MSI-X interrupts.
Supported Hardware
==================
Intel XL710 X710 Virtual Function
Intel Ethernet Adaptive Virtual Function
Intel X722 Virtual Function
Intel Ethernet Adaptive Virtual Function
Identifying Your Adapter
========================
@@ -32,7 +33,8 @@ Identifying Your Adapter
For more information on how to identify your adapter, go to the
Adapter & Driver ID Guide at:
http://support.intel.com/support/go/network/adapter/idguide.htm
https://www.intel.com/content/www/us/en/support/articles/000005584/network-and-i-o/ethernet-products.html
Known Issues/Troubleshooting
============================

2
Documentation/sound/hd-audio/models.rst
View File

@@ -691,7 +691,7 @@ ref
no-jd
BIOS setup but without jack-detection
intel
Intel DG45* mobos
Intel D*45* mobos
dell-m6-amic
Dell desktops/laptops with analog mics
dell-m6-dmic

2
MAINTAINERS
View File

@@ -7411,7 +7411,7 @@ F: Documentation/networking/ixgb.txt
F: Documentation/networking/ixgbe.txt
F: Documentation/networking/ixgbevf.txt
F: Documentation/networking/i40e.txt
F: Documentation/networking/i40evf.txt
F: Documentation/networking/iavf.txt
F: Documentation/networking/ice.txt
F: drivers/net/ethernet/intel/
F: drivers/net/ethernet/intel/*/

15
Makefile
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 4
PATCHLEVEL = 19
SUBLEVEL = 272
SUBLEVEL = 282
EXTRAVERSION =
NAME = "People's Front"
@@ -88,10 +88,17 @@ endif
# If the user is running make -s (silent mode), suppress echoing of
# commands
# make-4.0 (and later) keep single letter options in the 1st word of MAKEFLAGS.
ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),)
quiet=silent_
tools_silent=s
ifeq ($(filter 3.%,$(MAKE_VERSION)),)
silence:=$(findstring s,$(firstword -$(MAKEFLAGS)))
else
silence:=$(findstring s,$(filter-out --%,$(MAKEFLAGS)))
endif
ifeq ($(silence),s)
quiet=silent_
tools_silent=s
endif
export quiet Q KBUILD_VERBOSE

4
arch/alpha/kernel/module.c
View File

@@ -158,10 +158,8 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
base = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr;
symtab = (Elf64_Sym *)sechdrs[symindex].sh_addr;
/* The small sections were sorted to the end of the segment.
The following should definitely cover them. */
gp = (u64)me->core_layout.base + me->core_layout.size - 0x8000;
got = sechdrs[me->arch.gotsecindex].sh_addr;
gp = got + 0x8000;
for (i = 0; i < n; i++) {
unsigned long r_sym = ELF64_R_SYM (rela[i].r_info);

30
arch/alpha/kernel/traps.c
View File

@@ -235,7 +235,21 @@ do_entIF(unsigned long type, struct pt_regs *regs)
{
int signo, code;
if ((regs->ps & ~IPL_MAX) == 0) {
if (type == 3) { /* FEN fault */
/* Irritating users can call PAL_clrfen to disable the
FPU for the process. The kernel will then trap in
do_switch_stack and undo_switch_stack when we try
to save and restore the FP registers.
Given that GCC by default generates code that uses the
FP registers, PAL_clrfen is not useful except for DoS
attacks. So turn the bleeding FPU back on and be done
with it. */
current_thread_info()->pcb.flags |= 1;
__reload_thread(&current_thread_info()->pcb);
return;
}
if (!user_mode(regs)) {
if (type == 1) {
const unsigned int *data
= (const unsigned int *) regs->pc;
@@ -368,20 +382,6 @@ do_entIF(unsigned long type, struct pt_regs *regs)
}
break;
case 3: /* FEN fault */
/* Irritating users can call PAL_clrfen to disable the
FPU for the process. The kernel will then trap in
do_switch_stack and undo_switch_stack when we try
to save and restore the FP registers.
Given that GCC by default generates code that uses the
FP registers, PAL_clrfen is not useful except for DoS
attacks. So turn the bleeding FPU back on and be done
with it. */
current_thread_info()->pcb.flags |= 1;
__reload_thread(&current_thread_info()->pcb);
return;
case 5: /* illoc */
default: /* unexpected instruction-fault type */
;

2
arch/arm/boot/dts/exynos3250-rinato.dts
View File

@@ -237,7 +237,7 @@
i80-if-timings {
cs-setup = <0>;
wr-setup = <0>;
wr-act = <1>;
wr-active = <1>;
wr-hold = <0>;
};
};

2
arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
View File

@@ -10,7 +10,7 @@
/ {
thermal-zones {
cpu_thermal: cpu-thermal {
thermal-sensors = <&tmu 0>;
thermal-sensors = <&tmu>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {

2
arch/arm/boot/dts/exynos4.dtsi
View File

@@ -611,7 +611,7 @@
status = "disabled";
hdmi_i2c_phy: hdmiphy@38 {
compatible = "exynos4210-hdmiphy";
compatible = "samsung,exynos4210-hdmiphy";
reg = <0x38>;
};
};

1
arch/arm/boot/dts/exynos5410-odroidxu.dts
View File

@@ -113,7 +113,6 @@
};
&cpu0_thermal {
thermal-sensors = <&tmu_cpu0 0>;
polling-delay-passive = <0>;
polling-delay = <0>;

2
arch/arm/boot/dts/exynos5420.dtsi
View File

@@ -530,7 +530,7 @@
};
mipi_phy: mipi-video-phy {
compatible = "samsung,s5pv210-mipi-video-phy";
compatible = "samsung,exynos5420-mipi-video-phy";
syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};

3
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -924,7 +924,7 @@
status = "disabled";
};
spdif: sound@ff88b0000 {
spdif: sound@ff8b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
@@ -1172,6 +1172,7 @@
clock-names = "dp", "pclk";
phys = <&edp_phy>;
phy-names = "dp";
power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_EDP>;
reset-names = "dp";
rockchip,grf = <&grf>;

2
arch/arm/boot/dts/spear320-hmi.dts
View File

@@ -248,7 +248,7 @@
irq-trigger = <0x1>;
stmpegpio: stmpe-gpio {
compatible = "stmpe,gpio";
compatible = "st,stmpe-gpio";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;

2
arch/arm/crypto/curve25519-core.S
View File

@@ -10,8 +10,8 @@
#include <linux/linkage.h>
.text
.fpu neon
.arch armv7-a
.fpu neon
.align 4
ENTRY(curve25519_neon)

24
arch/arm/mach-imx/mmdc.c
View File

@@ -105,6 +105,7 @@ struct mmdc_pmu {
cpumask_t cpu;
struct hrtimer hrtimer;
unsigned int active_events;
int id;
struct device *dev;
struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
struct hlist_node node;
@@ -445,8 +446,6 @@ static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
void __iomem *mmdc_base, struct device *dev)
{
int mmdc_num;
*pmu_mmdc = (struct mmdc_pmu) {
.pmu = (struct pmu) {
.task_ctx_nr = perf_invalid_context,
@@ -463,15 +462,16 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
.active_events = 0,
};
mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
return mmdc_num;
return pmu_mmdc->id;
}
static int imx_mmdc_remove(struct platform_device *pdev)
{
struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
perf_pmu_unregister(&pmu_mmdc->pmu);
iounmap(pmu_mmdc->mmdc_base);
@@ -485,7 +485,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
{
struct mmdc_pmu *pmu_mmdc;
char *name;
int mmdc_num;
int ret;
const struct of_device_id *of_id =
of_match_device(imx_mmdc_dt_ids, &pdev->dev);
@@ -508,14 +507,14 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
cpuhp_mmdc_state = ret;
}
mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
if (mmdc_num == 0)
name = "mmdc";
else
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", mmdc_num);
ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
if (ret < 0)
goto pmu_free;
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", ret);
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
@@ -536,6 +535,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
hrtimer_cancel(&pmu_mmdc->hrtimer);
pmu_free:

2
arch/arm/mach-omap1/timer.c
View File

@@ -165,7 +165,7 @@ static int __init omap1_dm_timer_init(void)
kfree(pdata);
err_free_pdev:
platform_device_unregister(pdev);
platform_device_put(pdev);
return ret;
}

1
arch/arm/mach-omap2/timer.c
View File

@@ -650,6 +650,7 @@ static void __init realtime_counter_init(void)
}
rate = clk_get_rate(sys_clk);
clk_put(sys_clk);
if (soc_is_dra7xx()) {
/*

1
arch/arm/mach-zynq/slcr.c
View File

@@ -222,6 +222,7 @@ int __init zynq_early_slcr_init(void)
zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
if (IS_ERR(zynq_slcr_regmap)) {
pr_err("%s: failed to find zynq-slcr\n", __func__);
of_node_put(np);
return -ENODEV;
}

30
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@@ -47,6 +47,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
cpu1: cpu@1 {
@@ -55,6 +56,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
cpu2: cpu@2 {
@@ -63,6 +65,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
cpu3: cpu@3 {
@@ -71,6 +74,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
};
l2: l2-cache0 {
@@ -151,6 +155,28 @@
#clock-cells = <0>;
};
scpi {
compatible = "arm,scpi-pre-1.0";
mboxes = <&mailbox 1 &mailbox 2>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
clock-output-names = "vcpu";
};
};
scpi_sensors: sensors {
compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -167,7 +193,7 @@
sd_emmc_b: sd@5000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x5000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
@@ -179,7 +205,7 @@
sd_emmc_c: mmc@7000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x7000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,

12
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@@ -150,7 +150,7 @@
reg = <0x14 0x10>;
};
eth_mac: eth_mac@34 {
eth_mac: eth-mac@34 {
reg = <0x34 0x10>;
};
@@ -167,7 +167,7 @@
scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
@@ -423,7 +423,7 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
hwrng: rng {
hwrng: rng@0 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
@@ -470,21 +470,21 @@
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x70000 0x0 0x800>;
interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_b: mmc@72000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x72000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_c: mmc@74000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x74000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};

2
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@@ -636,7 +636,7 @@
};
};
eth-phy-mux {
eth-phy-mux@55c {
compatible = "mdio-mux-mmioreg", "mdio-mux";
#address-cells = <1>;
#size-cells = <0>;

1
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@@ -380,6 +380,7 @@
pwm: pwm@11006000 {
compatible = "mediatek,mt7622-pwm";
reg = <0 0x11006000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_PWM_SEL>,
<&pericfg CLK_PERI_PWM_PD>,

12
arch/arm64/boot/dts/vendor/bindings/arm/msm/msm.txt vendored
View File

@@ -62,6 +62,12 @@ SoCs:
- KHAJE
compatible = "qcom,khaje"
- KHAJEP
compatible = "qcom,khajep"
- KHAJEQ
compatible = "qcom,khajeq"
- SCUBA
compatible = "qcom,scuba"
@@ -253,6 +259,12 @@ compatible = "qcom,bengalp-idp"
compatible = "qcom,khaje-idp"
compatible = "qcom,khaje-qrd"
compatible = "qcom,khaje-atp"
compatible = "qcom,khajep-idp"
compatible = "qcom,khajep-qrd"
compatible = "qcom,khajeq-idp"
compatible = "qcom,khajeq-qrd"
compatible = "qcom,khajep-atp"
compatible = "qcom,khajeq-atp"
compatible = "qcom,scuba-rumi"
compatible = "qcom,scuba-idp"
compatible = "qcom,scuba-qrd"

2
arch/arm64/boot/dts/vendor/bindings/input/qpnp-power-on.txt vendored
View File

@@ -118,6 +118,8 @@ Optional properties:
power off trigger during system shutdown case.
- qcom,ps-hold-hard-reset-disable: Boolean property to disable PS_HOLD
power off trigger during system hard reset case.
- qcom,log-kpd-event: Boolean property to enable logging of KPDPWR status
during driver INIT and runtime when key is pressed.
Optional Sub-nodes:
- qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features

83
arch/arm64/boot/dts/vendor/qcom/Makefile vendored
View File

@@ -48,6 +48,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
kona-xrfusion-overlay.dtbo \
kona-xrfusion-ult-overlay.dtbo \
kona-arglass-overlay.dtbo \
kona-xrsku4-overlay.dtbo \
kona-hdk-overlay.dtbo
kona-cdp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
@@ -62,6 +63,7 @@ kona-qrd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-xrfusion-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-xrfusion-ult-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-arglass-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-xrsku4-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
kona-hdk-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
else
dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
@@ -72,6 +74,7 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
kona-xrfusion.dtb \
kona-xrfusion-ult.dtb \
kona-arglass.dtb \
kona-xrsku4.dtb \
kona-cdp.dtb \
kona-cdp-lcd.dtb \
kona-cdp-lcd-tron.dtb \
@@ -85,6 +88,7 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
kona-v2-xrfusion.dtb \
kona-v2-xrfusion-ult.dtb \
kona-v2-arglass.dtb \
kona-v2-xrsku4.dtb \
kona-hdk.dtb \
kona-v2.1-mtp.dtb \
kona-v2.1-mtp-ws.dtb \
@@ -95,8 +99,11 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
kona-v2.1-xrfusion.dtb \
kona-v2.1-xrfusion-ult.dtb \
kona-v2.1-arglass.dtb \
kona-v2.1-xrsku4.dtb \
qrb5165-iot-rb5.dtb \
qrb5165m-iot-rb5.dtb \
qrb5165n-iot-rb5.dtb \
qrb5165n-v2-iot-rb5.dtb \
kona-v2.1-iot-rb5.dtb
endif
@@ -276,27 +283,67 @@ endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_KHAJE) += \
khaje-idp-overlay.dtbo \
khaje-atp-overlay.dtbo \
khaje-qrd-overlay.dtbo \
khaje-qrd-hvdcp3p5-overlay.dtbo \
khaje-qrd-nowcd9375-overlay.dtbo \
khaje-qrd-nopmi-overlay.dtbo \
khaje-idp-overlay.dtbo \
khaje-idp-nopmi-overlay.dtbo \
khaje-idp-usbc-overlay.dtbo \
khaje-idp-pm8010-overlay.dtbo \
khaje-qrd-nopmi-overlay.dtbo \
khaje-idps-display-90hz-overlay.dtbo \
khaje-atp-overlay.dtbo
khajep-atp-overlay.dtbo \
khajep-qrd-overlay.dtbo \
khajep-qrd-hvdcp3p5-overlay.dtbo \
khajep-qrd-nowcd9375-overlay.dtbo \
khajep-qrd-nopmi-overlay.dtbo \
khajep-idp-overlay.dtbo \
khajep-idp-nopmi-overlay.dtbo \
khajep-idp-usbc-overlay.dtbo \
khajep-idp-pm8010-overlay.dtbo \
khajep-idps-display-90hz-overlay.dtbo \
khajeq-atp-overlay.dtbo \
khajeq-qrd-overlay.dtbo \
khajeq-qrd-hvdcp3p5-overlay.dtbo \
khajeq-qrd-nowcd9375-overlay.dtbo \
khajeq-qrd-nopmi-overlay.dtbo \
khajeq-idp-overlay.dtbo \
khajeq-idp-nopmi-overlay.dtbo \
khajeq-idp-usbc-overlay.dtbo \
khajeq-idp-pm8010-overlay.dtbo \
khajeq-idps-display-90hz-overlay.dtbo
khaje-atp-overlay.dtbo-base := khaje.dtb
khaje-idp-overlay.dtbo-base := khaje.dtb
khaje-qrd-overlay.dtbo-base := khaje.dtb
khaje-qrd-hvdcp3p5-overlay.dtbo-base := khaje.dtb
khaje-qrd-nowcd9375-overlay.dtbo-base := khaje.dtb
khaje-idp-nopmi-overlay.dtbo-base := khaje.dtb
khaje-idp-usbc-overlay.dtbo-base := khaje.dtb
khaje-idp-pm8010-overlay.dtbo-base := khaje.dtb
khaje-qrd-nopmi-overlay.dtbo-base := khaje.dtb
khaje-idps-display-90hz-overlay.dtbo-base := khaje.dtb
khaje-atp-overlay.dtbo-base := khaje.dtb
khaje-qrd-overlay.dtbo-base := khaje.dtb
khaje-qrd-hvdcp3p5-overlay.dtbo-base := khaje.dtb
khaje-qrd-nopmi-overlay.dtbo-base := khaje.dtb
khaje-qrd-nowcd9375-overlay.dtbo-base := khaje.dtb
khajep-atp-overlay.dtbo-base := khajep.dtb
khajep-idps-display-90hz-overlay.dtbo-base := khajep.dtb
khajep-idp-overlay.dtbo-base := khajep.dtb
khajep-idp-nopmi-overlay.dtbo-base := khajep.dtb
khajep-idp-usbc-overlay.dtbo-base := khajep.dtb
khajep-idp-pm8010-overlay.dtbo-base := khajep.dtb
khajep-qrd-overlay.dtbo-base := khajep.dtb
khajep-qrd-hvdcp3p5-overlay.dtbo-base := khajep.dtb
khajep-qrd-nowcd9375-overlay.dtbo-base := khajep.dtb
khajep-qrd-nopmi-overlay.dtbo-base := khajep.dtb
khajeq-atp-overlay.dtbo-base := khajeq.dtb
khajeq-qrd-overlay.dtbo-base := khajeq.dtb
khajeq-qrd-hvdcp3p5-overlay.dtbo-base := khajeq.dtb
khajeq-qrd-nowcd9375-overlay.dtbo-base := khajeq.dtb
khajeq-qrd-nopmi-overlay.dtbo-base := khajeq.dtb
khajeq-idps-display-90hz-overlay.dtbo-base := khajeq.dtb
khajeq-idp-overlay.dtbo-base := khajeq.dtb
khajeq-idp-nopmi-overlay.dtbo-base := khajeq.dtb
khajeq-idp-pm8010-overlay.dtbo-base := khajeq.dtb
khajeq-idp-usbc-overlay.dtbo-base := khajeq.dtb
else
dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \
khaje-qrd.dtb \
@@ -307,7 +354,25 @@ dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \
khaje-idp-pm8010.dtb \
khaje-qrd-nopmi.dtb \
khaje-idps-display-90hz.dtb \
khaje-atp.dtb
khaje-atp.dtb \
khajep-atp.dtb \
khajep-qrd.dtb \
khajep-qrd-hvdcp3p5.dtb \
khajep-idps-display-90hz.dtb \
khajep-idp-nopmi.dtb \
khajep-idp-usbc.dtb \
khajep-idp-pm8010.dtb \
khajep-qrd-nowcd9375.dtb \
khajep-qrd-nopmi.dtb \
khajeq-atp.dtb \
khajeq-idps-display-90hz.dtb \
khajeq-idp-nopmi.dtb \
khajeq-idp-usbc.dtb \
khajeq-idp-pm8010.dtb \
khajeq-qrd.dtb \
khajeq-qrd-nowcd9375.dtb \
khajeq-qrd-hvdcp3p5.dtb \
khajeq-qrd-nopmi.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)

107
arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-idp.dtsi vendored
View File

@@ -118,8 +118,8 @@
&cam_sensor_rear1_reset_active>;
pinctrl-1 = <&cam_sensor_mclk1_suspend
&cam_sensor_rear1_reset_suspend>;
gpios = <&tlmm 19 0>,
<&tlmm 21 0>;
gpios = <&tlmm 21 0>,
<&tlmm 19 0>;
gpio-reset = <1>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
@@ -145,8 +145,8 @@
"cam_clk";
rgltr-cntrl-support;
pwm-switch;
rgltr-min-voltage = <1800000 2800000 1056000 0>;
rgltr-max-voltage = <1800000 2800000 1056000 0>;
rgltr-min-voltage = <1800000 2800000 1050000 0>;
rgltr-max-voltage = <1800000 2800000 1050000 0>;
rgltr-load-current = <0 80000 105000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
@@ -211,7 +211,7 @@
cell-index = <0>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <0>;
sensor-position-roll = <90>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <180>;
actuator-src = <&actuator_rear>;
@@ -255,7 +255,7 @@
cell-index = <1>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <1>;
sensor-position-roll = <90>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <180>;
actuator-src = <&actuator_rear_aux>;
@@ -278,8 +278,8 @@
&cam_sensor_rear1_reset_active>;
pinctrl-1 = <&cam_sensor_mclk1_suspend
&cam_sensor_rear1_reset_suspend>;
gpios = <&tlmm 19 0>,
<&tlmm 21 0>;
gpios = <&tlmm 21 0>,
<&tlmm 19 0>;
gpio-reset = <1>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
@@ -299,9 +299,9 @@
cell-index = <2>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <2>;
sensor-position-roll = <90>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <180>;
sensor-position-yaw = <0>;
eeprom-src = <&eeprom_front>;
cam_vio-supply = <&L7P>;
cam_vana-supply = <&L6P>;
@@ -311,8 +311,8 @@
"cam_clk";
rgltr-cntrl-support;
pwm-switch;
rgltr-min-voltage = <1800000 2800000 1056000 0>;
rgltr-max-voltage = <1800000 2800000 1056000 0>;
rgltr-min-voltage = <1800000 2800000 1050000 0>;
rgltr-max-voltage = <1800000 2800000 1050000 0>;
rgltr-load-current = <0 80000 105000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
@@ -329,10 +329,14 @@
<&tlmm 66 0>,
<&tlmm 67 0>;
gpio-reset = <1>;
gpio-custom1 = <2>;
gpio-custom2 = <3>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
"CAM_RESET2",
"CAM_CSIMUX_OE0",
"CAM_CSIMUX_SEL0";
sensor-mode = <0>;
cci-master = <1>;
status = "ok";
@@ -347,7 +351,7 @@
cell-index = <3>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <2>;
sensor-position-roll = <90>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <180>;
led-flash-src = <&led_flash_rear_aux2>;
@@ -378,10 +382,14 @@
<&tlmm 66 0>,
<&tlmm 67 0>;
gpio-reset = <1>;
gpio-custom1 = <2>;
gpio-custom2 = <3>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
"CAM_RESET3",
"CAM_CSIMUX_OE1",
"CAM_CSIMUX_SEL1";
sensor-mode = <0>;
cci-master = <0>;
status = "ok";
@@ -390,4 +398,73 @@
clock-cntl-level = "turbo";
clock-rates = <19200000>;
};
/*TPG0*/
qcom,cam-tpg0 {
cell-index = <4>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <4>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <180>;
gpios = <&tlmm 30 0>,
<&tlmm 35 0>;
gpio-reset = <1>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
sensor-mode = <0>;
status = "ok";
clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "turbo";
clock-rates = <19200000>;
};
/*TPG1*/
qcom,cam-tpg1 {
cell-index = <5>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <5>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <180>;
gpios = <&tlmm 30 0>,
<&tlmm 35 0>;
gpio-reset = <1>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
sensor-mode = <0>;
status = "ok";
clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "turbo";
clock-rates = <19200000>;
};
/*TPG2*/
qcom,cam-tpg2 {
cell-index = <6>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <6>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <180>;
gpios = <&tlmm 30 0>,
<&tlmm 35 0>;
gpio-reset = <1>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
sensor-mode = <0>;
status = "ok";
clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "turbo";
clock-rates = <19200000>;
};
};

10
arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-qrd.dtsi vendored
View File

@@ -145,8 +145,8 @@
"cam_clk";
rgltr-cntrl-support;
pwm-switch;
rgltr-min-voltage = <1800000 2800000 1056000 0>;
rgltr-max-voltage = <1800000 2800000 1056000 0>;
rgltr-min-voltage = <1800000 2800000 1050000 0>;
rgltr-max-voltage = <1800000 2800000 1050000 0>;
rgltr-load-current = <0 80000 105000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
@@ -301,7 +301,7 @@
cell-index = <2>;
compatible = "qcom,cam-sensor";
csiphy-sd-index = <2>;
sensor-position-roll = <90>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <0>;
eeprom-src = <&eeprom_front>;
@@ -313,8 +313,8 @@
"cam_clk";
rgltr-cntrl-support;
pwm-switch;
rgltr-min-voltage = <1800000 2800000 1056000 0>;
rgltr-max-voltage = <1800000 2800000 1056000 0>;
rgltr-min-voltage = <1800000 2800000 1050000 0>;
rgltr-max-voltage = <1800000 2800000 1050000 0>;
rgltr-load-current = <0 80000 105000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";

184
arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera.dtsi vendored
View File

@@ -8,7 +8,7 @@
cam_csiphy0: qcom,csiphy0 {
cell-index = <0>;
compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy";
reg = <0x05C52000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x52000>;
@@ -30,15 +30,16 @@
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
clock-rates =
<19200000 0 19200000 0>,
<341330000 0 200000000 0>,
<240000000 0 200000000 0>,
<341330000 0 200000000 0>,
<384000000 0 268800000 0>;
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
cam_csiphy1: qcom,csiphy1 {
cell-index = <1>;
compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy";
reg = <0x05C53000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x53000>;
@@ -60,15 +61,16 @@
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
clock-rates =
<19200000 0 19200000 0>,
<341330000 0 200000000 0>,
<240000000 0 200000000 0>,
<341330000 0 200000000 0>,
<384000000 0 268800000 0>;
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
cam_csiphy2: qcom,csiphy2 {
cell-index = <2>;
compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy";
reg = <0x05C54000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x54000>;
@@ -90,15 +92,16 @@
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
clock-rates =
<19200000 0 19200000 0>,
<341330000 0 200000000 0>,
<240000000 0 200000000 0>,
<341330000 0 200000000 0>,
<384000000 0 268800000 0>;
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
cam_cci0: qcom,cci0 {
cell-index = <0>;
compatible = "qcom,cci";
compatible = "qcom,cci-v1.2", "qcom,cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x05C1B000 0x1000>;
@@ -197,8 +200,7 @@
msm_cam_smmu_tfe {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x400 0x000>,
<&apps_smmu 0x401 0x000>;
iommus = <&apps_smmu 0x400 0x000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
label = "tfe";
@@ -217,9 +219,7 @@
msm_cam_smmu_ope {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x820 0x000>,
<&apps_smmu 0x821 0x020>,
<&apps_smmu 0x840 0x000>,
<&apps_smmu 0x841 0x000>;
<&apps_smmu 0x840 0x000>;
qcom,iommu-faults = "non-fatal";
multiple-client-devices;
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
@@ -238,8 +238,7 @@
msm_cam_smmu_cpas_cdm {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x800 0x000>,
<&apps_smmu 0x801 0x020>;
iommus = <&apps_smmu 0x800 0x000>;
label = "cpas-cdm0";
qcom,iommu-faults = "non-fatal";
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
@@ -273,6 +272,8 @@
reg = <0x5c11000 0x1000>,
<0x5c13000 0x4000>;
reg-cam-base = <0x11000 0x13000>;
cam_hw_fuse = <CAM_CPAS_ISP_FUSE_ID 0x01B401D0 5 CAM_CPAS_FEATURE_TYPE_DISABLE 2>,
<CAM_CPAS_ISP_PIX_FUSE_ID 0x01B401D0 6 CAM_CPAS_FEATURE_TYPE_DISABLE 2>;
interrupt-names = "cpas_camnoc";
interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
@@ -283,37 +284,42 @@
"gcc_camss_top_ahb_clk",
"gcc_camss_top_ahb_clk_src",
"gcc_camss_axi_clk",
"gcc_camss_axi_clk_src";
"gcc_camss_axi_clk_src",
"gcc_camss_nrt_axi_clk",
"gcc_camss_rt_axi_clk";
clocks =
<&gcc GCC_CAMERA_AHB_CLK>,
<&gcc GCC_CAMSS_TOP_AHB_CLK>,
<&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,
<&gcc GCC_CAMSS_AXI_CLK>,
<&gcc GCC_CAMSS_AXI_CLK_SRC>;
<&gcc GCC_CAMSS_AXI_CLK_SRC>,
<&gcc GCC_CAMSS_NRT_AXI_CLK>,
<&gcc GCC_CAMSS_RT_AXI_CLK>;
src-clock-name = "gcc_camss_axi_clk_src";
clock-rates =
<0 0 0 0 0>,
<0 80000000 80000000 19200000 19200000>,
<0 80000000 80000000 150000000 150000000>,
<0 80000000 80000000 200000000 200000000>,
<0 80000000 80000000 300000000 300000000>,
<0 80000000 80000000 300000000 300000000>,
<0 80000000 80000000 300000000 300000000>;
<0 0 0 0 0 0 0>,
<0 0 80000000 0 19200000 0 0>,
<0 0 80000000 0 150000000 0 0>,
<0 0 80000000 0 200000000 0 0>,
<0 0 80000000 0 300000000 0 0>,
<0 0 80000000 0 300000000 0 0>,
<0 0 80000000 0 300000000 0 0>;
clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
control-camnoc-axi-clk;
camnoc-bus-width = <32>;
camnoc-axi-clk-bw-margin-perc = <20>;
qcom,msm-bus,name = "cam_ahb"; /*Need to verify*/
qcom,msm-bus,num-cases = <7>; /*Need to verify*/
qcom,msm-bus,num-paths = <1>; /*Need to verify*/
qcom,msm-bus,vectors-KBps = /*Need to verify*/
qcom,msm-bus,name = "cam_ahb";
qcom,msm-bus,num-cases = <7>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
<MSM_BUS_MASTER_AMPSS_M0
@@ -417,6 +423,10 @@
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_OPE_WR_VID
CAM_CPAS_PATH_DATA_OPE_WR_DISP
CAM_CPAS_PATH_DATA_OPE_WR_REF>;
parent-node = <&level1_nrt0_rd_wr>;
};
@@ -427,6 +437,9 @@
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
constituent-paths =
<CAM_CPAS_PATH_DATA_OPE_RD_IN
CAM_CPAS_PATH_DATA_OPE_RD_REF>;
parent-node = <&level1_nrt0_rd_wr>;
};
@@ -591,23 +604,22 @@
"cphy_rx_clk_src",
"tfe_cphy_rx_clk",
"tfe_clk_src",
"tfe_clk",
"tfe_axi_clk";
"tfe_clk";
clocks =
<&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CLK>,
<&gcc GCC_CAMSS_AXI_CLK>;
<&gcc GCC_CAMSS_TFE_0_CLK>;
clock-rates =
<240000000 240000000 0 240000000 256000000 256000000 150000000>,
<384000000 384000000 0 341333333 460800000 460800000 200000000>,
<426400000 426400000 0 384000000 576000000 576000000 300000000>;
<240000000 0 240000000 0 256000000 0>,
<384000000 0 341333333 0 460800000 0>,
<426400000 0 384000000 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -623,19 +635,18 @@
camss-supply = <&gcc_camss_top_gdsc>;
clock-names =
"tfe_clk_src",
"tfe_clk",
"tfe_axi_clk";
"tfe_clk";
clocks =
<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CLK>,
<&gcc GCC_CAMSS_AXI_CLK>;
<&gcc GCC_CAMSS_TFE_0_CLK>;
clock-rates =
<256000000 256000000 150000000>,
<460800000 460800000 200000000>,
<576000000 576000000 300000000>;
<256000000 0>,
<460800000 0>,
<576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -657,23 +668,22 @@
"cphy_rx_clk_src",
"tfe_cphy_rx_clk",
"tfe_clk_src",
"tfe_clk",
"tfe_axi_clk";
"tfe_clk";
clocks =
<&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_1_CLK>,
<&gcc GCC_CAMSS_AXI_CLK>;
<&gcc GCC_CAMSS_TFE_1_CLK>;
clock-rates =
<240000000 240000000 0 240000000 256000000 256000000 150000000>,
<384000000 384000000 0 341333333 460800000 460800000 200000000>,
<426400000 426400000 0 384000000 576000000 576000000 300000000>;
<240000000 0 240000000 0 256000000 0>,
<384000000 0 341333333 0 460800000 0>,
<426400000 0 384000000 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -684,24 +694,23 @@
reg = <0x5c75000 0x5000>;
reg-cam-base = <0x75000>;
interrupt-names = "tfe1";
interrupts = <0 213 0>;
interrupts = <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&gcc_camss_top_gdsc>;
clock-names =
"tfe_clk_src",
"tfe_clk",
"tfe_axi_clk";
"tfe_clk";
clocks =
<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_1_CLK>,
<&gcc GCC_CAMSS_AXI_CLK>;
<&gcc GCC_CAMSS_TFE_1_CLK>;
clock-rates =
<256000000 256000000 150000000>,
<460800000 460800000 200000000>,
<576000000 576000000 300000000>;
<256000000 0>,
<460800000 0>,
<576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -723,23 +732,22 @@
"cphy_rx_clk_src",
"tfe_cphy_rx_clk",
"tfe_clk_src",
"tfe_clk",
"tfe_axi_clk";
"tfe_clk";
clocks =
<&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_2_CSID_CLK>,
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>,
<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_2_CLK>,
<&gcc GCC_CAMSS_AXI_CLK>;
<&gcc GCC_CAMSS_TFE_2_CLK>;
clock-rates =
<240000000 240000000 0 240000000 256000000 256000000 150000000>,
<384000000 384000000 0 341333333 460800000 460800000 200000000>,
<426400000 426400000 0 384000000 576000000 576000000 300000000>;
<240000000 0 240000000 0 256000000 0>,
<384000000 0 341333333 0 460800000 0>,
<426400000 0 384000000 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -755,19 +763,18 @@
camss-supply = <&gcc_camss_top_gdsc>;
clock-names =
"tfe_clk_src",
"tfe_clk",
"tfe_axi_clk";
"tfe_clk";
clocks =
<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_2_CLK>,
<&gcc GCC_CAMSS_AXI_CLK>;
<&gcc GCC_CAMSS_TFE_2_CLK>;
clock-rates =
<256000000 256000000 150000000>,
<460800000 460800000 200000000>,
<576000000 576000000 300000000>;
<256000000 0>,
<460800000 0>,
<576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -782,14 +789,16 @@
camss-supply = <&gcc_camss_top_gdsc>;
clock-names =
"cphy_rx_clk_src",
"tfe_0_cphy_rx_clk";
"tfe_0_cphy_rx_clk",
"gcc_camss_cphy_0_clk";
clocks =
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>;
<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
<&gcc GCC_CAMSS_CPHY_0_CLK>;
clock-rates =
<240000000 240000000>,
<341333333 341333333>,
<384000000 384000000>;
<240000000 0 0>,
<341333333 0 0>,
<384000000 0 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "cphy_rx_clk_src";
clock-control-debugfs = "false";
@@ -807,14 +816,16 @@
camss-supply = <&gcc_camss_top_gdsc>;
clock-names =
"cphy_rx_clk_src",
"tfe_1_cphy_rx_clk";
"tfe_1_cphy_rx_clk",
"gcc_camss_cphy_1_clk";
clocks =
<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
<&gcc GCC_CAMSS_CPHY_1_CLK>;
clock-rates =
<240000000 240000000>,
<341333333 341333333>,
<384000000 384000000>;
<240000000 0 0>,
<341333333 0 0>,
<384000000 0 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "cphy_rx_clk_src";
clock-control-debugfs = "false";
@@ -859,12 +870,13 @@
<&gcc GCC_CAMSS_OPE_CLK_SRC>,
<&gcc GCC_CAMSS_OPE_CLK>;
clock-rates =
<171428571 200000000 200000000>,
<171428571 266600000 266600000>,
<240000000 465000000 465000000>,
<240000000 580000000 580000000>;
<171428571 200000000 0>,
<171428571 266600000 0>,
<240000000 465000000 0>,
<240000000 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
src-clock-name = "ope_clk_src";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
};

25
arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-cpas.txt vendored
View File

@@ -67,9 +67,12 @@ First Level Node - CAM CPAS device
- cam_hw_fuse
Usage: optional
Value type: <u32>
Definition: List of fuse based features and respective
fuse info.
Value type: <u32:fuse_id> <u32:address> <u32:fuse_bit> <u32:fuse_type> <u32:hw_id>
fuse_id: fuse id for each features
address: fuse register io address
fuse_bit: fuse bit number in the fuse registers
fuse_type: fuse feature is enable type or disable type
hw_id: Hw id of the feature
- custom-id
Usage: optinal
@@ -133,6 +136,16 @@ First Level Node - CAM CPAS device
Definition: List of strings corresponds clock-rates levels.
Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo.
- qcom,cam-cx-ipeak
Usage: required
Value type: <u32>
Definition: Camera Cx Ipeak ID.
- qcom,cx-ipeak-gpu-limit;
Usage: required
Value type: <u32>
Definition: Camera Cx Ipeak GPU Limit.
- control-camnoc-axi-clk
Usage: optional
Value type: <empty>
@@ -294,8 +307,8 @@ Example:
reg = <0xac40000 0x1000>,
<0xac42000 0x5000>;
reg-cam-base = <0x40000 0x42000>;
cam_hw_fuse = <CAM_CPAS_QCFA_BINNING_ENABLE 0x00780210 29>,
<CAM_CPAS_SECURE_CAMERA_ENABLE 0x00780210 18>;
cam_hw_fuse = <CAM_CPAS_QCFA_BINNING_ENABLE 0x00780210 29 CAM_CPAS_FEATURE_TYPE_ENABLE 0>,
<CAM_CPAS_SECURE_CAMERA_ENABLE 0x00780210 18 CAM_CPAS_FEATURE_TYPE_ENABLE 0>;
interrupt-names = "cpas_camnoc";
interrupts = <0 459 0>;
qcom,cpas-hw-ver = <0x170100>; /* Titan v170 v1.0.0 */
@@ -316,6 +329,8 @@ Example:
src-clock-name = "slow_ahb_clk_src";
clock-rates = <0 0 0 0 80000000 0>;
clock-cntl-level = "turbo";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
qcom,cx-ipeak-gpu-limit = <650000000>;
control-camnoc-axi-clk;
camnoc-bus-width = <32>;
camnoc-axi-clk-bw-margin-perc = <10>;

2
arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-csiphy.txt vendored
View File

@@ -16,7 +16,7 @@ First Level Node - CSIPHY device
Definition: Should be "qcom,csiphy-v1.0",
"qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1",
"qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2",
"qcom,csiphy-v1.2.3", "qcom,csiphy".
"qcom,csiphy-v1.2.3", "qcom,csiphy-v2.0.1", "qcom,csiphy".
- cell-index: csiphy hardware core index
Usage: required

8
arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera-sensor-idp.dtsi vendored
View File

@@ -136,8 +136,8 @@
"cam_clk";
rgltr-cntrl-support;
pwm-switch;
rgltr-min-voltage = <1800000 2800000 1056000 0>;
rgltr-max-voltage = <1800000 2800000 1056000 0>;
rgltr-min-voltage = <1800000 2800000 1050000 0>;
rgltr-max-voltage = <1800000 2800000 1050000 0>;
rgltr-load-current = <0 80000 105000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
@@ -276,8 +276,8 @@
"cam_clk";
rgltr-cntrl-support;
pwm-switch;
rgltr-min-voltage = <1800000 2800000 1056000 0>;
rgltr-max-voltage = <1800000 2800000 1056000 0>;
rgltr-min-voltage = <1800000 2800000 1050000 0>;
rgltr-max-voltage = <1800000 2800000 1050000 0>;
rgltr-load-current = <0 80000 105000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";

42
arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera.dtsi vendored
View File

@@ -30,9 +30,10 @@
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
clock-rates =
<19200000 0 19200000 0>,
<341330000 0 200000000 0>,
<240000000 0 200000000 0>,
<341330000 0 200000000 0>,
<384000000 0 268800000 0>;
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -60,9 +61,10 @@
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
clock-rates =
<19200000 0 19200000 0>,
<341330000 0 200000000 0>,
<240000000 0 200000000 0>,
<341330000 0 200000000 0>,
<384000000 0 268800000 0>;
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -239,10 +241,9 @@
reg = <0x5c11000 0x1000>,
<0x5c13000 0x4000>;
reg-cam-base = <0x11000 0x13000>;
cam_hw_fuse = <CAM_CPAS_SECURE_CAMERA_ENABLE 0x01B401E4 8>;
interrupt-names = "cpas_camnoc";
interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
camnoc-axi-min-ib-bw = <3000000000>;
regulator-names = "camss-vdd";
camss-vdd-supply = <&gcc_camss_top_gdsc>;
clock-names =
@@ -272,6 +273,7 @@
<0 0 80000000 0 300000000 0 0>;
clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
control-camnoc-axi-clk;
camnoc-bus-width = <32>;
camnoc-axi-clk-bw-margin-perc = <20>;
@@ -284,28 +286,32 @@
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
RPMH_REGULATOR_LEVEL_MIN_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS_L1
RPMH_REGULATOR_LEVEL_LOW_SVS_L2
RPMH_REGULATOR_LEVEL_SVS
RPMH_REGULATOR_LEVEL_SVS_L0
RPMH_REGULATOR_LEVEL_SVS_L1
RPMH_REGULATOR_LEVEL_SVS_L2
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM_L1
RPMH_REGULATOR_LEVEL_NOM_L2
RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_TURBO_L1>;
vdd-corner-ahb-mapping = "suspend", "minsvs",
"lowsvs", "svs", "svs_l1",
"nominal", "nominal", "nominal",
vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs",
"lowsvs", "lowsvs", "svs", "svs_l1", "svs_l1",
"svs_l1", "nominal", "nominal", "nominal",
"turbo", "turbo";
client-id-based;
client-names =
@@ -538,8 +544,8 @@
compatible = "qcom,csid530";
reg-names = "csid", "top", "camnoc";
reg = <0x5c6e000 0x1000>,
<0x5c11000 0x1000>,
<0x5c13000 0x4000>;
<0x5c11000 0x1000>,
<0x5c13000 0x4000>;
reg-cam-base = <0x6e000 0x11000 0x13000>;
interrupt-names = "csid0";
interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
@@ -566,6 +572,7 @@
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -592,6 +599,7 @@
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -600,8 +608,8 @@
compatible = "qcom,csid530";
reg-names = "csid", "top", "camnoc";
reg = <0x5c75000 0x1000>,
<0x5c11000 0x1000>,
<0x5c13000 0x4000>;
<0x5c11000 0x1000>,
<0x5c13000 0x4000>;
reg-cam-base = <0x75000 0x11000 0x13000>;
interrupt-names = "csid1";
interrupts = <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
@@ -628,6 +636,7 @@
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -654,6 +663,7 @@
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
@@ -662,7 +672,7 @@
compatible = "qcom,tpgv1";
reg-names = "tpg0", "top";
reg = <0x5c66000 0x400>,
<0x5c11000 0x1000>;
<0x5c11000 0x1000>;
reg-cam-base = <0x66000 0x11000>;
regulator-names = "camss";
camss-supply = <&gcc_camss_top_gdsc>;
@@ -689,7 +699,7 @@
compatible = "qcom,tpgv1";
reg-names = "tpg0", "top";
reg = <0x5c68000 0x400>,
<0x5c11000 0x1000>;
<0x5c11000 0x1000>;
reg-cam-base = <0x68000 0x11000>;
regulator-names = "camss";
camss-supply = <&gcc_camss_top_gdsc>;
@@ -757,6 +767,8 @@
<240000000 0 580000000 0>;
clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
src-clock-name = "ope_clk_src";
clock-control-debugfs = "true";
qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
status = "ok";
};
};

116
arch/arm64/boot/dts/vendor/qcom/dsi-panel-arglass-seeya-dual-1080p-90hz-video.dtsi vendored Normal file
View File

@@ -0,0 +1,116 @@
&mdss_mdp {
dsi_dual_arglass_seeya_90hz_video: qcom,mdss_dsi_arglass_seeya_90hz_video {
qcom,mdss-dsi-panel-name =
"sy049wdm02 uoled video mode dsi seeya 90HZ panel with DSC";
qcom,mdss-dsi-panel-type = "dsi_video_mode";
qcom,dsi-ctrl-num = <0 1>;
qcom,dsi-phy-num = <0 1>;
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-bpp = <24>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
qcom,mdss-dsi-dma-trigger = "trigger_sw";
qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
qcom,adjust-timer-wakeup-ms = <1>;
qcom,mdss-dsi-panel-count = <2>;
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
17000 15500 30000 8000 3000>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-width = <1920>;
qcom,mdss-dsi-panel-height = <1080>;
qcom,mdss-dsi-h-front-porch = <32>;
qcom,mdss-dsi-h-back-porch = <32>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <14>;
qcom,mdss-dsi-v-front-porch = <16>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-panel-framerate = <90>;
qcom,mdss-dsi-on-command = [
//cmd1
39 01 00 00 00 00 02 53 29
39 01 00 00 00 00 03 51 FF 01
39 01 00 00 00 00 02 03 01
39 01 00 00 00 00 07 80 01 E0 E0 0E 00 31
39 01 00 00 00 00 08 81 03 04 00 10 00 10 00
39 01 00 00 00 00 08 82 03 04 00 10 00 10 01
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 02 26 20
//pps
39 01 00 00 00 00 11 70 00 00 00 89 20 80 04 38
07 80 00 1e 03 C0 03 C0
39 01 00 00 00 00 02 65 10
39 01 00 00 00 00 11 70 02 00 00 00 00 20 03 B4
00 0D 00 0C 03 50 01 E9
39 01 00 00 00 00 02 65 20
39 01 00 00 00 00 0D 70 18 00 10 F0 03 0C 20 00
06 0B 0B 33
// cmd2 p1
39 01 00 00 00 00 03 F0 AA 11
39 01 00 00 00 00 02 C0 00
39 01 00 00 00 00 09 C2 03 FF 03 FF 03 FF 03 FF
// cmd2 p2
39 01 00 00 00 00 03 F0 AA 12
39 01 00 00 00 00 03 BF 37 A9
/* H mirror dsi1 */
39 01 00 00 00 00 03 FF 5A 80
39 01 00 00 00 00 02 65 2F
39 01 00 00 00 00 02 F2 01
39 01 00 00 00 00 02 36 02
/* v mirror dsi0 */
39 01 00 04 00 00 03 FF 5A 80
39 01 00 04 00 00 02 65 2F
39 01 00 04 00 00 02 F2 01
39 01 00 04 00 00 02 36 01
39 01 00 04 00 00 03 F0 AA 13
39 01 00 04 00 00 02 65 01
39 01 00 04 00 00 02 C1 A2
39 01 00 04 00 00 07 C4 12 53 64 31 42 56
39 01 00 04 00 00 03 F0 AA 16
39 01 00 04 00 00 07 B6 12 53 64 31 42 56
39 01 00 04 00 00 03 B0 00 55
/* CMDs PP0 */
39 01 00 00 00 00 03 FF 5A 80
39 01 00 00 00 00 02 65 2F
39 01 00 00 00 00 02 F2 01
//cmd3 p1
39 01 00 00 00 00 03 FF 5A 81
39 01 00 00 00 00 02 65 05
39 01 00 00 00 00 02 F2 22
39 01 00 00 00 00 02 65 0A
39 01 00 00 00 00 02 F2 00
39 01 00 00 00 00 02 65 16
39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F
75 7B 80 86 8B 91
05 01 00 00 14 00 01 11
05 01 00 00 64 00 01 29
39 01 00 00 00 00 03 F0 AA 11
];
qcom,mdss-dsi-off-command = [05 01 00 00 0a 00
02 28 00 05 01 00 00 3c 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <30>;
qcom,mdss-dsc-slice-width = <960>;
qcom,mdss-dsc-slice-per-pkt = <1>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
};
};
};
};

2
arch/arm64/boot/dts/vendor/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi vendored
View File

@@ -1,7 +1,7 @@
&mdss_mdp {
dsi_dual_arglass_seeya_video: qcom,mdss_dsi_arglass_seeya_video {
qcom,mdss-dsi-panel-name =
"sy049wdm02 uoled video mode dsi seeya panel with DSC";
"sy049wdm02 uoled video mode dsi seeya 60Hz panel";
qcom,mdss-dsi-panel-type = "dsi_video_mode";
qcom,dsi-ctrl-num = <0 1>;
qcom,dsi-phy-num = <0 1>;

4
arch/arm64/boot/dts/vendor/qcom/khaje-pm7250b.dtsi vendored
View File

@@ -87,3 +87,7 @@
};
};
};
&pm7250b_pon {
qcom,log-kpd-event;
};

2
arch/arm64/boot/dts/vendor/qcom/khaje-sde.dtsi vendored
View File

@@ -25,7 +25,7 @@
"div_clk",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk", "rot_clk";
clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>;
clock-rate = <0 0 0 0 0 383000000 19200000 383000000 200000000>;
clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000
560000000>;

41
arch/arm64/boot/dts/vendor/qcom/khaje.dtsi vendored
View File

@@ -3969,12 +3969,21 @@ tpdm_turing_llm: tpdm@8861000 {
qcom,speed-bin = <0>;
qcom,initial-pwrlevel = <5>;
qcom,ca-target-pwrlevel = <4>;
qcom,initial-pwrlevel = <6>;
qcom,ca-target-pwrlevel = <5>;
/* TURBO_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1260000000>;
qcom,bus-freq = <7>;
qcom,bus-min = <7>;
qcom,bus-max = <7>;
};
/* TURBO_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1114800000>;
qcom,bus-freq = <7>;
qcom,bus-min = <7>;
@@ -3982,8 +3991,8 @@ tpdm_turing_llm: tpdm@8861000 {
};
/* TURBO */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <1025000000>;
qcom,bus-freq = <6>;
qcom,bus-min = <5>;
@@ -3991,8 +4000,8 @@ tpdm_turing_llm: tpdm@8861000 {
};
/* NOM */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <785000000>;
qcom,bus-freq = <5>;
qcom,bus-min = <4>;
@@ -4000,8 +4009,8 @@ tpdm_turing_llm: tpdm@8861000 {
};
/* SVS_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <600000000>;
qcom,bus-freq = <4>;
qcom,bus-min = <3>;
@@ -4009,8 +4018,8 @@ tpdm_turing_llm: tpdm@8861000 {
};
/* SVS */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <465000000>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
@@ -4018,8 +4027,8 @@ tpdm_turing_llm: tpdm@8861000 {
};
/* LOW SVS */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <320000000>;
qcom,bus-freq = <2>;
qcom,bus-min = <1>;
@@ -4027,8 +4036,8 @@ tpdm_turing_llm: tpdm@8861000 {
};
/* XO */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <0>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
@@ -4180,6 +4189,10 @@ tpdm_turing_llm: tpdm@8861000 {
#include "pm8008.dtsi"
};
&pm8008_regulators {
/delete-property/ qcom,enable-ocp-broadcast;
};
&pm8008_8 {
/* PM8008 IRQ STAT */
interrupt-parent = <&tlmm>;

14
arch/arm64/boot/dts/vendor/qcom/khajep-atp-overlay.dts vendored Normal file
View File

@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep ATP";
compatible = "qcom,khajep-atp", "qcom,khajep", "qcom,atp";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <33 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

12
arch/arm64/boot/dts/vendor/qcom/khajep-atp.dts vendored Normal file
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@@ -0,0 +1,12 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep ATP";
compatible = "qcom,khajep-atp", "qcom,khajep", "qcom,atp";
qcom,board-id = <33 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-atp.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-atp.dtsi"

13
arch/arm64/boot/dts/vendor/qcom/khajep-idp-nopmi-overlay.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-idp-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDP nopmi";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

11
arch/arm64/boot/dts/vendor/qcom/khajep-idp-nopmi.dts vendored Normal file
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@@ -0,0 +1,11 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-idp-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDP nopmi";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-idp-nopmi.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-idp-nopmi.dtsi"

14
arch/arm64/boot/dts/vendor/qcom/khajep-idp-overlay.dts vendored Normal file
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@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khaje IDP";
compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

15
arch/arm64/boot/dts/vendor/qcom/khajep-idp-pm8010-overlay.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-idp.dtsi"
#include "khajep-idp-pm8010.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep IDP with PM8010";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x10222 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajep-idp-pm8010.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-idp.dtsi"
#include "khajep-idp-pm8010.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDP with PM8010";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,board-id = <0x10222 0>;
qcom,pmic-id = <0x02D 0x2E 0x0 0x0>;
};

4
arch/arm64/boot/dts/vendor/qcom/khajep-idp-pm8010.dtsi vendored Normal file
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@@ -0,0 +1,4 @@
#include "khaje-idp-pm8010.dtsi"
&soc {
};

16
arch/arm64/boot/dts/vendor/qcom/khajep-idp-usbc-overlay.dts vendored Normal file
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@@ -0,0 +1,16 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajep-idp-usbc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDP USBC Audio";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x1010022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

15
arch/arm64/boot/dts/vendor/qcom/khajep-idp-usbc.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajep-idp-usbc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDP USBC Audio";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x1010022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-idp-usbc.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-idp-usbc.dtsi"

12
arch/arm64/boot/dts/vendor/qcom/khajep-idp.dts vendored Normal file
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@@ -0,0 +1,12 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDP";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-idp.dtsi vendored Normal file
View File

@@ -0,0 +1 @@
#include "khaje-idp.dtsi"

15
arch/arm64/boot/dts/vendor/qcom/khajep-idps-display-90hz-overlay.dts vendored Normal file
View File

@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajep-idps-display-90hz.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDPS + 90Hz";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x10122 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajep-idps-display-90hz.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajep-idps-display-90hz.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP IDPS + 90Hz";
compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp";
qcom,board-id = <0x10122 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-idps-display-90hz.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-idps-display-90hz.dtsi"

15
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-hvdcp3p5-overlay.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khaje-qrd-hvdcp3p5.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep QRD HVDCP3P5";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x1010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-hvdcp3p5.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khajep-qrd-hvdcp3p5.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP QRD HVDCP3P5";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,board-id = <0x1010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-hvdcp3p5.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-qrd-hvdcp3p5.dtsi"

13
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-nopmi-overlay.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-qrd-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP QRD nopmi overlay";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x1000B 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

11
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-nopmi.dts vendored Normal file
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@@ -0,0 +1,11 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-qrd-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP QRD nopmi";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-nopmi.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-qrd-nopmi.dtsi"

15
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-nowcd9375-overlay.dts vendored Normal file
View File

@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khajep-qrd-nowcd9375.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep QRD NOWCD9375";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x2010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-nowcd9375.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khajep-qrd-nowcd9375.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEP QRD NOWCD9375";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,board-id = <0x2010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-nowcd9375.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-qrd-nowcd9375.dtsi"

18
arch/arm64/boot/dts/vendor/qcom/khajep-qrd-overlay.dts vendored Normal file
View File

@@ -0,0 +1,18 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajep-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep QRD";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,msm-id = <561 0x10000>;
qcom,board-id = <0x1000B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};
&bengal_snd {
qcom,wcd-datalane-mismatch = <1>;
};

11
arch/arm64/boot/dts/vendor/qcom/khajep-qrd.dts vendored Normal file
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@@ -0,0 +1,11 @@
/dts-v1/;
#include "khajep.dtsi"
#include "khajep-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep QRD";
compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
};

3
arch/arm64/boot/dts/vendor/qcom/khajep-qrd.dtsi vendored Normal file
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@@ -0,0 +1,3 @@
#include "khaje-qrd.dtsi"
&soc {
};

9
arch/arm64/boot/dts/vendor/qcom/khajep.dts vendored Normal file
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@@ -0,0 +1,9 @@
/dts-v1/;
#include "khajep.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep SoC";
compatible = "qcom,khajep";
qcom,board-id = <0 0>;
};

22
arch/arm64/boot/dts/vendor/qcom/khajep.dtsi vendored Normal file
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@@ -0,0 +1,22 @@
/dts-v1/;
#include "khaje.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajep SoC";
compatible = "qcom,khajep";
qcom,msm-id = <561 0x10000>;
};
&soc {
qcom,rmnet-ipa {
status = "disabled";
};
};
&ipa_hw {
status = "disabled";
};

14
arch/arm64/boot/dts/vendor/qcom/khajeq-atp-overlay.dts vendored Normal file
View File

@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajeq ATP";
compatible = "qcom,khajeq-atp", "qcom,khajeq", "qcom,atp";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <33 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

12
arch/arm64/boot/dts/vendor/qcom/khajeq-atp.dts vendored Normal file
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@@ -0,0 +1,12 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajeq ATP";
compatible = "qcom,khajeq-atp", "qcom,khajeq", "qcom,atp";
qcom,board-id = <33 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-atp.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-atp.dtsi"

13
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-nopmi-overlay.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-idp-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDP nopmi";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

11
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-nopmi.dts vendored Normal file
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@@ -0,0 +1,11 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-idp-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDP nopmi";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-nopmi.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-idp-nopmi.dtsi"

14
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-overlay.dts vendored Normal file
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@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khaje IDP";
compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

15
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-pm8010-overlay.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-idp.dtsi"
#include "khajeq-idp-pm8010.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajeq IDP with PM8010";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x10222 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-pm8010.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-idp.dtsi"
#include "khajeq-idp-pm8010.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDP with PM8010";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,board-id = <0x10222 0>;
qcom,pmic-id = <0x02D 0x2E 0x0 0x0>;
};

5
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-pm8010.dtsi vendored Normal file
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@@ -0,0 +1,5 @@
#include "khaje-idp-pm8010.dtsi"
&soc {
};

16
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-usbc-overlay.dts vendored Normal file
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@@ -0,0 +1,16 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajeq-idp-usbc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDP USBC Audio";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x1010022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

15
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-usbc.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajeq-idp-usbc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDP USBC Audio";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x1010022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-idp-usbc.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-idp-usbc.dtsi"

12
arch/arm64/boot/dts/vendor/qcom/khajeq-idp.dts vendored Normal file
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@@ -0,0 +1,12 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDP";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,board-id = <0x10022 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-idp.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-idp.dtsi"

15
arch/arm64/boot/dts/vendor/qcom/khajeq-idps-display-90hz-overlay.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajeq-idps-display-90hz.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDPS + 90Hz";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x10122 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajeq-idps-display-90hz.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-idp.dtsi"
#include "khaje-idp-pm7250b.dtsi"
#include "khajeq-idps-display-90hz.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ IDPS + 90Hz";
compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp";
qcom,board-id = <0x10122 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-idps-display-90hz.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-idps-display-90hz.dtsi"

15
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-hvdcp3p5-overlay.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khajeq-qrd-hvdcp3p5.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajeq QRD HVDCP3P5";
compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x1010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-hvdcp3p5.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khajeq-qrd-hvdcp3p5.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ QRD HVDCP3P5";
compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd";
qcom,board-id = <0x1010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-hvdcp3p5.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-qrd-hvdcp3p5.dtsi"

13
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-nopmi-overlay.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-qrd-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ QRD nopmi overlay";
compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x1000B 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

11
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-nopmi.dts vendored Normal file
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@@ -0,0 +1,11 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-qrd-nopmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ QRD nopmi";
compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-nopmi.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-qrd-nopmi.dtsi"

15
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-nowcd9375-overlay.dts vendored Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "khajeq-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khajeq-qrd-nowcd9375.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Khajeq QRD NOWCD9375";
compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd";
qcom,msm-id = <562 0x10000>;
qcom,board-id = <0x2010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

13
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-nowcd9375.dts vendored Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
#include "khajeq.dtsi"
#include "khajeq-qrd.dtsi"
#include "khaje-qrd-pm7250b.dtsi"
#include "khajeq-qrd-nowcd9375.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KHAJEQ QRD NOWCD9375";
compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd";
qcom,board-id = <0x2010B 0>;
qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
};

1
arch/arm64/boot/dts/vendor/qcom/khajeq-qrd-nowcd9375.dtsi vendored Normal file
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@@ -0,0 +1 @@
#include "khaje-qrd-nowcd9375.dtsi"

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