927d042434
When we call crypto_qti_program_key to program the key, and it fails due to trustzone busy issue, we try to call invalidate key method just after that, and in the process, overwrite the error code returned by the program key failure. Fix this by handling the errors from both program key and invalidate key separately, and return the program key error code to caller. Test: Verified device boot up and reboot. Change-Id: Iaff0844f68b4886c23e1840d7e0e4a404d38fc96 Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
472 lines
13 KiB
C
472 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/crypto-qti-common.h>
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#include "crypto-qti-ice-regs.h"
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#include "crypto-qti-platform.h"
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static int ice_check_fuse_setting(struct crypto_vops_qti_entry *ice_entry)
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{
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uint32_t regval;
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uint32_t major, minor;
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major = (ice_entry->ice_hw_version & ICE_CORE_MAJOR_REV_MASK) >>
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ICE_CORE_MAJOR_REV;
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minor = (ice_entry->ice_hw_version & ICE_CORE_MINOR_REV_MASK) >>
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ICE_CORE_MINOR_REV;
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//Check fuse setting is not supported on ICE 3.2 onwards
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if ((major == 0x03) && (minor >= 0x02))
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return 0;
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regval = ice_readl(ice_entry, ICE_REGS_FUSE_SETTING);
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regval &= (ICE_FUSE_SETTING_MASK |
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ICE_FORCE_HW_KEY0_SETTING_MASK |
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ICE_FORCE_HW_KEY1_SETTING_MASK);
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if (regval) {
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pr_err("%s: error: ICE_ERROR_HW_DISABLE_FUSE_BLOWN\n",
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__func__);
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return -EPERM;
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}
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return 0;
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}
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static int ice_check_version(struct crypto_vops_qti_entry *ice_entry)
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{
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uint32_t version, major, minor, step;
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version = ice_readl(ice_entry, ICE_REGS_VERSION);
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major = (version & ICE_CORE_MAJOR_REV_MASK) >> ICE_CORE_MAJOR_REV;
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minor = (version & ICE_CORE_MINOR_REV_MASK) >> ICE_CORE_MINOR_REV;
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step = (version & ICE_CORE_STEP_REV_MASK) >> ICE_CORE_STEP_REV;
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if (major < ICE_CORE_CURRENT_MAJOR_VERSION) {
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pr_err("%s: Unknown ICE device at %lu, rev %d.%d.%d\n",
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__func__, (unsigned long)ice_entry->icemmio_base,
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major, minor, step);
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return -ENODEV;
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}
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ice_entry->ice_hw_version = version;
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return 0;
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}
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int crypto_qti_init_crypto(struct device *dev, void __iomem *mmio_base,
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void **priv_data)
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{
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int err = 0;
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struct crypto_vops_qti_entry *ice_entry;
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ice_entry = devm_kzalloc(dev,
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sizeof(struct crypto_vops_qti_entry),
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GFP_KERNEL);
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if (!ice_entry)
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return -ENOMEM;
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ice_entry->icemmio_base = mmio_base;
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ice_entry->flags = 0;
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err = ice_check_version(ice_entry);
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if (err) {
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pr_err("%s: check version failed, err %d\n", __func__, err);
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return err;
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}
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err = ice_check_fuse_setting(ice_entry);
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if (err)
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return err;
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*priv_data = (void *)ice_entry;
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return err;
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}
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static void ice_low_power_and_optimization_enable(
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struct crypto_vops_qti_entry *ice_entry)
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{
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uint32_t regval;
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regval = ice_readl(ice_entry, ICE_REGS_ADVANCED_CONTROL);
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/* Enable low power mode sequence
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* [0]-0,[1]-0,[2]-0,[3]-7,[4]-0,[5]-0,[6]-0,[7]-0,
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* Enable CONFIG_CLK_GATING, STREAM2_CLK_GATING and STREAM1_CLK_GATING
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*/
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regval |= 0x7000;
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/* Optimization enable sequence
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*/
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regval |= 0xD807100;
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ice_writel(ice_entry, regval, ICE_REGS_ADVANCED_CONTROL);
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/*
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* Memory barrier - to ensure write completion before next transaction
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*/
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wmb();
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}
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static int ice_wait_bist_status(struct crypto_vops_qti_entry *ice_entry)
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{
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int count;
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uint32_t regval;
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for (count = 0; count < QTI_ICE_MAX_BIST_CHECK_COUNT; count++) {
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regval = ice_readl(ice_entry, ICE_REGS_BIST_STATUS);
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if (!(regval & ICE_BIST_STATUS_MASK))
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break;
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udelay(50);
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}
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if (regval) {
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pr_err("%s: wait bist status failed, reg %d\n",
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__func__, regval);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void ice_enable_intr(struct crypto_vops_qti_entry *ice_entry)
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{
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uint32_t regval;
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regval = ice_readl(ice_entry, ICE_REGS_NON_SEC_IRQ_MASK);
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regval &= ~ICE_REGS_NON_SEC_IRQ_MASK;
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ice_writel(ice_entry, regval, ICE_REGS_NON_SEC_IRQ_MASK);
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/*
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* Memory barrier - to ensure write completion before next transaction
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*/
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wmb();
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}
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static void ice_disable_intr(struct crypto_vops_qti_entry *ice_entry)
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{
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uint32_t regval;
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regval = ice_readl(ice_entry, ICE_REGS_NON_SEC_IRQ_MASK);
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regval |= ICE_REGS_NON_SEC_IRQ_MASK;
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ice_writel(ice_entry, regval, ICE_REGS_NON_SEC_IRQ_MASK);
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/*
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* Memory barrier - to ensure write completion before next transaction
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*/
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wmb();
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}
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int crypto_qti_enable(void *priv_data)
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{
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int err = 0;
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struct crypto_vops_qti_entry *ice_entry;
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ice_entry = (struct crypto_vops_qti_entry *) priv_data;
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if (!ice_entry) {
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pr_err("%s: vops ice data is invalid\n", __func__);
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return -EINVAL;
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}
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ice_low_power_and_optimization_enable(ice_entry);
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err = ice_wait_bist_status(ice_entry);
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if (err)
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return err;
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ice_enable_intr(ice_entry);
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return err;
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}
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void crypto_qti_disable(void *priv_data)
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{
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struct crypto_vops_qti_entry *ice_entry;
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ice_entry = (struct crypto_vops_qti_entry *) priv_data;
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if (!ice_entry) {
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pr_err("%s: vops ice data is invalid\n", __func__);
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return;
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}
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crypto_qti_disable_platform(ice_entry);
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ice_disable_intr(ice_entry);
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}
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int crypto_qti_resume(void *priv_data)
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{
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int err = 0;
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struct crypto_vops_qti_entry *ice_entry;
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ice_entry = (struct crypto_vops_qti_entry *) priv_data;
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if (!ice_entry) {
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pr_err("%s: vops ice data is invalid\n", __func__);
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return -EINVAL;
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}
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err = ice_wait_bist_status(ice_entry);
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return err;
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}
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static void ice_dump_test_bus(struct crypto_vops_qti_entry *ice_entry)
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{
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uint32_t regval = 0x1;
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uint32_t val;
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uint8_t bus_selector;
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uint8_t stream_selector;
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pr_err("ICE TEST BUS DUMP:\n");
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for (bus_selector = 0; bus_selector <= 0xF; bus_selector++) {
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regval = 0x1; /* enable test bus */
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regval |= bus_selector << 28;
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if (bus_selector == 0xD)
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continue;
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ice_writel(ice_entry, regval, ICE_REGS_TEST_BUS_CONTROL);
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/*
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* make sure test bus selector is written before reading
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* the test bus register
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*/
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wmb();
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val = ice_readl(ice_entry, ICE_REGS_TEST_BUS_REG);
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pr_err("ICE_TEST_BUS_CONTROL: 0x%08x | ICE_TEST_BUS_REG: 0x%08x\n",
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regval, val);
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}
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pr_err("ICE TEST BUS DUMP (ICE_STREAM1_DATAPATH_TEST_BUS):\n");
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for (stream_selector = 0; stream_selector <= 0xF; stream_selector++) {
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regval = 0xD0000001; /* enable stream test bus */
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regval |= stream_selector << 16;
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ice_writel(ice_entry, regval, ICE_REGS_TEST_BUS_CONTROL);
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/*
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* make sure test bus selector is written before reading
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* the test bus register
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*/
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wmb();
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val = ice_readl(ice_entry, ICE_REGS_TEST_BUS_REG);
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pr_err("ICE_TEST_BUS_CONTROL: 0x%08x | ICE_TEST_BUS_REG: 0x%08x\n",
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regval, val);
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}
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}
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int crypto_qti_debug(void *priv_data)
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{
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struct crypto_vops_qti_entry *ice_entry;
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ice_entry = (struct crypto_vops_qti_entry *) priv_data;
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if (!ice_entry) {
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pr_err("%s: vops ice data is invalid\n", __func__);
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return -EINVAL;
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}
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pr_err("%s: ICE Control: 0x%08x | ICE Reset: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_CONTROL),
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ice_readl(ice_entry, ICE_REGS_RESET));
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pr_err("%s: ICE Version: 0x%08x | ICE FUSE: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_VERSION),
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ice_readl(ice_entry, ICE_REGS_FUSE_SETTING));
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pr_err("%s: ICE Param1: 0x%08x | ICE Param2: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_PARAMETERS_1),
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ice_readl(ice_entry, ICE_REGS_PARAMETERS_2));
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pr_err("%s: ICE Param3: 0x%08x | ICE Param4: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_PARAMETERS_3),
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ice_readl(ice_entry, ICE_REGS_PARAMETERS_4));
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pr_err("%s: ICE Param5: 0x%08x | ICE IRQ STTS: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_PARAMETERS_5),
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ice_readl(ice_entry, ICE_REGS_NON_SEC_IRQ_STTS));
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pr_err("%s: ICE IRQ MASK: 0x%08x | ICE IRQ CLR: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_NON_SEC_IRQ_MASK),
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ice_readl(ice_entry, ICE_REGS_NON_SEC_IRQ_CLR));
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pr_err("%s: ICE INVALID CCFG ERR STTS: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_INVALID_CCFG_ERR_STTS));
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pr_err("%s: ICE BIST Sts: 0x%08x | ICE Bypass Sts: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_BIST_STATUS),
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ice_readl(ice_entry, ICE_REGS_BYPASS_STATUS));
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pr_err("%s: ICE ADV CTRL: 0x%08x | ICE ENDIAN SWAP: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_ADVANCED_CONTROL),
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ice_readl(ice_entry, ICE_REGS_ENDIAN_SWAP));
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pr_err("%s: ICE_STM1_ERR_SYND1: 0x%08x | ICE_STM1_ERR_SYND2: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_ERROR_SYNDROME1),
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ice_readl(ice_entry, ICE_REGS_STREAM1_ERROR_SYNDROME2));
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pr_err("%s: ICE_STM2_ERR_SYND1: 0x%08x | ICE_STM2_ERR_SYND2: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_ERROR_SYNDROME1),
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ice_readl(ice_entry, ICE_REGS_STREAM2_ERROR_SYNDROME2));
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pr_err("%s: ICE_STM1_COUNTER1: 0x%08x | ICE_STM1_COUNTER2: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS1),
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS2));
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pr_err("%s: ICE_STM1_COUNTER3: 0x%08x | ICE_STM1_COUNTER4: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS3),
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS4));
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pr_err("%s: ICE_STM2_COUNTER1: 0x%08x | ICE_STM2_COUNTER2: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS1),
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS2));
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pr_err("%s: ICE_STM2_COUNTER3: 0x%08x | ICE_STM2_COUNTER4: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS3),
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS4));
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pr_err("%s: ICE_STM1_CTR5_MSB: 0x%08x | ICE_STM1_CTR5_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS5_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS5_LSB));
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pr_err("%s: ICE_STM1_CTR6_MSB: 0x%08x | ICE_STM1_CTR6_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS6_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS6_LSB));
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pr_err("%s: ICE_STM1_CTR7_MSB: 0x%08x | ICE_STM1_CTR7_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS7_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS7_LSB));
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pr_err("%s: ICE_STM1_CTR8_MSB: 0x%08x | ICE_STM1_CTR8_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS8_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS8_LSB));
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pr_err("%s: ICE_STM1_CTR9_MSB: 0x%08x | ICE_STM1_CTR9_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS9_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM1_COUNTERS9_LSB));
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pr_err("%s: ICE_STM2_CTR5_MSB: 0x%08x | ICE_STM2_CTR5_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS5_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS5_LSB));
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pr_err("%s: ICE_STM2_CTR6_MSB: 0x%08x | ICE_STM2_CTR6_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS6_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS6_LSB));
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pr_err("%s: ICE_STM2_CTR7_MSB: 0x%08x | ICE_STM2_CTR7_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS7_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS7_LSB));
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pr_err("%s: ICE_STM2_CTR8_MSB: 0x%08x | ICE_STM2_CTR8_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS8_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS8_LSB));
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pr_err("%s: ICE_STM2_CTR9_MSB: 0x%08x | ICE_STM2_CTR9_LSB: 0x%08x\n",
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ice_entry->ice_dev_type,
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS9_MSB),
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ice_readl(ice_entry, ICE_REGS_STREAM2_COUNTERS9_LSB));
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ice_dump_test_bus(ice_entry);
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return 0;
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}
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int crypto_qti_keyslot_program(void *priv_data,
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const struct blk_crypto_key *key,
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unsigned int slot,
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u8 data_unit_mask, int capid)
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{
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int err1 = 0, err2 = 0;
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struct crypto_vops_qti_entry *ice_entry;
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ice_entry = (struct crypto_vops_qti_entry *) priv_data;
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if (!ice_entry) {
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pr_err("%s: vops ice data is invalid\n", __func__);
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return -EINVAL;
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}
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err1 = crypto_qti_program_key(ice_entry, key, slot,
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data_unit_mask, capid);
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if (err1) {
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pr_err("%s: program key failed with error %d\n",
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__func__, err1);
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err2 = crypto_qti_invalidate_key(ice_entry, slot);
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if (err2) {
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pr_err("%s: invalidate key failed with error %d\n",
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__func__, err2);
|
|
}
|
|
}
|
|
|
|
return err1;
|
|
}
|
|
|
|
int crypto_qti_keyslot_evict(void *priv_data, unsigned int slot)
|
|
{
|
|
int err = 0;
|
|
struct crypto_vops_qti_entry *ice_entry;
|
|
|
|
ice_entry = (struct crypto_vops_qti_entry *) priv_data;
|
|
if (!ice_entry) {
|
|
pr_err("%s: vops ice data is invalid\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = crypto_qti_invalidate_key(ice_entry, slot);
|
|
if (err) {
|
|
pr_err("%s: invalidate key failed with error %d\n",
|
|
__func__, err);
|
|
return err;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
int crypto_qti_derive_raw_secret(const u8 *wrapped_key,
|
|
unsigned int wrapped_key_size, u8 *secret,
|
|
unsigned int secret_size)
|
|
{
|
|
int err = 0;
|
|
|
|
if (wrapped_key_size <= RAW_SECRET_SIZE) {
|
|
pr_err("%s: Invalid wrapped_key_size: %u\n",
|
|
__func__, wrapped_key_size);
|
|
err = -EINVAL;
|
|
return err;
|
|
}
|
|
if (secret_size != RAW_SECRET_SIZE) {
|
|
pr_err("%s: Invalid secret size: %u\n", __func__, secret_size);
|
|
err = -EINVAL;
|
|
return err;
|
|
}
|
|
|
|
if (wrapped_key_size > 64)
|
|
err = crypto_qti_tz_raw_secret(wrapped_key, wrapped_key_size,
|
|
secret, secret_size);
|
|
else
|
|
memcpy(secret, wrapped_key, secret_size);
|
|
|
|
return err;
|
|
}
|