236f749edb
[ Upstream commit adeec61a4723fd3e39da68db4cc4d924e6d7f641 ]
A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS
special-purpose register does not affect subsequent speculative
instructions, permitting speculative store bypassing for a window of
time.
We worked around this for a number of CPUs in commits:
* 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417")
* 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround")
Since then, similar errata have been published for a number of other Arm
Ltd CPUs, for which the same mitigation is sufficient. This is described
in their respective Software Developer Errata Notice (SDEN) documents:
* Cortex-A76 (MP052) SDEN v31.0, erratum 3324349
https://developer.arm.com/documentation/SDEN-885749/3100/
* Cortex-A77 (MP074) SDEN v19.0, erratum 3324348
https://developer.arm.com/documentation/SDEN-1152370/1900/
* Cortex-A78 (MP102) SDEN v21.0, erratum 3324344
https://developer.arm.com/documentation/SDEN-1401784/2100/
* Cortex-A78C (MP138) SDEN v16.0, erratum 3324346
https://developer.arm.com/documentation/SDEN-1707916/1600/
* Cortex-A78C (MP154) SDEN v10.0, erratum 3324347
https://developer.arm.com/documentation/SDEN-2004089/1000/
* Cortex-A725 (MP190) SDEN v5.0, erratum 3456106
https://developer.arm.com/documentation/SDEN-2832921/0500/
* Cortex-X1 (MP077) SDEN v21.0, erratum 3324344
https://developer.arm.com/documentation/SDEN-1401782/2100/
* Cortex-X1C (MP136) SDEN v16.0, erratum 3324346
https://developer.arm.com/documentation/SDEN-1707914/1600/
* Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349
https://developer.arm.com/documentation/SDEN-885747/3200/
* Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341
https://developer.arm.com/documentation/SDEN-1401781/1900/
Note that due to the manner in which Arm develops IP and tracks errata,
some CPUs share a common erratum number and some CPUs have multiple
erratum numbers for the same HW issue.
On parts without SB, it is necessary to use ISB for the workaround. The
spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB"
sequence in this case, which is sufficient on all affected parts.
Enable the existing mitigation by adding the relevant MIDRs to
erratum_spec_ssbs_list. The list is sorted alphanumerically (involving
moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and
potentially extend again in future. The Kconfig text is also updated to
clarify the set of affected parts and the mitigation.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20240801101803.1982459-4-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
[ Mark: fix conflicts in silicon-errata.rst ]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
104 lines
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104 lines
7.0 KiB
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Silicon Errata and Software Workarounds
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=======================================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 27 November 2015
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It is an unfortunate fact of life that hardware is often produced with
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so-called "errata", which can cause it to deviate from the architecture
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under specific circumstances. For hardware produced by ARM, these
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errata are broadly classified into the following categories:
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Category A: A critical error without a viable workaround.
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Category B: A significant or critical error with an acceptable
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workaround.
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Category C: A minor error that is not expected to occur under normal
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operation.
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For more information, consult one of the "Software Developers Errata
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Notice" documents available on infocenter.arm.com (registration
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required).
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As far as Linux is concerned, Category B errata may require some special
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treatment in the operating system. For example, avoiding a particular
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sequence of code, or configuring the processor in a particular way. A
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less common situation may require similar actions in order to declassify
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a Category A erratum into a Category C erratum. These are collectively
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known as "software workarounds" and are only required in the minority of
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cases (e.g. those cases that both require a non-secure workaround *and*
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can be triggered by Linux).
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For software workarounds that may adversely impact systems unaffected by
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the erratum in question, a Kconfig entry is added under "Kernel
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Features" -> "ARM errata workarounds via the alternatives framework".
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These are enabled by default and patched in at runtime when an affected
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CPU is detected. For less-intrusive workarounds, a Kconfig option is not
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available and the code is structured (preferably with a comment) in such
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a way that the erratum will not be hit.
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This approach can make it slightly onerous to determine exactly which
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errata are worked around in an arbitrary kernel source tree, so this
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file acts as a registry of software workarounds in the Linux Kernel and
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will be updated when new workarounds are committed and backported to
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stable kernels.
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| Implementor | Component | Erratum ID | Kconfig |
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+----------------+-----------------+-----------------+-----------------------------+
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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
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| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
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| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
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| ARM | Cortex-A57 | #852523 | N/A |
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| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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| ARM | Cortex-A57 | #1742098 | ARM64_ERRATUM_1742098 |
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| ARM | Cortex-A72 | #853709 | N/A |
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| ARM | Cortex-A72 | #1655431 | ARM64_ERRATUM_1742098 |
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
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| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 |
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| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 |
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
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| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
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| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
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| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
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| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
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| ARM | MMU-500 | #841119,#826419 | N/A |
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| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
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| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
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| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |
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| Cavium | ThunderX SMMUv2 | #27704 | N/A |
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| Cavium | ThunderX2 SMMUv3| #74 | N/A |
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| Cavium | ThunderX2 SMMUv3| #126 | N/A |
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| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
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| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
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| Hisilicon | Hip0{6,7} | #161010701 | N/A |
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| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
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| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
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| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
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| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
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| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
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