Files
kernel_xiaomi_sm8250/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
Marco Franchi 48c926cd34 dt-bindings: Remove leading zeros from bindings notation
Improve the binding example by removing all the leading zeros to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading 0s

Converted using the following command:

perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"`

Some unnecessary changes were manually fixed.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-11-09 17:05:05 -06:00

55 lines
1.6 KiB
Plaintext

Etnaviv DRM master device
=========================
The Etnaviv DRM master device is a virtual device needed to list all
Vivante GPU cores that comprise the GPU subsystem.
Required properties:
- compatible: Should be one of
"fsl,imx-gpu-subsystem"
"marvell,dove-gpu-subsystem"
- cores: Should contain a list of phandles pointing to Vivante GPU devices
example:
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
};
Vivante GPU core devices
========================
Required properties:
- compatible: Should be "vivante,gc"
A more specific compatible is not needed, as the cores contain chip
identification registers at fixed locations, which provide all the
necessary information to the driver.
- reg: should be register base and length as documented in the
datasheet
- interrupts: Should contain the cores interrupt line
- clocks: should contain one clock for entry in clock-names
see Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names:
- "bus": AXI/register clock
- "core": GPU core clock
- "shader": Shader clock (only required if GPU has feature PIPE_3D)
Optional properties:
- power-domains: a power domain consumer specifier according to
Documentation/devicetree/bindings/power/power_domain.txt
example:
gpu_3d: gpu@130000 {
compatible = "vivante,gc";
reg = <0x00130000 0x4000>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
power-domains = <&gpc 1>;
};