213c4e99fc
git-subtree-dir: techpack/video git-subtree-mainline:078c8b4302git-subtree-split:563c068743Change-Id: I03aafbfd2c133ff9cd1475c96f3bed969f7bb5be
61 lines
2.1 KiB
C
61 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#include "hfi_common.h"
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#include "hfi_io_common.h"
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void __interrupt_init_iris1(struct venus_hfi_device *device, u32 sid)
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{
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u32 mask_val = 0;
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/* All interrupts should be disabled initially 0x1F6 : Reset value */
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mask_val = __read_register(device, WRAPPER_INTR_MASK, sid);
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/* Write 0 to unmask CPU and WD interrupts */
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mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BMSK |
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WRAPPER_INTR_MASK_A2HCPU_BMSK);
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__write_register(device, WRAPPER_INTR_MASK, mask_val, sid);
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}
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void __setup_ucregion_memory_map_iris1(struct venus_hfi_device *device, u32 sid)
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{
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/* initialize CPU QTBL & UCREGION */
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__write_register(device, UC_REGION_ADDR,
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(u32)device->iface_q_table.align_device_addr, sid);
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__write_register(device, UC_REGION_SIZE, SHARED_QSIZE, sid);
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__write_register(device, QTBL_ADDR,
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(u32)device->iface_q_table.align_device_addr, sid);
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__write_register(device, QTBL_INFO, 0x01, sid);
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if (device->sfr.align_device_addr)
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__write_register(device, SFR_ADDR,
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(u32)device->sfr.align_device_addr, sid);
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if (device->qdss.align_device_addr)
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__write_register(device, MMAP_ADDR,
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(u32)device->qdss.align_device_addr, sid);
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/* initialize DSP QTBL & UCREGION with CPU queues by default */
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__write_register(device, HFI_DSP_QTBL_ADDR,
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(u32)device->iface_q_table.align_device_addr, sid);
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__write_register(device, HFI_DSP_UC_REGION_ADDR,
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(u32)device->iface_q_table.align_device_addr, sid);
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__write_register(device, HFI_DSP_UC_REGION_SIZE, SHARED_QSIZE, sid);
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if (device->res->cvp_internal) {
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/* initialize DSP QTBL & UCREGION with DSP queues */
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__write_register(device, HFI_DSP_QTBL_ADDR,
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(u32)device->dsp_iface_q_table.align_device_addr, sid);
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__write_register(device, HFI_DSP_UC_REGION_ADDR,
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(u32)device->dsp_iface_q_table.align_device_addr, sid);
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__write_register(device, HFI_DSP_UC_REGION_SIZE,
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device->dsp_iface_q_table.mem_data.size, sid);
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}
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}
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void __clock_config_on_enable_iris1(struct venus_hfi_device *device, u32 sid)
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{
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__write_register(device, WRAPPER_CPU_CGC_DIS, 0, sid);
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__write_register(device, WRAPPER_CPU_CLOCK_CONFIG, 0, sid);
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}
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