078c8b4302
git-subtree-dir: techpack/display git-subtree-mainline:59d05eab57git-subtree-split:06878e0bb5Change-Id: I3eb42ba067416dfb810d911813649ff7865da02e
318 lines
7.4 KiB
C
318 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clk/msm-clk-provider.h>
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#include <linux/clk/msm-clk.h>
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#include <linux/clk/msm-clock-generic.h>
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#include <dt-bindings/clock/msm-clocks-8974.h>
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#include "pll_drv.h"
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#include "dsi_pll.h"
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#define VCO_DELAY_USEC 1
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static struct clk_div_ops fixed_2div_ops;
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static const struct clk_ops byte_mux_clk_ops;
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static const struct clk_ops pixel_clk_src_ops;
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static const struct clk_ops byte_clk_src_ops;
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static const struct clk_ops analog_postdiv_clk_ops;
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static struct lpfr_cfg lpfr_lut_struct[] = {
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{479500000, 8},
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{480000000, 11},
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{575500000, 8},
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{576000000, 12},
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{610500000, 8},
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{659500000, 9},
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{671500000, 10},
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{672000000, 14},
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{708500000, 10},
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{750000000, 11},
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};
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static void dsi_pll_software_reset(struct mdss_pll_resources *dsi_pll_res)
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{
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/*
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* Add HW recommended delays after toggling the software
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* reset bit off and back on.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
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udelay(1);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
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udelay(1);
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}
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static int vco_set_rate_hpm(struct clk *c, unsigned long rate)
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{
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int rc;
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struct dsi_pll_vco_clk *vco = to_vco_clk(c);
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struct mdss_pll_resources *dsi_pll_res = vco->priv;
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rc = mdss_pll_resource_enable(dsi_pll_res, true);
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if (rc) {
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pr_err("Failed to enable mdss dsi pll resources\n");
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return rc;
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}
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rc = vco_set_rate(vco, rate);
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mdss_pll_resource_enable(dsi_pll_res, false);
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return rc;
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}
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static int dsi_pll_enable_seq_8974(struct mdss_pll_resources *dsi_pll_res)
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{
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int i, rc = 0;
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int pll_locked;
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dsi_pll_software_reset(dsi_pll_res);
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/*
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* PLL power up sequence.
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* Add necessary delays recommeded by hardware.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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udelay(1);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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udelay(200);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
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udelay(500);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(500);
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for (i = 0; i < 2; i++) {
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udelay(100);
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/* DSI Uniphy lock detect setting */
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0c);
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udelay(100);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
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pll_locked = dsi_pll_lock_status(dsi_pll_res);
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if (pll_locked)
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break;
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dsi_pll_software_reset(dsi_pll_res);
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/*
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* PLL power up sequence.
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* Add necessary delays recommeded by hardware.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x1);
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udelay(1);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
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udelay(200);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
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udelay(250);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
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udelay(200);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
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udelay(500);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0xf);
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udelay(500);
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}
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if (!pll_locked) {
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pr_err("DSI PLL lock failed\n");
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rc = -EINVAL;
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} else {
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pr_debug("DSI PLL Lock success\n");
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}
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return rc;
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}
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/* Op structures */
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static const struct clk_ops clk_ops_dsi_vco = {
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.set_rate = vco_set_rate_hpm,
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.round_rate = vco_round_rate,
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.handoff = vco_handoff,
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.prepare = vco_prepare,
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.unprepare = vco_unprepare,
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};
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static struct clk_div_ops fixed_4div_ops = {
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.set_div = fixed_4div_set_div,
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.get_div = fixed_4div_get_div,
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};
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static struct clk_div_ops analog_postdiv_ops = {
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.set_div = analog_set_div,
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.get_div = analog_get_div,
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};
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static struct clk_div_ops digital_postdiv_ops = {
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.set_div = digital_set_div,
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.get_div = digital_get_div,
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};
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static struct clk_mux_ops byte_mux_ops = {
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.set_mux_sel = set_byte_mux_sel,
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.get_mux_sel = get_byte_mux_sel,
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};
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static struct dsi_pll_vco_clk dsi_vco_clk_8974 = {
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.ref_clk_rate = 19200000,
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.min_rate = 350000000,
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.max_rate = 750000000,
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.pll_en_seq_cnt = 3,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_8974,
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.pll_enable_seqs[1] = dsi_pll_enable_seq_8974,
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.pll_enable_seqs[2] = dsi_pll_enable_seq_8974,
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.lpfr_lut_size = 10,
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.lpfr_lut = lpfr_lut_struct,
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.c = {
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.dbg_name = "dsi_vco_clk_8974",
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.ops = &clk_ops_dsi_vco,
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CLK_INIT(dsi_vco_clk_8974.c),
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},
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};
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static struct div_clk analog_postdiv_clk_8974 = {
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.data = {
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.max_div = 255,
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.min_div = 1,
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},
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.ops = &analog_postdiv_ops,
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.c = {
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.parent = &dsi_vco_clk_8974.c,
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.dbg_name = "analog_postdiv_clk",
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.ops = &analog_postdiv_clk_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(analog_postdiv_clk_8974.c),
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},
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};
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static struct div_clk indirect_path_div2_clk_8974 = {
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.ops = &fixed_2div_ops,
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.data = {
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.div = 2,
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.min_div = 2,
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.max_div = 2,
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},
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.c = {
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.parent = &analog_postdiv_clk_8974.c,
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.dbg_name = "indirect_path_div2_clk",
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.ops = &clk_ops_div,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(indirect_path_div2_clk_8974.c),
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},
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};
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static struct div_clk pixel_clk_src_8974 = {
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.data = {
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.max_div = 255,
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.min_div = 1,
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},
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.ops = &digital_postdiv_ops,
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.c = {
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.parent = &dsi_vco_clk_8974.c,
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.dbg_name = "pixel_clk_src_8974",
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.ops = &pixel_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(pixel_clk_src_8974.c),
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},
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};
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static struct mux_clk byte_mux_8974 = {
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.num_parents = 2,
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.parents = (struct clk_src[]){
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{&dsi_vco_clk_8974.c, 0},
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{&indirect_path_div2_clk_8974.c, 1},
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},
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.ops = &byte_mux_ops,
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.c = {
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.parent = &dsi_vco_clk_8974.c,
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.dbg_name = "byte_mux_8974",
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.ops = &byte_mux_clk_ops,
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CLK_INIT(byte_mux_8974.c),
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},
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};
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static struct div_clk byte_clk_src_8974 = {
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.ops = &fixed_4div_ops,
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.data = {
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.min_div = 4,
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.max_div = 4,
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},
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.c = {
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.parent = &byte_mux_8974.c,
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.dbg_name = "byte_clk_src_8974",
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.ops = &byte_clk_src_ops,
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CLK_INIT(byte_clk_src_8974.c),
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},
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};
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static struct clk_lookup mdss_dsi_pllcc_8974[] = {
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CLK_LOOKUP_OF("pixel_src", pixel_clk_src_8974,
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"fd8c0000.qcom,mmsscc-mdss"),
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CLK_LOOKUP_OF("byte_src", byte_clk_src_8974,
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"fd8c0000.qcom,mmsscc-mdss"),
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};
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int dsi_pll_clock_register_hpm(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc;
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/* Set client data to mux, div and vco clocks */
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byte_clk_src_8974.priv = pll_res;
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pixel_clk_src_8974.priv = pll_res;
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byte_mux_8974.priv = pll_res;
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indirect_path_div2_clk_8974.priv = pll_res;
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analog_postdiv_clk_8974.priv = pll_res;
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dsi_vco_clk_8974.priv = pll_res;
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pll_res->vco_delay = VCO_DELAY_USEC;
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/* Set clock source operations */
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pixel_clk_src_ops = clk_ops_slave_div;
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pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
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analog_postdiv_clk_ops = clk_ops_div;
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analog_postdiv_clk_ops.prepare = dsi_pll_div_prepare;
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byte_clk_src_ops = clk_ops_div;
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byte_clk_src_ops.prepare = dsi_pll_div_prepare;
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byte_mux_clk_ops = clk_ops_gen_mux;
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byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;
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if (pll_res->target_id == MDSS_PLL_TARGET_8974) {
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rc = of_msm_clock_register(pdev->dev.of_node,
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mdss_dsi_pllcc_8974, ARRAY_SIZE(mdss_dsi_pllcc_8974));
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if (rc) {
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pr_err("Clock register failed\n");
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rc = -EPROBE_DEFER;
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}
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} else {
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pr_err("Invalid target ID\n");
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rc = -EINVAL;
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}
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if (!rc)
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pr_info("Registered DSI PLL clocks successfully\n");
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return rc;
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}
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