8834c35bfc
When the system suspend is happening, last core disables the non-sec interrupts at QGIC by setting the GRPEN1_EL1_NS to ZERO. This prevents the core from detecting any non-sec interrupts and that would result in the system not waking up from any of interrupts. Do not modify GRPEN1_EL1_NS register when the system is going into suspend. Change-Id: I7d6c5047fb4743df187fe49fba18b64db3179bc9 Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org> Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _IRQ_GIC_COMMON_H
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#define _IRQ_GIC_COMMON_H
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/arm-gic-common.h>
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struct gic_quirk {
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const char *desc;
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bool (*init)(void *data);
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u32 iidr;
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u32 mask;
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};
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extern bool from_suspend;
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#ifdef CONFIG_QCOM_SHOW_RESUME_IRQ
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extern int msm_show_resume_irq_mask;
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#else
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#define msm_show_resume_irq_mask 0
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#endif
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int gic_configure_irq(unsigned int irq, unsigned int type,
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void __iomem *base, void (*sync_access)(void));
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void gic_dist_config(void __iomem *base, int gic_irqs,
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void (*sync_access)(void));
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void gic_cpu_config(void __iomem *base, void (*sync_access)(void));
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void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
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void *data);
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void gic_set_kvm_info(const struct gic_kvm_info *info);
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#endif /* _IRQ_GIC_COMMON_H */
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