1d9e50b547
This way, everything stays within the gmu files. Change-Id: Ia8e12ca8c0da6d4e18f235c5ae8a342e6742d819 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
224 lines
5.9 KiB
C
224 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef __KGSL_GMU_H
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#define __KGSL_GMU_H
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#include "kgsl_gmu_core.h"
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#include "kgsl_hfi.h"
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#define GMU_PWR_LEVELS 2
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#define GMU_FREQUENCY 200000000
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#define MAX_GMUFW_SIZE 0x8000 /* in bytes */
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#define BWMEM_SIZE (12 + (4 * NUM_BW_LEVELS)) /*in bytes*/
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#define GMU_VER_MAJOR(ver) (((ver) >> 28) & 0xF)
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#define GMU_VER_MINOR(ver) (((ver) >> 16) & 0xFFF)
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#define GMU_VER_STEP(ver) ((ver) & 0xFFFF)
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#define GMU_VERSION(major, minor) \
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((((major) & 0xF) << 28) | (((minor) & 0xFFF) << 16))
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#define GMU_INT_WDOG_BITE BIT(0)
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#define GMU_INT_RSCC_COMP BIT(1)
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#define GMU_INT_FENCE_ERR BIT(3)
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#define GMU_INT_DBD_WAKEUP BIT(4)
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#define GMU_INT_HOST_AHB_BUS_ERR BIT(5)
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#define GMU_AO_INT_MASK \
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(GMU_INT_WDOG_BITE | \
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GMU_INT_FENCE_ERR | \
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GMU_INT_HOST_AHB_BUS_ERR)
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/* Bitmask for GPU low power mode enabling and hysterisis*/
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#define SPTP_ENABLE_MASK (BIT(2) | BIT(0))
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#define IFPC_ENABLE_MASK (BIT(1) | BIT(0))
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#define HW_NAP_ENABLE_MASK BIT(0)
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#define MIN_BW_ENABLE_MASK BIT(12)
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#define MIN_BW_HYST 0xFA0
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/* Bitmask for RPMH capability enabling */
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#define RPMH_INTERFACE_ENABLE BIT(0)
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#define LLC_VOTE_ENABLE BIT(4)
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#define DDR_VOTE_ENABLE BIT(8)
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#define MX_VOTE_ENABLE BIT(9)
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#define CX_VOTE_ENABLE BIT(10)
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#define GFX_VOTE_ENABLE BIT(11)
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#define RPMH_ENABLE_MASK (RPMH_INTERFACE_ENABLE | \
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LLC_VOTE_ENABLE | \
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DDR_VOTE_ENABLE | \
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MX_VOTE_ENABLE | \
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CX_VOTE_ENABLE | \
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GFX_VOTE_ENABLE)
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/* Constants for GMU OOBs */
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#define OOB_BOOT_OPTION 0
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#define OOB_SLUMBER_OPTION 1
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/* Gmu FW block header format */
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struct gmu_block_header {
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uint32_t addr;
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uint32_t size;
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uint32_t type;
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uint32_t value;
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};
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/* GMU Block types */
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#define GMU_BLK_TYPE_DATA 0
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#define GMU_BLK_TYPE_PREALLOC_REQ 1
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#define GMU_BLK_TYPE_CORE_VER 2
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#define GMU_BLK_TYPE_CORE_DEV_VER 3
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#define GMU_BLK_TYPE_PWR_VER 4
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#define GMU_BLK_TYPE_PWR_DEV_VER 5
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#define GMU_BLK_TYPE_HFI_VER 6
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#define GMU_BLK_TYPE_PREALLOC_PERSIST_REQ 7
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/* For GMU Logs*/
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#define LOGMEM_SIZE SZ_4K
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/* GMU memdesc entries */
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#define GMU_KERNEL_ENTRIES 16
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extern struct gmu_dev_ops adreno_a6xx_gmudev;
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#define KGSL_GMU_DEVICE(_a) ((struct gmu_device *)((_a)->gmu_core.ptr))
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enum gmu_mem_type {
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GMU_ITCM = 0,
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GMU_ICACHE,
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GMU_CACHE = GMU_ICACHE,
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GMU_DTCM,
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GMU_DCACHE,
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GMU_NONCACHED_KERNEL,
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GMU_NONCACHED_USER,
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GMU_MEM_TYPE_MAX,
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};
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enum gmu_context_index {
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GMU_CONTEXT_USER = 0,
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GMU_CONTEXT_KERNEL,
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};
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/**
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* struct gmu_memdesc - Gmu shared memory object descriptor
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* @hostptr: Kernel virtual address
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* @gmuaddr: GPU virtual address
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* @physaddr: Physical address of the memory object
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* @size: Size of the memory object
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* @mem_type: memory type for this memory
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* @ctx_idx: GMU IOMMU context idx
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*/
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struct gmu_memdesc {
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void *hostptr;
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uint64_t gmuaddr;
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phys_addr_t physaddr;
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uint64_t size;
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enum gmu_mem_type mem_type;
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enum gmu_context_index ctx_idx;
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};
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struct gmu_bw_votes {
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uint32_t cmds_wait_bitmask;
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uint32_t cmds_per_bw_vote;
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uint32_t cmd_addrs[MAX_BW_CMDS];
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uint32_t cmd_data[MAX_GX_LEVELS][MAX_BW_CMDS];
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};
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struct rpmh_votes_t {
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uint32_t gx_votes[MAX_GX_LEVELS];
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uint32_t cx_votes[MAX_CX_LEVELS];
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struct gmu_bw_votes ddr_votes;
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struct gmu_bw_votes cnoc_votes;
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};
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enum gmu_load_mode {
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CACHED_LOAD_BOOT,
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CACHED_BOOT,
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TCM_BOOT,
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TCM_LOAD_BOOT,
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INVALID_LOAD
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};
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struct kgsl_mailbox {
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struct mbox_client *client;
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struct mbox_chan *channel;
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};
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/**
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* struct gmu_device - GMU device structure
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* @ver: GMU Version information
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* @reg_phys: GMU CSR physical address
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* @reg_len: GMU CSR range
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* @gmu_interrupt_num: GMU interrupt number
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* @fw_image: GMU FW image
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* @hfi_mem: pointer to HFI shared memory
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* @dump_mem: pointer to GMU debug dump memory
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* @gmu_log: gmu event log memory
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* @hfi: HFI controller
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* @gpu_freqs: GPU frequency table with lowest freq at index 0
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* @num_gpupwrlevels: number GPU frequencies in GPU freq table
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* @num_bwlevel: number of GPU BW levels
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* @num_cnocbwlevel: number CNOC BW levels
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* @rpmh_votes: RPMh TCS command set for GPU, GMU voltage and bw scaling
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* @cx_gdsc: CX headswitch that controls power of GMU and
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subsystem peripherals
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* @gx_gdsc: GX headswitch that controls power of GPU subsystem
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* @clks: GPU subsystem clocks required for GMU functionality
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* @load_mode: GMU FW load/boot mode
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* @wakeup_pwrlevel: GPU wake up power/DCVS level in case different
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* than default power level
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* @pcl: GPU BW scaling client
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* @ccl: CNOC BW scaling client
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* @idle_level: Minimal GPU idle power level
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* @fault_count: GMU fault count
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* @mailbox: Messages to AOP for ACD enable/disable go through this
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* @log_wptr_retention: Store the log wptr offset on slumber
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*/
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struct gmu_device {
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struct {
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u32 core;
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u32 core_dev;
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u32 pwr;
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u32 pwr_dev;
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u32 hfi;
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} ver;
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struct platform_device *pdev;
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unsigned long reg_phys;
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unsigned int reg_len;
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int gmu_interrupt_num;
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const struct firmware *fw_image;
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struct gmu_memdesc *hfi_mem;
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struct gmu_memdesc *dump_mem;
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struct gmu_memdesc *gmu_log;
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struct kgsl_hfi hfi;
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unsigned int gpu_freqs[MAX_GX_LEVELS];
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unsigned int num_gpupwrlevels;
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unsigned int num_bwlevels;
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unsigned int num_cnocbwlevels;
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struct rpmh_votes_t rpmh_votes;
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struct regulator *cx_gdsc;
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struct regulator *gx_gdsc;
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struct clk *clks[MAX_GMU_CLKS];
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enum gmu_load_mode load_mode;
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unsigned int wakeup_pwrlevel;
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unsigned int pcl;
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unsigned int ccl;
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unsigned int idle_level;
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unsigned int fault_count;
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struct kgsl_mailbox mailbox;
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bool preallocations;
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struct gmu_memdesc kmem_entries[GMU_KERNEL_ENTRIES];
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unsigned long kmem_bitmap;
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const struct gmu_vma_entry *vma;
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unsigned int log_wptr_retention;
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};
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struct gmu_memdesc *gmu_get_memdesc(struct gmu_device *gmu,
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unsigned int addr, unsigned int size);
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unsigned int gmu_get_memtype_base(struct gmu_device *gmu,
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enum gmu_mem_type type);
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int gmu_prealloc_req(struct kgsl_device *device, struct gmu_block_header *blk);
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int gmu_cache_finalize(struct kgsl_device *device);
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#endif /* __KGSL_GMU_H */
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