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clk/qcom/clk-alpha-pll: Fix pll post div mask when width is not set

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Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.

Fixes: 1c35411 ("clk: qcom: support for 2 bit PLL post divider")
Change-Id: I8e4fa923b1183a14c7893f08597a8289f8c3e3b8
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Tested-by: Christopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20241006-fix-postdiv-mask-v3-1-160354980433@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Barnabás Czémán
2024-10-24 22:44:08 +08:00
committed by Bruno Martins
parent 327fcc87ed
commit f973db0464
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/qcom/clk-alpha-pll.c
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@@ -44,7 +44,7 @@
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
#define PLL_POST_DIV_SHIFT 8
#define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
#define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
#define PLL_ALPHA_EN BIT(24)
#define PLL_ALPHA_MODE BIT(25)
#define PLL_VCO_SHIFT 20