Merge "i3c: i3c-master-qcom-geni: Fix IBI and Hot join related issues"
This commit is contained in:
qctecmdr
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Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
commit
ed57810b41
@@ -151,12 +151,17 @@
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#define CFG_FAIL_STALL_DIFF_EN BIT(20)
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#define ADDR_ASSOCIATED_W_OTHER_GPII_EN BIT(21)
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/* Enable bits for GPIIn, n:[0-11] */
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#define GPIIn_IBI_EN(n) BIT(n)
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/* IBI_CMD fields */
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#define IBI_CMD_OPCODE BIT(0)
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#define I3C_SLAVE_RW BIT(15)
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#define STALL BIT(21)
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#define I3C_SLAVE_ADDR_SHIFT 8
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#define I3C_SLAVE_MASK 0x7f
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#define NUM_OF_MDB_SHIFT 16
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#define IBI_NUM_OF_MDB_MSK GENMASK(18, 16)
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/* IBI_GEN_CONFIG fields */
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#define IBI_C_ENABLE BIT(0)
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@@ -319,6 +324,9 @@ struct geni_i3c_clk_fld {
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u32 i2c_t_cycle_cnt;
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};
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static void geni_i3c_enable_ibi_ctrl(struct geni_i3c_dev *gi3c, bool enable);
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static void geni_i3c_enable_ibi_irq(struct geni_i3c_dev *gi3c, bool enable);
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static struct geni_i3c_dev*
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to_geni_i3c_master(struct i3c_master_controller *master)
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{
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@@ -1456,38 +1464,14 @@ static int geni_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
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static void qcom_geni_i3c_ibi_conf(struct geni_i3c_dev *gi3c)
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{
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u32 val, timeout;
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gi3c->ibi.err = 0;
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reinit_completion(&gi3c->ibi.done);
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/* set the configuration for 100Khz OD speed */
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geni_write_reg(0x5FD74322, gi3c->se.ibi_base, IBI_SCL_PP_TIMING_CONFIG);
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/* Enable I3C IBI controller */
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_CONFIG);
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val |= IBI_C_ENABLE;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_CONFIG);
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/* enable ENABLE_CHANGE */
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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val |= IBI_C_ENABLE;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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/* wait for ENABLE_CHANGE */
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timeout = wait_for_completion_timeout(&gi3c->ibi.done, XFER_TIMEOUT);
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if (!timeout) {
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"timeout while ENABLE_CHANGE bit\n");
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return;
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}
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/* enable manager interrupts */
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geni_write_reg(0x1B, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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/* Enable GPII0 interrupts */
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geni_write_reg(0x1, gi3c->se.ibi_base, IBI_GPII_IBI_EN);
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geni_write_reg(~0u, gi3c->se.ibi_base, IBI_IRQ_EN(0));
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geni_i3c_enable_ibi_ctrl(gi3c, true);
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geni_i3c_enable_ibi_irq(gi3c, true);
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gi3c->ibi.is_init = true;
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}
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@@ -1498,6 +1482,7 @@ static int geni_i3c_master_request_ibi(struct i3c_dev_desc *dev,
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struct geni_i3c_dev *gi3c = to_geni_i3c_master(m);
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struct geni_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
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unsigned long i, flags;
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unsigned int payload_len = req->max_payload_len;
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if (!gi3c->ibi.hw_support)
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return -EPERM;
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@@ -1531,6 +1516,7 @@ static int geni_i3c_master_request_ibi(struct i3c_dev_desc *dev,
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cmd = ((dev->info.dyn_addr & I3C_SLAVE_MASK)
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<< I3C_SLAVE_ADDR_SHIFT) | I3C_SLAVE_RW | STALL;
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cmd |= ((payload_len << NUM_OF_MDB_SHIFT) & IBI_NUM_OF_MDB_MSK);
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geni_write_reg(cmd, gi3c->se.ibi_base, IBI_CMD(0));
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/* wait for adding slave IBI */
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@@ -1591,9 +1577,103 @@ static int qcom_deallocate_ibi_table_entry(struct geni_i3c_dev *gi3c)
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return 0;
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}
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static void qcom_geni_i3c_ibi_unconf(struct geni_i3c_dev *gi3c)
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static void geni_i3c_enable_hotjoin_irq(struct geni_i3c_dev *gi3c, bool enable)
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{
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u32 val;
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//Disable hot-join, until next probe happens
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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if (enable)
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val |= HOT_JOIN_IRQ_EN;
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else
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val &= ~HOT_JOIN_IRQ_EN;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"%s:%s\n", __func__, (enable) ? "Enabled" : "Disabled");
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}
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static void geni_i3c_enable_ibi_irq(struct geni_i3c_dev *gi3c, bool enable)
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{
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u32 val;
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if (enable) {
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/* enable manager interrupts : HPG sec 4.1 */
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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val |= (val & 0x1B);
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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/* Enable GPII0 interrupts */
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geni_write_reg(GPIIn_IBI_EN(0), gi3c->se.ibi_base,
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IBI_GPII_IBI_EN);
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geni_write_reg(~0u, gi3c->se.ibi_base, IBI_IRQ_EN(0));
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} else {
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geni_write_reg(0, gi3c->se.ibi_base, IBI_GPII_IBI_EN);
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geni_write_reg(0, gi3c->se.ibi_base, IBI_IRQ_EN(0));
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geni_write_reg(0, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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}
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}
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static void geni_i3c_enable_ibi_ctrl(struct geni_i3c_dev *gi3c, bool enable)
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{
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u32 val, timeout;
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if (enable) {
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reinit_completion(&gi3c->ibi.done);
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/* enable ENABLE_CHANGE */
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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val |= IBI_C_ENABLE;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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/* Enable I3C IBI controller, if not in enabled state */
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_CONFIG);
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if (!(val & IBI_C_ENABLE)) {
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val |= IBI_C_ENABLE;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_CONFIG);
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/* wait for ENABLE_CHANGE */
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timeout = wait_for_completion_timeout(&gi3c->ibi.done,
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XFER_TIMEOUT);
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if (!timeout) {
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"timeout while ENABLE_CHANGE bit\n");
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return;
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}
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"%s: IBI ctrl enabled\n", __func__);
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}
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} else {
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/* Disable IBI controller */
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/* check if any IBI is enabled, if not then disable IBI ctrl */
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GPII_IBI_EN);
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if (!val) {
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gi3c->ibi.err = 0;
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reinit_completion(&gi3c->ibi.done);
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_CONFIG);
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val &= ~IBI_C_ENABLE;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_CONFIG);
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/* wait for ENABLE change */
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timeout = wait_for_completion_timeout(&gi3c->ibi.done,
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XFER_TIMEOUT);
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if (!timeout) {
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"timeout disabling IBI: 0x%x\n", gi3c->ibi.err);
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return;
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}
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"%s: IBI ctrl disabled\n", __func__);
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}
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}
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}
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static void qcom_geni_i3c_ibi_unconf(struct geni_i3c_dev *gi3c)
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{
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u32 val;
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int ret = 0;
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val = geni_read_reg(gi3c->se.ibi_base, IBI_ALLOCATED_ENTRIES_GPII(0));
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@@ -1603,40 +1683,6 @@ static void qcom_geni_i3c_ibi_unconf(struct geni_i3c_dev *gi3c)
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return;
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}
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/* disable interrupts */
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geni_write_reg(0, gi3c->se.ibi_base, IBI_GPII_IBI_EN);
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geni_write_reg(0, gi3c->se.ibi_base, IBI_IRQ_EN(0));
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/* check if any IBI is enabled, if not then reset HW */
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GPII_IBI_EN);
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if (!val) {
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gi3c->ibi.err = 0;
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reinit_completion(&gi3c->ibi.done);
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_CONFIG);
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val &= ~IBI_C_ENABLE;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_CONFIG);
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/* wait for ENABLE change */
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timeout = wait_for_completion_timeout(&gi3c->ibi.done,
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XFER_TIMEOUT);
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if (!timeout) {
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"timeout while disabling IBI controller\n");
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return;
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}
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if (gi3c->ibi.err) {
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"error while disabling IBI controller 0x%x\n",
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gi3c->ibi.err);
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return;
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}
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}
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gi3c->ibi.is_init = false;
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}
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@@ -1992,17 +2038,6 @@ static int geni_i3c_probe(struct platform_device *pdev)
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geni_se_init(gi3c->se.base, gi3c->tx_wm, tx_depth);
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se_config_packing(gi3c->se.base, BITS_PER_BYTE, PACKING_BYTES_PW, true);
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gi3c->hj_wl = wakeup_source_register(gi3c->se.dev,
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dev_name(gi3c->se.dev));
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if (!gi3c->hj_wl) {
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GENI_SE_ERR(gi3c->ipcl, false, gi3c->se.dev, "wakeup source registration failed\n");
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se_geni_resources_off(&gi3c->se.i3c_rsc);
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return -ENOMEM;
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}
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INIT_WORK(&gi3c->hj_wd, geni_i3c_hotjoin);
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gi3c->hj_wq = alloc_workqueue("%s", 0, 0, dev_name(gi3c->se.dev));
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ret = i3c_ibi_rsrcs_init(gi3c, pdev);
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if (ret) {
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se_geni_resources_off(&gi3c->se.i3c_rsc);
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@@ -2025,8 +2060,19 @@ static int geni_i3c_probe(struct platform_device *pdev)
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GENI_SE_ERR(gi3c->ipcl, false, gi3c->se.dev,
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"i3c_master_register failed:%d\n", ret);
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//enable hot-join IRQ also
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geni_write_reg(~0u, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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// hot-join
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gi3c->hj_wl = wakeup_source_register(gi3c->se.dev,
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dev_name(gi3c->se.dev));
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if (!gi3c->hj_wl) {
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GENI_SE_ERR(gi3c->ipcl, false, gi3c->se.dev,
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"wakeup source registration failed\n");
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se_geni_resources_off(&gi3c->se.i3c_rsc);
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return -ENOMEM;
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}
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INIT_WORK(&gi3c->hj_wd, geni_i3c_hotjoin);
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gi3c->hj_wq = alloc_workqueue("%s", 0, 0, dev_name(gi3c->se.dev));
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geni_i3c_enable_hotjoin_irq(gi3c, true);
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev, "I3C probed\n");
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@@ -2036,17 +2082,20 @@ static int geni_i3c_probe(struct platform_device *pdev)
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static int geni_i3c_remove(struct platform_device *pdev)
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{
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struct geni_i3c_dev *gi3c = platform_get_drvdata(pdev);
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int ret = 0, val = 0;
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int ret = 0;
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//Disable hot-join, until next probe happens
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val = geni_read_reg(gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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val &= ~HOT_JOIN_IRQ_EN;
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geni_write_reg(val, gi3c->se.ibi_base, IBI_GEN_IRQ_EN);
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geni_i3c_enable_hotjoin_irq(gi3c, false);
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destroy_workqueue(gi3c->hj_wq);
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wakeup_source_unregister(gi3c->hj_wl);
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if (gi3c->ibi.is_init)
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qcom_geni_i3c_ibi_unconf(gi3c);
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destroy_workqueue(gi3c->hj_wq);
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wakeup_source_unregister(gi3c->hj_wl);
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geni_i3c_enable_ibi_ctrl(gi3c, false);
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/* Potentially to be done before pinctrl change */
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geni_i3c_enable_ibi_irq(gi3c, false);
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/*force suspend to avoid the auto suspend caused by driver removal*/
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pm_runtime_force_suspend(gi3c->se.dev);
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ret = pinctrl_select_state(gi3c->se.i3c_rsc.geni_pinctrl,
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@@ -2054,7 +2103,9 @@ static int geni_i3c_remove(struct platform_device *pdev)
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if (ret)
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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" i3c: pinctrl_select_state failed\n");
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ret = i3c_master_unregister(&gi3c->ctrlr);
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/* TBD : If we need debug for previous session, Don't delete logs */
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if (gi3c->ipcl)
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ipc_log_context_destroy(gi3c->ipcl);
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return ret;
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