PCI: Move Rohm Vendor ID to generic list
[ Upstream commit 0ce26a1c31ca928df4dfc7504c8898b71ff9f5d5 ] Move the Rohm Vendor ID to pci_ids.h instead of defining it in several drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
3027c58b74
commit
ea2d984775
@@ -972,7 +972,6 @@ static void pch_dma_remove(struct pci_dev *pdev)
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}
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}
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/* PCI Device ID of DMA device */
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/* PCI Device ID of DMA device */
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#define PCI_VENDOR_ID_ROHM 0x10DB
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#define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810
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#define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810
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#define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815
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#define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815
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#define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026
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#define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026
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@@ -31,8 +31,6 @@
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#define IOH_IRQ_BASE 0
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#define IOH_IRQ_BASE 0
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#define PCI_VENDOR_ID_ROHM 0x10DB
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struct ioh_reg_comn {
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struct ioh_reg_comn {
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u32 ien;
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u32 ien;
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u32 istatus;
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u32 istatus;
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@@ -524,7 +524,6 @@ static int pch_gpio_resume(struct pci_dev *pdev)
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#define pch_gpio_resume NULL
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#define pch_gpio_resume NULL
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#endif
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#endif
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#define PCI_VENDOR_ID_ROHM 0x10DB
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static const struct pci_device_id pch_gpio_pcidev_id[] = {
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static const struct pci_device_id pch_gpio_pcidev_id[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
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{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
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{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
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@@ -177,7 +177,6 @@ static wait_queue_head_t pch_event;
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static DEFINE_MUTEX(pch_mutex);
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static DEFINE_MUTEX(pch_mutex);
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/* Definition for ML7213 by LAPIS Semiconductor */
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/* Definition for ML7213 by LAPIS Semiconductor */
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#define PCI_VENDOR_ID_ROHM 0x10DB
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#define PCI_DEVICE_ID_ML7213_I2C 0x802D
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#define PCI_DEVICE_ID_ML7213_I2C 0x802D
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#define PCI_DEVICE_ID_ML7223_I2C 0x8010
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#define PCI_DEVICE_ID_ML7223_I2C 0x8010
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#define PCI_DEVICE_ID_ML7831_I2C 0x8817
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#define PCI_DEVICE_ID_ML7831_I2C 0x8817
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@@ -64,7 +64,6 @@
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#define CLKCFG_UARTCLKSEL (1 << 18)
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#define CLKCFG_UARTCLKSEL (1 << 18)
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/* Macros for ML7213 */
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/* Macros for ML7213 */
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#define PCI_VENDOR_ID_ROHM 0x10db
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#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
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#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
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/* Macros for ML7223 */
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/* Macros for ML7223 */
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@@ -27,7 +27,6 @@
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#define DRV_VERSION "1.01"
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#define DRV_VERSION "1.01"
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const char pch_driver_version[] = DRV_VERSION;
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const char pch_driver_version[] = DRV_VERSION;
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#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
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#define PCH_GBE_MAR_ENTRIES 16
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#define PCH_GBE_MAR_ENTRIES 16
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#define PCH_GBE_SHORT_PKT 64
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#define PCH_GBE_SHORT_PKT 64
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#define DSC_INIT16 0xC000
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#define DSC_INIT16 0xC000
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@@ -37,11 +36,9 @@ const char pch_driver_version[] = DRV_VERSION;
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#define PCH_GBE_PCI_BAR 1
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#define PCH_GBE_PCI_BAR 1
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#define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
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#define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
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/* Macros for ML7223 */
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#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802
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#define PCI_VENDOR_ID_ROHM 0x10db
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#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
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/* Macros for ML7831 */
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#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
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#define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
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#define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
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#define PCH_GBE_TX_WEIGHT 64
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#define PCH_GBE_TX_WEIGHT 64
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@@ -92,7 +92,6 @@
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#define PCH_MAX_SPBR 1023
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#define PCH_MAX_SPBR 1023
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/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
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/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
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#define PCI_VENDOR_ID_ROHM 0x10DB
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#define PCI_DEVICE_ID_ML7213_SPI 0x802c
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#define PCI_DEVICE_ID_ML7213_SPI 0x802c
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#define PCI_DEVICE_ID_ML7223_SPI 0x800F
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#define PCI_DEVICE_ID_ML7223_SPI 0x800F
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#define PCI_DEVICE_ID_ML7831_SPI 0x8816
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#define PCI_DEVICE_ID_ML7831_SPI 0x8816
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@@ -192,8 +192,6 @@ enum {
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#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
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#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
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#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
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#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
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#define PCI_VENDOR_ID_ROHM 0x10DB
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
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#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
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@@ -368,7 +368,6 @@ struct pch_udc_dev {
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#define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC 0x0939
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#define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC 0x0939
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#define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
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#define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
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#define PCI_VENDOR_ID_ROHM 0x10DB
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#define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
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#define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
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#define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
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#define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
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@@ -1140,6 +1140,8 @@
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#define PCI_VENDOR_ID_TCONRAD 0x10da
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#define PCI_VENDOR_ID_TCONRAD 0x10da
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#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
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#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
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#define PCI_VENDOR_ID_ROHM 0x10db
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#define PCI_VENDOR_ID_NVIDIA 0x10de
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#define PCI_VENDOR_ID_NVIDIA 0x10de
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#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
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#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
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#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
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#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
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