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clk: qcom: clk-rcg2: Update logic to calculate D value for RCG

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The current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range. While at it, add
support for 2/3 divider in frac_table_pixel.

Change-Id: Ia42b9197de6d594129b1a48106f8e5a2be70a1c6
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
This commit is contained in:
Jagadeesh Kona
2021-09-29 12:53:48 +05:30
committed by Jagadeesh Kona
parent a4341e9d9e
commit e9ba570dbf
1 changed files with 12 additions and 2 deletions
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14
drivers/clk/qcom/clk-rcg2.c
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@@ -506,7 +506,7 @@ static bool clk_rcg2_current_config(struct clk_rcg2 *rcg,
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
{
u32 cfg, mask;
u32 cfg, mask, d_val, not2d_val, n_minus_m;
struct clk_hw *hw = &rcg->clkr.hw;
int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
@@ -525,8 +525,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
if (ret)
return ret;
/* Calculate 2d value */
d_val = f->n;
n_minus_m = f->n - f->m;
n_minus_m *= 2;
d_val = clamp_t(u32, d_val, f->m, n_minus_m);
not2d_val = ~d_val & mask;
ret = regmap_update_bits(rcg->clkr.regmap,
rcg->cmd_rcgr + D_REG, mask, ~f->n);
rcg->cmd_rcgr + D_REG, mask, not2d_val);
if (ret)
return ret;
}
@@ -1102,6 +1111,7 @@ static const struct frac_entry frac_table_pixel[] = {
{ 2, 9 },
{ 4, 9 },
{ 1, 1 },
{ 2, 3 },
{ }
};