From cc83dfc7cea40b7fc76c7a4d432e7a29991ae9e8 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Tue, 30 Oct 2018 15:07:28 -0700 Subject: [PATCH 01/74] lib/lz4: update LZ4 decompressor module Update the LZ4 compression module based on LZ4 v1.8.3 in order for the erofs file system to use the newest LZ4_decompress_safe_partial() which can now decode exactly the nb of bytes requested [1] to take place of the open hacked code in the erofs file system itself. Currently, apart from the erofs file system, no other users use LZ4_decompress_safe_partial, so no worry about the interface. In addition, LZ4 v1.8.x boosts up decompression speed compared to the current code which is based on LZ4 v1.7.3, mainly due to shortcut optimization for the specific common LZ4-sequences [2]. lzbench testdata (tested in kirin710, 8 cores, 4 big cores at 2189Mhz, 2GB DDR RAM at 1622Mhz, with enwik8 testdata [3]): Compressor name Compress. Decompress. Compr. size Ratio Filename memcpy 5004 MB/s 4924 MB/s 100000000 100.00 enwik8 lz4hc 1.7.3 -9 12 MB/s 653 MB/s 42203253 42.20 enwik8 lz4hc 1.8.0 -9 12 MB/s 908 MB/s 42203096 42.20 enwik8 lz4hc 1.8.3 -9 11 MB/s 965 MB/s 42203094 42.20 enwik8 [1] https://github.com/lz4/lz4/issues/566 https://github.com/lz4/lz4/commit/08d347b5b217b011ff7487130b79480d8cfdaeb8 [2] v1.8.1 perf: slightly faster compression and decompression speed https://github.com/lz4/lz4/commit/a31b7058cb97e4393da55e78a77a1c6f0c9ae038 v1.8.2 perf: slightly faster HC compression and decompression speed https://github.com/lz4/lz4/commit/45f8603aae389d34c689d3ff7427b314071ccd2c https://github.com/lz4/lz4/commit/1a191b3f8d26b50a7c1d41590b529ec308d768cd [3] http://mattmahoney.net/dc/textdata.html http://mattmahoney.net/dc/enwik8.zip Link: http://lkml.kernel.org/r/1537181207-21932-1-git-send-email-gaoxiang25@huawei.com Signed-off-by: Gao Xiang Tested-by: Guo Xuenan Cc: Colin Ian King Cc: Yann Collet Cc: Greg Kroah-Hartman Cc: Fang Wei Cc: Chao Yu Cc: Miao Xie Cc: Sven Schmidt <4sschmid@informatik.uni-hamburg.de> Cc: Kyungsik Lee Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- lib/lz4/lz4_decompress.c | 495 +++++++++++++++++++++++++++------------ lib/lz4/lz4defs.h | 9 +- 2 files changed, 356 insertions(+), 148 deletions(-) diff --git a/lib/lz4/lz4_decompress.c b/lib/lz4/lz4_decompress.c index 141734d255e4..0c9d3ad17e0f 100644 --- a/lib/lz4/lz4_decompress.c +++ b/lib/lz4/lz4_decompress.c @@ -43,30 +43,36 @@ /*-***************************** * Decompression functions *******************************/ -/* LZ4_decompress_generic() : - * This generic decompression function cover all use cases. - * It shall be instantiated several times, using different sets of directives - * Note that it is important this generic function is really inlined, + +#define DEBUGLOG(l, ...) {} /* disabled */ + +#ifndef assert +#define assert(condition) ((void)0) +#endif + +/* + * LZ4_decompress_generic() : + * This generic decompression function covers all use cases. + * It shall be instantiated several times, using different sets of directives. + * Note that it is important for performance that this function really get inlined, * in order to remove useless branches during compilation optimization. */ static FORCE_INLINE int LZ4_decompress_generic( - const char * const source, - char * const dest, - int inputSize, + const char * const src, + char * const dst, + int srcSize, /* * If endOnInput == endOnInputSize, - * this value is the max size of Output Buffer. + * this value is `dstCapacity` */ int outputSize, /* endOnOutputSize, endOnInputSize */ - int endOnInput, + endCondition_directive endOnInput, /* full, partial */ - int partialDecoding, - /* only used if partialDecoding == partial */ - int targetOutputSize, + earlyEnd_directive partialDecoding, /* noDict, withPrefix64k, usingExtDict */ - int dict, - /* == dest when no prefix */ + dict_directive dict, + /* always <= dst, == dst when no prefix */ const BYTE * const lowPrefix, /* only if dict == usingExtDict */ const BYTE * const dictStart, @@ -74,35 +80,43 @@ static FORCE_INLINE int LZ4_decompress_generic( const size_t dictSize ) { - /* Local Variables */ - const BYTE *ip = (const BYTE *) source; - const BYTE * const iend = ip + inputSize; + const BYTE *ip = (const BYTE *) src; + const BYTE * const iend = ip + srcSize; - BYTE *op = (BYTE *) dest; + BYTE *op = (BYTE *) dst; BYTE * const oend = op + outputSize; BYTE *cpy; - BYTE *oexit = op + targetOutputSize; - const BYTE * const lowLimit = lowPrefix - dictSize; const BYTE * const dictEnd = (const BYTE *)dictStart + dictSize; - static const unsigned int dec32table[] = { 0, 1, 2, 1, 4, 4, 4, 4 }; - static const int dec64table[] = { 0, 0, 0, -1, 0, 1, 2, 3 }; + static const unsigned int inc32table[8] = {0, 1, 2, 1, 0, 4, 4, 4}; + static const int dec64table[8] = {0, 0, 0, -1, -4, 1, 2, 3}; const int safeDecode = (endOnInput == endOnInputSize); const int checkOffset = ((safeDecode) && (dictSize < (int)(64 * KB))); + /* Set up the "end" pointers for the shortcut. */ + const BYTE *const shortiend = iend - + (endOnInput ? 14 : 8) /*maxLL*/ - 2 /*offset*/; + const BYTE *const shortoend = oend - + (endOnInput ? 14 : 8) /*maxLL*/ - 18 /*maxML*/; + + DEBUGLOG(5, "%s (srcSize:%i, dstSize:%i)", __func__, + srcSize, outputSize); + /* Special cases */ - /* targetOutputSize too high => decode everything */ - if ((partialDecoding) && (oexit > oend - MFLIMIT)) - oexit = oend - MFLIMIT; + assert(lowPrefix <= op); + assert(src != NULL); /* Empty output buffer */ if ((endOnInput) && (unlikely(outputSize == 0))) - return ((inputSize == 1) && (*ip == 0)) ? 0 : -1; + return ((srcSize == 1) && (*ip == 0)) ? 0 : -1; if ((!endOnInput) && (unlikely(outputSize == 0))) return (*ip == 0 ? 1 : -1); + if ((endOnInput) && unlikely(srcSize == 0)) + return -1; + /* Main Loop : decode sequences */ while (1) { size_t length; @@ -111,12 +125,74 @@ static FORCE_INLINE int LZ4_decompress_generic( /* get literal length */ unsigned int const token = *ip++; - length = token>>ML_BITS; + /* ip < iend before the increment */ + assert(!endOnInput || ip <= iend); + + /* + * A two-stage shortcut for the most common case: + * 1) If the literal length is 0..14, and there is enough + * space, enter the shortcut and copy 16 bytes on behalf + * of the literals (in the fast mode, only 8 bytes can be + * safely copied this way). + * 2) Further if the match length is 4..18, copy 18 bytes + * in a similar manner; but we ensure that there's enough + * space in the output for those 18 bytes earlier, upon + * entering the shortcut (in other words, there is a + * combined check for both stages). + */ + if ((endOnInput ? length != RUN_MASK : length <= 8) + /* + * strictly "less than" on input, to re-enter + * the loop with at least one byte + */ + && likely((endOnInput ? ip < shortiend : 1) & + (op <= shortoend))) { + /* Copy the literals */ + memcpy(op, ip, endOnInput ? 16 : 8); + op += length; ip += length; + + /* + * The second stage: + * prepare for match copying, decode full info. + * If it doesn't work out, the info won't be wasted. + */ + length = token & ML_MASK; /* match length */ + offset = LZ4_readLE16(ip); + ip += 2; + match = op - offset; + assert(match <= op); /* check overflow */ + + /* Do not deal with overlapping matches. */ + if ((length != ML_MASK) && + (offset >= 8) && + (dict == withPrefix64k || match >= lowPrefix)) { + /* Copy the match. */ + memcpy(op + 0, match + 0, 8); + memcpy(op + 8, match + 8, 8); + memcpy(op + 16, match + 16, 2); + op += length + MINMATCH; + /* Both stages worked, load the next token. */ + continue; + } + + /* + * The second stage didn't work out, but the info + * is ready. Propel it right to the point of match + * copying. + */ + goto _copy_match; + } + + /* decode literal length */ if (length == RUN_MASK) { unsigned int s; + if (unlikely(endOnInput ? ip >= iend - RUN_MASK : 0)) { + /* overflow detection */ + goto _output_error; + } do { s = *ip++; length += s; @@ -125,14 +201,14 @@ static FORCE_INLINE int LZ4_decompress_generic( : 1) & (s == 255)); if ((safeDecode) - && unlikely( - (size_t)(op + length) < (size_t)(op))) { + && unlikely((uptrval)(op) + + length < (uptrval)(op))) { /* overflow detection */ goto _output_error; } if ((safeDecode) - && unlikely( - (size_t)(ip + length) < (size_t)(ip))) { + && unlikely((uptrval)(ip) + + length < (uptrval)(ip))) { /* overflow detection */ goto _output_error; } @@ -140,16 +216,19 @@ static FORCE_INLINE int LZ4_decompress_generic( /* copy literals */ cpy = op + length; - if (((endOnInput) && ((cpy > (partialDecoding ? oexit : oend - MFLIMIT)) + LZ4_STATIC_ASSERT(MFLIMIT >= WILDCOPYLENGTH); + + if (((endOnInput) && ((cpy > oend - MFLIMIT) || (ip + length > iend - (2 + 1 + LASTLITERALS)))) || ((!endOnInput) && (cpy > oend - WILDCOPYLENGTH))) { if (partialDecoding) { if (cpy > oend) { /* - * Error : - * write attempt beyond end of output buffer + * Partial decoding : + * stop in the middle of literal segment */ - goto _output_error; + cpy = oend; + length = oend - op; } if ((endOnInput) && (ip + length > iend)) { @@ -184,29 +263,43 @@ static FORCE_INLINE int LZ4_decompress_generic( memcpy(op, ip, length); ip += length; op += length; - /* Necessarily EOF, due to parsing restrictions */ - break; - } - LZ4_wildCopy(op, ip, cpy); - ip += length; - op = cpy; + /* Necessarily EOF, due to parsing restrictions */ + if (!partialDecoding || (cpy == oend)) + break; + } else { + /* may overwrite up to WILDCOPYLENGTH beyond cpy */ + LZ4_wildCopy(op, ip, cpy); + ip += length; + op = cpy; + } /* get offset */ offset = LZ4_readLE16(ip); ip += 2; match = op - offset; - if ((checkOffset) && (unlikely(match < lowLimit))) { + /* get matchlength */ + length = token & ML_MASK; + +_copy_match: + if ((checkOffset) && (unlikely(match + dictSize < lowPrefix))) { /* Error : offset outside buffers */ goto _output_error; } /* costs ~1%; silence an msan warning when offset == 0 */ - LZ4_write32(op, (U32)offset); + /* + * note : when partialDecoding, there is no guarantee that + * at least 4 bytes remain available in output buffer + */ + if (!partialDecoding) { + assert(oend > op); + assert(oend - op >= 4); + + LZ4_write32(op, (U32)offset); + } - /* get matchlength */ - length = token & ML_MASK; if (length == ML_MASK) { unsigned int s; @@ -221,7 +314,7 @@ static FORCE_INLINE int LZ4_decompress_generic( if ((safeDecode) && unlikely( - (size_t)(op + length) < (size_t)op)) { + (uptrval)(op) + length < (uptrval)op)) { /* overflow detection */ goto _output_error; } @@ -229,24 +322,26 @@ static FORCE_INLINE int LZ4_decompress_generic( length += MINMATCH; - /* check external dictionary */ + /* match starting within external dictionary */ if ((dict == usingExtDict) && (match < lowPrefix)) { if (unlikely(op + length > oend - LASTLITERALS)) { /* doesn't respect parsing restriction */ - goto _output_error; + if (!partialDecoding) + goto _output_error; + length = min(length, (size_t)(oend - op)); } if (length <= (size_t)(lowPrefix - match)) { /* - * match can be copied as a single segment - * from external dictionary + * match fits entirely within external + * dictionary : just copy */ memmove(op, dictEnd - (lowPrefix - match), length); op += length; } else { /* - * match encompass external + * match stretches into both external * dictionary and current block */ size_t const copySize = (size_t)(lowPrefix - match); @@ -254,7 +349,6 @@ static FORCE_INLINE int LZ4_decompress_generic( memcpy(op, dictEnd - copySize, copySize); op += copySize; - if (restSize > (size_t)(op - lowPrefix)) { /* overlap copy */ BYTE * const endOfMatch = op + restSize; @@ -267,23 +361,44 @@ static FORCE_INLINE int LZ4_decompress_generic( op += restSize; } } - continue; } /* copy match within block */ cpy = op + length; - if (unlikely(offset < 8)) { - const int dec64 = dec64table[offset]; + /* + * partialDecoding : + * may not respect endBlock parsing restrictions + */ + assert(op <= oend); + if (partialDecoding && + (cpy > oend - MATCH_SAFEGUARD_DISTANCE)) { + size_t const mlen = min(length, (size_t)(oend - op)); + const BYTE * const matchEnd = match + mlen; + BYTE * const copyEnd = op + mlen; + if (matchEnd > op) { + /* overlap copy */ + while (op < copyEnd) + *op++ = *match++; + } else { + memcpy(op, match, mlen); + } + op = copyEnd; + if (op == oend) + break; + continue; + } + + if (unlikely(offset < 8)) { op[0] = match[0]; op[1] = match[1]; op[2] = match[2]; op[3] = match[3]; - match += dec32table[offset]; + match += inc32table[offset]; memcpy(op + 4, match, 4); - match -= dec64; + match -= dec64table[offset]; } else { LZ4_copy8(op, match); match += 8; @@ -291,7 +406,7 @@ static FORCE_INLINE int LZ4_decompress_generic( op += 8; - if (unlikely(cpy > oend - 12)) { + if (unlikely(cpy > oend - MATCH_SAFEGUARD_DISTANCE)) { BYTE * const oCopyLimit = oend - (WILDCOPYLENGTH - 1); if (cpy > oend - LASTLITERALS) { @@ -307,60 +422,139 @@ static FORCE_INLINE int LZ4_decompress_generic( match += oCopyLimit - op; op = oCopyLimit; } - while (op < cpy) *op++ = *match++; } else { LZ4_copy8(op, match); - if (length > 16) LZ4_wildCopy(op + 8, match + 8, cpy); } - - op = cpy; /* correction */ + op = cpy; /* wildcopy correction */ } /* end of decoding */ if (endOnInput) { /* Nb of output bytes decoded */ - return (int) (((char *)op) - dest); + return (int) (((char *)op) - dst); } else { /* Nb of input bytes read */ - return (int) (((const char *)ip) - source); + return (int) (((const char *)ip) - src); } /* Overflow error detected */ _output_error: - return -1; + return (int) (-(((const char *)ip) - src)) - 1; } int LZ4_decompress_safe(const char *source, char *dest, int compressedSize, int maxDecompressedSize) { - return LZ4_decompress_generic(source, dest, compressedSize, - maxDecompressedSize, endOnInputSize, full, 0, - noDict, (BYTE *)dest, NULL, 0); + return LZ4_decompress_generic(source, dest, + compressedSize, maxDecompressedSize, + endOnInputSize, decode_full_block, + noDict, (BYTE *)dest, NULL, 0); } -int LZ4_decompress_safe_partial(const char *source, char *dest, - int compressedSize, int targetOutputSize, int maxDecompressedSize) +int LZ4_decompress_safe_partial(const char *src, char *dst, + int compressedSize, int targetOutputSize, int dstCapacity) { - return LZ4_decompress_generic(source, dest, compressedSize, - maxDecompressedSize, endOnInputSize, partial, - targetOutputSize, noDict, (BYTE *)dest, NULL, 0); + dstCapacity = min(targetOutputSize, dstCapacity); + return LZ4_decompress_generic(src, dst, compressedSize, dstCapacity, + endOnInputSize, partial_decode, + noDict, (BYTE *)dst, NULL, 0); } int LZ4_decompress_fast(const char *source, char *dest, int originalSize) { return LZ4_decompress_generic(source, dest, 0, originalSize, - endOnOutputSize, full, 0, withPrefix64k, - (BYTE *)(dest - 64 * KB), NULL, 64 * KB); + endOnOutputSize, decode_full_block, + withPrefix64k, + (BYTE *)dest - 64 * KB, NULL, 0); } +/* ===== Instantiate a few more decoding cases, used more than once. ===== */ + +int LZ4_decompress_safe_withPrefix64k(const char *source, char *dest, + int compressedSize, int maxOutputSize) +{ + return LZ4_decompress_generic(source, dest, + compressedSize, maxOutputSize, + endOnInputSize, decode_full_block, + withPrefix64k, + (BYTE *)dest - 64 * KB, NULL, 0); +} + +static int LZ4_decompress_safe_withSmallPrefix(const char *source, char *dest, + int compressedSize, + int maxOutputSize, + size_t prefixSize) +{ + return LZ4_decompress_generic(source, dest, + compressedSize, maxOutputSize, + endOnInputSize, decode_full_block, + noDict, + (BYTE *)dest - prefixSize, NULL, 0); +} + +int LZ4_decompress_safe_forceExtDict(const char *source, char *dest, + int compressedSize, int maxOutputSize, + const void *dictStart, size_t dictSize) +{ + return LZ4_decompress_generic(source, dest, + compressedSize, maxOutputSize, + endOnInputSize, decode_full_block, + usingExtDict, (BYTE *)dest, + (const BYTE *)dictStart, dictSize); +} + +static int LZ4_decompress_fast_extDict(const char *source, char *dest, + int originalSize, + const void *dictStart, size_t dictSize) +{ + return LZ4_decompress_generic(source, dest, + 0, originalSize, + endOnOutputSize, decode_full_block, + usingExtDict, (BYTE *)dest, + (const BYTE *)dictStart, dictSize); +} + +/* + * The "double dictionary" mode, for use with e.g. ring buffers: the first part + * of the dictionary is passed as prefix, and the second via dictStart + dictSize. + * These routines are used only once, in LZ4_decompress_*_continue(). + */ +static FORCE_INLINE +int LZ4_decompress_safe_doubleDict(const char *source, char *dest, + int compressedSize, int maxOutputSize, + size_t prefixSize, + const void *dictStart, size_t dictSize) +{ + return LZ4_decompress_generic(source, dest, + compressedSize, maxOutputSize, + endOnInputSize, decode_full_block, + usingExtDict, (BYTE *)dest - prefixSize, + (const BYTE *)dictStart, dictSize); +} + +static FORCE_INLINE +int LZ4_decompress_fast_doubleDict(const char *source, char *dest, + int originalSize, size_t prefixSize, + const void *dictStart, size_t dictSize) +{ + return LZ4_decompress_generic(source, dest, + 0, originalSize, + endOnOutputSize, decode_full_block, + usingExtDict, (BYTE *)dest - prefixSize, + (const BYTE *)dictStart, dictSize); +} + +/* ===== streaming decompression functions ===== */ + int LZ4_setStreamDecode(LZ4_streamDecode_t *LZ4_streamDecode, const char *dictionary, int dictSize) { - LZ4_streamDecode_t_internal *lz4sd = (LZ4_streamDecode_t_internal *) LZ4_streamDecode; + LZ4_streamDecode_t_internal *lz4sd = + &LZ4_streamDecode->internal_donotuse; lz4sd->prefixSize = (size_t) dictSize; lz4sd->prefixEnd = (const BYTE *) dictionary + dictSize; @@ -382,35 +576,51 @@ int LZ4_setStreamDecode(LZ4_streamDecode_t *LZ4_streamDecode, int LZ4_decompress_safe_continue(LZ4_streamDecode_t *LZ4_streamDecode, const char *source, char *dest, int compressedSize, int maxOutputSize) { - LZ4_streamDecode_t_internal *lz4sd = &LZ4_streamDecode->internal_donotuse; + LZ4_streamDecode_t_internal *lz4sd = + &LZ4_streamDecode->internal_donotuse; int result; - if (lz4sd->prefixEnd == (BYTE *)dest) { - result = LZ4_decompress_generic(source, dest, - compressedSize, - maxOutputSize, - endOnInputSize, full, 0, - usingExtDict, lz4sd->prefixEnd - lz4sd->prefixSize, - lz4sd->externalDict, - lz4sd->extDictSize); - + if (lz4sd->prefixSize == 0) { + /* The first call, no dictionary yet. */ + assert(lz4sd->extDictSize == 0); + result = LZ4_decompress_safe(source, dest, + compressedSize, maxOutputSize); + if (result <= 0) + return result; + lz4sd->prefixSize = result; + lz4sd->prefixEnd = (BYTE *)dest + result; + } else if (lz4sd->prefixEnd == (BYTE *)dest) { + /* They're rolling the current segment. */ + if (lz4sd->prefixSize >= 64 * KB - 1) + result = LZ4_decompress_safe_withPrefix64k(source, dest, + compressedSize, maxOutputSize); + else if (lz4sd->extDictSize == 0) + result = LZ4_decompress_safe_withSmallPrefix(source, + dest, compressedSize, maxOutputSize, + lz4sd->prefixSize); + else + result = LZ4_decompress_safe_doubleDict(source, dest, + compressedSize, maxOutputSize, + lz4sd->prefixSize, + lz4sd->externalDict, lz4sd->extDictSize); if (result <= 0) return result; - lz4sd->prefixSize += result; - lz4sd->prefixEnd += result; + lz4sd->prefixEnd += result; } else { + /* + * The buffer wraps around, or they're + * switching to another buffer. + */ lz4sd->extDictSize = lz4sd->prefixSize; lz4sd->externalDict = lz4sd->prefixEnd - lz4sd->extDictSize; - result = LZ4_decompress_generic(source, dest, + result = LZ4_decompress_safe_forceExtDict(source, dest, compressedSize, maxOutputSize, - endOnInputSize, full, 0, - usingExtDict, (BYTE *)dest, lz4sd->externalDict, lz4sd->extDictSize); if (result <= 0) return result; lz4sd->prefixSize = result; - lz4sd->prefixEnd = (BYTE *)dest + result; + lz4sd->prefixEnd = (BYTE *)dest + result; } return result; @@ -422,75 +632,66 @@ int LZ4_decompress_fast_continue(LZ4_streamDecode_t *LZ4_streamDecode, LZ4_streamDecode_t_internal *lz4sd = &LZ4_streamDecode->internal_donotuse; int result; - if (lz4sd->prefixEnd == (BYTE *)dest) { - result = LZ4_decompress_generic(source, dest, 0, originalSize, - endOnOutputSize, full, 0, - usingExtDict, - lz4sd->prefixEnd - lz4sd->prefixSize, - lz4sd->externalDict, lz4sd->extDictSize); - - if (result <= 0) - return result; - - lz4sd->prefixSize += originalSize; - lz4sd->prefixEnd += originalSize; - } else { - lz4sd->extDictSize = lz4sd->prefixSize; - lz4sd->externalDict = lz4sd->prefixEnd - lz4sd->extDictSize; - result = LZ4_decompress_generic(source, dest, 0, originalSize, - endOnOutputSize, full, 0, - usingExtDict, (BYTE *)dest, - lz4sd->externalDict, lz4sd->extDictSize); + if (lz4sd->prefixSize == 0) { + assert(lz4sd->extDictSize == 0); + result = LZ4_decompress_fast(source, dest, originalSize); if (result <= 0) return result; lz4sd->prefixSize = originalSize; - lz4sd->prefixEnd = (BYTE *)dest + originalSize; + lz4sd->prefixEnd = (BYTE *)dest + originalSize; + } else if (lz4sd->prefixEnd == (BYTE *)dest) { + if (lz4sd->prefixSize >= 64 * KB - 1 || + lz4sd->extDictSize == 0) + result = LZ4_decompress_fast(source, dest, + originalSize); + else + result = LZ4_decompress_fast_doubleDict(source, dest, + originalSize, lz4sd->prefixSize, + lz4sd->externalDict, lz4sd->extDictSize); + if (result <= 0) + return result; + lz4sd->prefixSize += originalSize; + lz4sd->prefixEnd += originalSize; + } else { + lz4sd->extDictSize = lz4sd->prefixSize; + lz4sd->externalDict = lz4sd->prefixEnd - lz4sd->extDictSize; + result = LZ4_decompress_fast_extDict(source, dest, + originalSize, lz4sd->externalDict, lz4sd->extDictSize); + if (result <= 0) + return result; + lz4sd->prefixSize = originalSize; + lz4sd->prefixEnd = (BYTE *)dest + originalSize; } - return result; } -/* - * Advanced decoding functions : - * *_usingDict() : - * These decoding functions work the same as "_continue" ones, - * the dictionary must be explicitly provided within parameters - */ -static FORCE_INLINE int LZ4_decompress_usingDict_generic(const char *source, - char *dest, int compressedSize, int maxOutputSize, int safe, - const char *dictStart, int dictSize) +int LZ4_decompress_safe_usingDict(const char *source, char *dest, + int compressedSize, int maxOutputSize, + const char *dictStart, int dictSize) { if (dictSize == 0) - return LZ4_decompress_generic(source, dest, - compressedSize, maxOutputSize, safe, full, 0, - noDict, (BYTE *)dest, NULL, 0); - if (dictStart + dictSize == dest) { - if (dictSize >= (int)(64 * KB - 1)) - return LZ4_decompress_generic(source, dest, - compressedSize, maxOutputSize, safe, full, 0, - withPrefix64k, (BYTE *)dest - 64 * KB, NULL, 0); - return LZ4_decompress_generic(source, dest, compressedSize, - maxOutputSize, safe, full, 0, noDict, - (BYTE *)dest - dictSize, NULL, 0); + return LZ4_decompress_safe(source, dest, + compressedSize, maxOutputSize); + if (dictStart+dictSize == dest) { + if (dictSize >= 64 * KB - 1) + return LZ4_decompress_safe_withPrefix64k(source, dest, + compressedSize, maxOutputSize); + return LZ4_decompress_safe_withSmallPrefix(source, dest, + compressedSize, maxOutputSize, dictSize); } - return LZ4_decompress_generic(source, dest, compressedSize, - maxOutputSize, safe, full, 0, usingExtDict, - (BYTE *)dest, (const BYTE *)dictStart, dictSize); -} - -int LZ4_decompress_safe_usingDict(const char *source, char *dest, - int compressedSize, int maxOutputSize, - const char *dictStart, int dictSize) -{ - return LZ4_decompress_usingDict_generic(source, dest, - compressedSize, maxOutputSize, 1, dictStart, dictSize); + return LZ4_decompress_safe_forceExtDict(source, dest, + compressedSize, maxOutputSize, dictStart, dictSize); } int LZ4_decompress_fast_usingDict(const char *source, char *dest, - int originalSize, const char *dictStart, int dictSize) + int originalSize, + const char *dictStart, int dictSize) { - return LZ4_decompress_usingDict_generic(source, dest, 0, - originalSize, 0, dictStart, dictSize); + if (dictSize == 0 || dictStart + dictSize == dest) + return LZ4_decompress_fast(source, dest, originalSize); + + return LZ4_decompress_fast_extDict(source, dest, originalSize, + dictStart, dictSize); } #ifndef STATIC diff --git a/lib/lz4/lz4defs.h b/lib/lz4/lz4defs.h index 00a0b58a0871..1a7fa9d9170f 100644 --- a/lib/lz4/lz4defs.h +++ b/lib/lz4/lz4defs.h @@ -75,6 +75,11 @@ typedef uintptr_t uptrval; #define WILDCOPYLENGTH 8 #define LASTLITERALS 5 #define MFLIMIT (WILDCOPYLENGTH + MINMATCH) +/* + * ensure it's possible to write 2 x wildcopyLength + * without overflowing output buffer + */ +#define MATCH_SAFEGUARD_DISTANCE ((2 * WILDCOPYLENGTH) - MINMATCH) /* Increase this value ==> compression run slower on incompressible data */ #define LZ4_SKIPTRIGGER 6 @@ -222,6 +227,8 @@ typedef enum { noDict = 0, withPrefix64k, usingExtDict } dict_directive; typedef enum { noDictIssue = 0, dictSmall } dictIssue_directive; typedef enum { endOnOutputSize = 0, endOnInputSize = 1 } endCondition_directive; -typedef enum { full = 0, partial = 1 } earlyEnd_directive; +typedef enum { decode_full_block = 0, partial_decode = 1 } earlyEnd_directive; + +#define LZ4_STATIC_ASSERT(c) BUILD_BUG_ON(!(c)) #endif From ba653b10fde5207f13c19b903a78cd02ebf1caa3 Mon Sep 17 00:00:00 2001 From: Nick Terrell Date: Fri, 14 Aug 2020 17:30:10 -0700 Subject: [PATCH 02/74] lz4: fix kernel decompression speed This patch replaces all memcpy() calls with LZ4_memcpy() which calls __builtin_memcpy() so the compiler can inline it. LZ4 relies heavily on memcpy() with a constant size being inlined. In x86 and i386 pre-boot environments memcpy() cannot be inlined because memcpy() doesn't get defined as __builtin_memcpy(). An equivalent patch has been applied upstream so that the next import won't lose this change [1]. I've measured the kernel decompression speed using QEMU before and after this patch for the x86_64 and i386 architectures. The speed-up is about 10x as shown below. Code Arch Kernel Size Time Speed v5.8 x86_64 11504832 B 148 ms 79 MB/s patch x86_64 11503872 B 13 ms 885 MB/s v5.8 i386 9621216 B 91 ms 106 MB/s patch i386 9620224 B 10 ms 962 MB/s I also measured the time to decompress the initramfs on x86_64, i386, and arm. All three show the same decompression speed before and after, as expected. [1] https://github.com/lz4/lz4/pull/890 Signed-off-by: Nick Terrell Signed-off-by: Andrew Morton Cc: Yann Collet Cc: Gao Xiang Cc: Sven Schmidt <4sschmid@informatik.uni-hamburg.de> Cc: Greg Kroah-Hartman Cc: Ingo Molnar Cc: Arvind Sankar Link: http://lkml.kernel.org/r/20200803194022.2966806-1-nickrterrell@gmail.com Signed-off-by: Linus Torvalds --- lib/lz4/lz4_compress.c | 4 ++-- lib/lz4/lz4_decompress.c | 18 +++++++++--------- lib/lz4/lz4defs.h | 10 ++++++++++ lib/lz4/lz4hc_compress.c | 2 +- 4 files changed, 22 insertions(+), 12 deletions(-) diff --git a/lib/lz4/lz4_compress.c b/lib/lz4/lz4_compress.c index cc7b6d4cc7c7..90bb67994688 100644 --- a/lib/lz4/lz4_compress.c +++ b/lib/lz4/lz4_compress.c @@ -446,7 +446,7 @@ static FORCE_INLINE int LZ4_compress_generic( *op++ = (BYTE)(lastRun << ML_BITS); } - memcpy(op, anchor, lastRun); + LZ4_memcpy(op, anchor, lastRun); op += lastRun; } @@ -708,7 +708,7 @@ static int LZ4_compress_destSize_generic( } else { *op++ = (BYTE)(lastRunSize<= 8) && (dict == withPrefix64k || match >= lowPrefix)) { /* Copy the match. */ - memcpy(op + 0, match + 0, 8); - memcpy(op + 8, match + 8, 8); - memcpy(op + 16, match + 16, 2); + LZ4_memcpy(op + 0, match + 0, 8); + LZ4_memcpy(op + 8, match + 8, 8); + LZ4_memcpy(op + 16, match + 16, 2); op += length + MINMATCH; /* Both stages worked, load the next token. */ continue; @@ -260,7 +260,7 @@ static FORCE_INLINE int LZ4_decompress_generic( } } - memcpy(op, ip, length); + LZ4_memcpy(op, ip, length); ip += length; op += length; @@ -347,7 +347,7 @@ static FORCE_INLINE int LZ4_decompress_generic( size_t const copySize = (size_t)(lowPrefix - match); size_t const restSize = length - copySize; - memcpy(op, dictEnd - copySize, copySize); + LZ4_memcpy(op, dictEnd - copySize, copySize); op += copySize; if (restSize > (size_t)(op - lowPrefix)) { /* overlap copy */ @@ -357,7 +357,7 @@ static FORCE_INLINE int LZ4_decompress_generic( while (op < endOfMatch) *op++ = *copyFrom++; } else { - memcpy(op, lowPrefix, restSize); + LZ4_memcpy(op, lowPrefix, restSize); op += restSize; } } @@ -383,7 +383,7 @@ static FORCE_INLINE int LZ4_decompress_generic( while (op < copyEnd) *op++ = *match++; } else { - memcpy(op, match, mlen); + LZ4_memcpy(op, match, mlen); } op = copyEnd; if (op == oend) @@ -397,7 +397,7 @@ static FORCE_INLINE int LZ4_decompress_generic( op[2] = match[2]; op[3] = match[3]; match += inc32table[offset]; - memcpy(op + 4, match, 4); + LZ4_memcpy(op + 4, match, 4); match -= dec64table[offset]; } else { LZ4_copy8(op, match); diff --git a/lib/lz4/lz4defs.h b/lib/lz4/lz4defs.h index 1a7fa9d9170f..c91dd96ef629 100644 --- a/lib/lz4/lz4defs.h +++ b/lib/lz4/lz4defs.h @@ -137,6 +137,16 @@ static FORCE_INLINE void LZ4_writeLE16(void *memPtr, U16 value) return put_unaligned_le16(value, memPtr); } +/* + * LZ4 relies on memcpy with a constant size being inlined. In freestanding + * environments, the compiler can't assume the implementation of memcpy() is + * standard compliant, so apply its specialized memcpy() inlining logic. When + * possible, use __builtin_memcpy() to tell the compiler to analyze memcpy() + * as-if it were standard compliant, so it can inline it in freestanding + * environments. This is needed when decompressing the Linux Kernel, for example. + */ +#define LZ4_memcpy(dst, src, size) __builtin_memcpy(dst, src, size) + static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) { #if LZ4_ARCH64 diff --git a/lib/lz4/lz4hc_compress.c b/lib/lz4/lz4hc_compress.c index 176f03b83e56..ccbf0e89d713 100644 --- a/lib/lz4/lz4hc_compress.c +++ b/lib/lz4/lz4hc_compress.c @@ -570,7 +570,7 @@ static int LZ4HC_compress_generic( *op++ = (BYTE) lastRun; } else *op++ = (BYTE)(lastRun< Date: Tue, 15 Dec 2020 20:44:03 -0800 Subject: [PATCH 03/74] lib/lz4: explicitly support in-place decompression LZ4 final literal copy could be overlapped when doing in-place decompression, so it's unsafe to just use memcpy() on an optimized memcpy approach but memmove() instead. Upstream LZ4 has updated this years ago [1] (and the impact is non-sensible [2] plus only a few bytes remain), this commit just synchronizes LZ4 upstream code to the kernel side as well. It can be observed as EROFS in-place decompression failure on specific files when X86_FEATURE_ERMS is unsupported, memcpy() optimization of commit 59daa706fbec ("x86, mem: Optimize memcpy by avoiding memory false dependece") will be enabled then. Currently most modern x86-CPUs support ERMS, these CPUs just use "rep movsb" approach so no problem at all. However, it can still be verified with forcely disabling ERMS feature... arch/x86/lib/memcpy_64.S: ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \ - "jmp memcpy_erms", X86_FEATURE_ERMS + "jmp memcpy_orig", X86_FEATURE_ERMS We didn't observe any strange on arm64/arm/x86 platform before since most memcpy() would behave in an increasing address order ("copy upwards" [3]) and it's the correct order of in-place decompression but it really needs an update to memmove() for sure considering it's an undefined behavior according to the standard and some unique optimization already exists in the kernel. [1] https://github.com/lz4/lz4/commit/33cb8518ac385835cc17be9a770b27b40cd0e15b [2] https://github.com/lz4/lz4/pull/717#issuecomment-497818921 [3] https://sourceware.org/bugzilla/show_bug.cgi?id=12518 Link: https://lkml.kernel.org/r/20201122030749.2698994-1-hsiangkao@redhat.com Signed-off-by: Gao Xiang Reviewed-by: Nick Terrell Cc: Yann Collet Cc: Miao Xie Cc: Chao Yu Cc: Li Guifu Cc: Guo Xuenan Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- lib/lz4/lz4_decompress.c | 6 +++++- lib/lz4/lz4defs.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/lib/lz4/lz4_decompress.c b/lib/lz4/lz4_decompress.c index fea6ad57cab7..cda8b794da04 100644 --- a/lib/lz4/lz4_decompress.c +++ b/lib/lz4/lz4_decompress.c @@ -260,7 +260,11 @@ static FORCE_INLINE int LZ4_decompress_generic( } } - LZ4_memcpy(op, ip, length); + /* + * supports overlapping memory regions; only matters + * for in-place decompression scenarios + */ + LZ4_memmove(op, ip, length); ip += length; op += length; diff --git a/lib/lz4/lz4defs.h b/lib/lz4/lz4defs.h index c91dd96ef629..673bd206aa98 100644 --- a/lib/lz4/lz4defs.h +++ b/lib/lz4/lz4defs.h @@ -146,6 +146,7 @@ static FORCE_INLINE void LZ4_writeLE16(void *memPtr, U16 value) * environments. This is needed when decompressing the Linux Kernel, for example. */ #define LZ4_memcpy(dst, src, size) __builtin_memcpy(dst, src, size) +#define LZ4_memmove(dst, src, size) __builtin_memmove(dst, src, size) static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) { From 4cbdeb6216e440bddb871d1bffd0d66f7752fd80 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 25 Aug 2021 11:42:03 +0800 Subject: [PATCH 04/74] erofs: sync up with kernel 5.10 Backport 5.10 LTS erofs to 4.19. Signed-off-by: Gao Xiang --- drivers/staging/erofs/Kconfig | 97 +- drivers/staging/erofs/Makefile | 10 +- drivers/staging/erofs/compress.h | 58 + drivers/staging/erofs/data.c | 224 +-- drivers/staging/erofs/decompressor.c | 344 ++++ drivers/staging/erofs/dir.c | 78 +- drivers/staging/erofs/erofs_fs.h | 278 +-- drivers/staging/erofs/inode.c | 415 ++-- drivers/staging/erofs/internal.h | 491 ++--- drivers/staging/erofs/lz4defs.h | 227 --- drivers/staging/erofs/namei.c | 82 +- drivers/staging/erofs/super.c | 592 +++--- .../erofs/{include/linux => }/tagptr.h | 15 +- drivers/staging/erofs/unzip_lz4.c | 251 --- drivers/staging/erofs/unzip_vle.c | 1695 ----------------- drivers/staging/erofs/unzip_vle_lz4.c | 210 -- drivers/staging/erofs/utils.c | 225 +-- drivers/staging/erofs/xattr.c | 254 ++- drivers/staging/erofs/xattr.h | 78 +- drivers/staging/erofs/zdata.c | 1370 +++++++++++++ drivers/staging/erofs/zdata.h | 188 ++ drivers/staging/erofs/zmap.c | 477 +++++ .../erofs/{unzip_pagevec.h => zpvec.h} | 71 +- .../include => include}/trace/events/erofs.h | 39 +- 24 files changed, 3827 insertions(+), 3942 deletions(-) create mode 100644 drivers/staging/erofs/compress.h create mode 100644 drivers/staging/erofs/decompressor.c delete mode 100644 drivers/staging/erofs/lz4defs.h rename drivers/staging/erofs/{include/linux => }/tagptr.h (93%) delete mode 100644 drivers/staging/erofs/unzip_lz4.c delete mode 100644 drivers/staging/erofs/unzip_vle.c delete mode 100644 drivers/staging/erofs/unzip_vle_lz4.c create mode 100644 drivers/staging/erofs/zdata.c create mode 100644 drivers/staging/erofs/zdata.h create mode 100644 drivers/staging/erofs/zmap.c rename drivers/staging/erofs/{unzip_pagevec.h => zpvec.h} (67%) rename {drivers/staging/erofs/include => include}/trace/events/erofs.h (85%) diff --git a/drivers/staging/erofs/Kconfig b/drivers/staging/erofs/Kconfig index 663b755bf2fb..74b0aaa7114c 100644 --- a/drivers/staging/erofs/Kconfig +++ b/drivers/staging/erofs/Kconfig @@ -1,19 +1,20 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: GPL-2.0-only config EROFS_FS tristate "EROFS filesystem support" depends on BLOCK + select LIBCRC32C help - EROFS(Enhanced Read-Only File System) is a lightweight + EROFS (Enhanced Read-Only File System) is a lightweight read-only file system with modern designs (eg. page-sized blocks, inline xattrs/data, etc.) for scenarios which need - high-performance read-only requirements, eg. firmwares in - mobile phone or LIVECDs. + high-performance read-only requirements, e.g. Android OS + for mobile phones and LIVECDs. - It also provides VLE compression support, focusing on - random read improvements, keeping relatively lower - compression ratios, which is useful for high-performance - devices with limited memory and ROM space. + It also provides fixed-sized output compression support, + which improves storage density, keeps relatively higher + compression ratios, which is more useful to achieve high + performance for embedded devices with limited memory. If unsure, say N. @@ -21,8 +22,9 @@ config EROFS_FS_DEBUG bool "EROFS debugging feature" depends on EROFS_FS help - Print EROFS debugging messages and enable more BUG_ONs - which check the filesystem consistency aggressively. + Print debugging messages and enable more BUG_ONs which check + filesystem consistency and find potential issues aggressively, + which can be used for Android eng build, for example. For daily use, say N. @@ -54,6 +56,7 @@ config EROFS_FS_POSIX_ACL config EROFS_FS_SECURITY bool "EROFS Security Labels" depends on EROFS_FS_XATTR + default y help Security labels provide an access control facility to support Linux Security Models (LSMs) accepted by AppArmor, SELinux, Smack and TOMOYO @@ -63,29 +66,15 @@ config EROFS_FS_SECURITY If you are not using a security module, say N. -config EROFS_FS_USE_VM_MAP_RAM - bool "EROFS VM_MAP_RAM Support" - depends on EROFS_FS - help - use vm_map_ram/vm_unmap_ram instead of vmap/vunmap. - - If you don't know what these are, say N. - -config EROFS_FAULT_INJECTION - bool "EROFS fault injection facility" - depends on EROFS_FS - help - Test EROFS to inject faults such as ENOMEM, EIO, and so on. - If unsure, say N. - config EROFS_FS_ZIP - bool "EROFS Data Compresssion Support" + bool "EROFS Data Compression Support" depends on EROFS_FS + select LZ4_DECOMPRESS + default y help - Currently we support VLE Compression only. - Play at your own risk. + Enable fixed-sized output compression for EROFS. - If you don't want to use compression feature, say N. + If you don't want to enable compression feature, say N. config EROFS_FS_CLUSTER_PAGE_LIMIT int "EROFS Cluster Pages Hard Limit" @@ -93,49 +82,11 @@ config EROFS_FS_CLUSTER_PAGE_LIMIT range 1 256 default "1" help - Indicates VLE compressed pages hard limit of a - compressed cluster. + Indicates maximum # of pages of a compressed + physical cluster. - For example, if files of a image are compressed - into 8k-unit, the hard limit should not be less - than 2. Otherwise, the image cannot be mounted - correctly on this kernel. - -choice - prompt "EROFS VLE Data Decompression mode" - depends on EROFS_FS_ZIP - default EROFS_FS_ZIP_CACHE_BIPOLAR - help - EROFS supports three options for VLE decompression. - "In-place Decompression Only" consumes the minimum memory - with lowest random read. - - "Bipolar Cached Decompression" consumes the maximum memory - with highest random read. - - If unsure, select "Bipolar Cached Decompression" - -config EROFS_FS_ZIP_NO_CACHE - bool "In-place Decompression Only" - help - Read compressed data into page cache and do in-place - decompression directly. - -config EROFS_FS_ZIP_CACHE_UNIPOLAR - bool "Unipolar Cached Decompression" - help - For each request, it caches the last compressed page - for further reading. - It still decompresses in place for the rest compressed pages. - -config EROFS_FS_ZIP_CACHE_BIPOLAR - bool "Bipolar Cached Decompression" - help - For each request, it caches the both end compressed pages - for further reading. - It still decompresses in place for the rest compressed pages. - - Recommended for performance priority. - -endchoice + For example, if files in a image were compressed + into 8k-unit, hard limit should not be configured + less than 2. Otherwise, the image will be refused + to mount on this kernel. diff --git a/drivers/staging/erofs/Makefile b/drivers/staging/erofs/Makefile index 9a766eb7ed75..46f2aa4ba46c 100644 --- a/drivers/staging/erofs/Makefile +++ b/drivers/staging/erofs/Makefile @@ -1,13 +1,11 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: GPL-2.0-only -EROFS_VERSION = "1.0pre1" +EROFS_VERSION = "1.0" -ccflags-y += -Wall -DEROFS_VERSION=\"$(EROFS_VERSION)\" +ccflags-y += -DEROFS_VERSION=\"$(EROFS_VERSION)\" obj-$(CONFIG_EROFS_FS) += erofs.o -# staging requirement: to be self-contained in its own directory -ccflags-y += -I$(src)/include erofs-objs := super.o inode.o data.o namei.o dir.o utils.o erofs-$(CONFIG_EROFS_FS_XATTR) += xattr.o -erofs-$(CONFIG_EROFS_FS_ZIP) += unzip_vle.o unzip_lz4.o unzip_vle_lz4.o +erofs-$(CONFIG_EROFS_FS_ZIP) += decompressor.o zmap.o zdata.o diff --git a/drivers/staging/erofs/compress.h b/drivers/staging/erofs/compress.h new file mode 100644 index 000000000000..e9b1aa0afe0e --- /dev/null +++ b/drivers/staging/erofs/compress.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 HUAWEI, Inc. + * https://www.huawei.com/ + */ +#ifndef __EROFS_FS_COMPRESS_H +#define __EROFS_FS_COMPRESS_H + +#include "internal.h" + +enum { + Z_EROFS_COMPRESSION_SHIFTED = Z_EROFS_COMPRESSION_MAX, + Z_EROFS_COMPRESSION_RUNTIME_MAX +}; + +struct z_erofs_decompress_req { + struct super_block *sb; + struct page **in, **out; + + unsigned short pageofs_out; + unsigned int inputsize, outputsize; + + /* indicate the algorithm will be used for decompression */ + unsigned int alg; + bool inplace_io, partial_decoding; +}; + +/* + * - 0x5A110C8D ('sallocated', Z_EROFS_MAPPING_STAGING) - + * used to mark temporary allocated pages from other + * file/cached pages and NULL mapping pages. + */ +#define Z_EROFS_MAPPING_STAGING ((void *)0x5A110C8D) + +/* check if a page is marked as staging */ +static inline bool z_erofs_page_is_staging(struct page *page) +{ + return page->mapping == Z_EROFS_MAPPING_STAGING; +} + +static inline bool z_erofs_put_stagingpage(struct list_head *pagepool, + struct page *page) +{ + if (!z_erofs_page_is_staging(page)) + return false; + + /* staging pages should not be used by others at the same time */ + if (page_ref_count(page) > 1) + put_page(page); + else + list_add(&page->lru, pagepool); + return true; +} + +int z_erofs_decompress(struct z_erofs_decompress_req *rq, + struct list_head *pagepool); + +#endif diff --git a/drivers/staging/erofs/data.c b/drivers/staging/erofs/data.c index 894e60ecebe2..4f305b68497e 100644 --- a/drivers/staging/erofs/data.c +++ b/drivers/staging/erofs/data.c @@ -1,21 +1,14 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * linux/drivers/staging/erofs/data.c - * * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ #include "internal.h" #include #include -static inline void read_endio(struct bio *bio) +static void erofs_readendio(struct bio *bio) { int i; struct bio_vec *bvec; @@ -27,7 +20,7 @@ static inline void read_endio(struct bio *bio) /* page is already locked */ DBG_BUGON(PageUptodate(page)); - if (unlikely(err)) + if (err) SetPageError(page); else SetPageUptodate(page); @@ -38,70 +31,35 @@ static inline void read_endio(struct bio *bio) bio_put(bio); } -/* prio -- true is used for dir */ -struct page *erofs_get_meta_page(struct super_block *sb, - erofs_blk_t blkaddr, bool prio) +struct page *erofs_get_meta_page(struct super_block *sb, erofs_blk_t blkaddr) { - struct inode *bd_inode = sb->s_bdev->bd_inode; - struct address_space *mapping = bd_inode->i_mapping; + struct address_space *const mapping = sb->s_bdev->bd_inode->i_mapping; struct page *page; -repeat: - page = find_or_create_page(mapping, blkaddr, - /* - * Prefer looping in the allocator rather than here, - * at least that code knows what it's doing. - */ - mapping_gfp_constraint(mapping, ~__GFP_FS) | __GFP_NOFAIL); - - BUG_ON(!page || !PageLocked(page)); - - if (!PageUptodate(page)) { - struct bio *bio; - int err; - - bio = prepare_bio(sb, blkaddr, 1, read_endio); - err = bio_add_page(bio, page, PAGE_SIZE, 0); - BUG_ON(err != PAGE_SIZE); - - __submit_bio(bio, REQ_OP_READ, - REQ_META | (prio ? REQ_PRIO : 0)); - + page = read_cache_page_gfp(mapping, blkaddr, + mapping_gfp_constraint(mapping, ~__GFP_FS)); + /* should already be PageUptodate */ + if (!IS_ERR(page)) lock_page(page); - - /* the page has been truncated by others? */ - if (unlikely(page->mapping != mapping)) { - unlock_page(page); - put_page(page); - goto repeat; - } - - /* more likely a read error */ - if (unlikely(!PageUptodate(page))) { - unlock_page(page); - put_page(page); - - page = ERR_PTR(-EIO); - } - } return page; } static int erofs_map_blocks_flatmode(struct inode *inode, - struct erofs_map_blocks *map, - int flags) + struct erofs_map_blocks *map, + int flags) { int err = 0; erofs_blk_t nblocks, lastblk; u64 offset = map->m_la; - struct erofs_vnode *vi = EROFS_V(inode); + struct erofs_inode *vi = EROFS_I(inode); + bool tailendpacking = (vi->datalayout == EROFS_INODE_FLAT_INLINE); trace_erofs_map_blocks_flatmode_enter(inode, map, flags); nblocks = DIV_ROUND_UP(inode->i_size, PAGE_SIZE); - lastblk = nblocks - is_inode_layout_inline(inode); + lastblk = nblocks - tailendpacking; - if (unlikely(offset >= inode->i_size)) { + if (offset >= inode->i_size) { /* leave out-of-bound access unmapped */ map->m_flags = 0; map->m_plen = 0; @@ -114,7 +72,7 @@ static int erofs_map_blocks_flatmode(struct inode *inode, if (offset < blknr_to_addr(lastblk)) { map->m_pa = blknr_to_addr(vi->raw_blkaddr) + map->m_la; map->m_plen = blknr_to_addr(lastblk) - offset; - } else if (is_inode_layout_inline(inode)) { + } else if (tailendpacking) { /* 2 - inode inline B: inode, [xattrs], inline last blk... */ struct erofs_sb_info *sbi = EROFS_SB(inode->i_sb); @@ -122,17 +80,21 @@ static int erofs_map_blocks_flatmode(struct inode *inode, vi->xattr_isize + erofs_blkoff(map->m_la); map->m_plen = inode->i_size - offset; - /* inline data should locate in one meta block */ + /* inline data should be located in one meta block */ if (erofs_blkoff(map->m_pa) + map->m_plen > PAGE_SIZE) { + erofs_err(inode->i_sb, + "inline data cross block boundary @ nid %llu", + vi->nid); DBG_BUGON(1); - err = -EIO; + err = -EFSCORRUPTED; goto err_out; } map->m_flags |= EROFS_MAP_META; } else { - errln("internal error @ nid: %llu (size %llu), m_la 0x%llx", - vi->nid, inode->i_size, map->m_la); + erofs_err(inode->i_sb, + "internal error @ nid: %llu (size %llu), m_la 0x%llx", + vi->nid, inode->i_size, map->m_la); DBG_BUGON(1); err = -EIO; goto err_out; @@ -146,56 +108,30 @@ static int erofs_map_blocks_flatmode(struct inode *inode, return err; } -#ifdef CONFIG_EROFS_FS_ZIP -extern int z_erofs_map_blocks_iter(struct inode *, - struct erofs_map_blocks *, struct page **, int); -#endif - -int erofs_map_blocks_iter(struct inode *inode, - struct erofs_map_blocks *map, - struct page **mpage_ret, int flags) -{ - /* by default, reading raw data never use erofs_map_blocks_iter */ - if (unlikely(!is_inode_layout_compression(inode))) { - if (*mpage_ret != NULL) - put_page(*mpage_ret); - *mpage_ret = NULL; - - return erofs_map_blocks(inode, map, flags); - } - -#ifdef CONFIG_EROFS_FS_ZIP - return z_erofs_map_blocks_iter(inode, map, mpage_ret, flags); -#else - /* data compression is not available */ - return -ENOTSUPP; -#endif -} - int erofs_map_blocks(struct inode *inode, - struct erofs_map_blocks *map, int flags) + struct erofs_map_blocks *map, int flags) { - if (unlikely(is_inode_layout_compression(inode))) { - struct page *mpage = NULL; - int err; + if (erofs_inode_is_data_compressed(EROFS_I(inode)->datalayout)) { + int err = z_erofs_map_blocks_iter(inode, map, flags); - err = erofs_map_blocks_iter(inode, map, &mpage, flags); - if (mpage != NULL) - put_page(mpage); + if (map->mpage) { + put_page(map->mpage); + map->mpage = NULL; + } return err; } return erofs_map_blocks_flatmode(inode, map, flags); } -static inline struct bio *erofs_read_raw_page( - struct bio *bio, - struct address_space *mapping, - struct page *page, - erofs_off_t *last_block, - unsigned nblocks, - bool ra) +static inline struct bio *erofs_read_raw_page(struct bio *bio, + struct address_space *mapping, + struct page *page, + erofs_off_t *last_block, + unsigned int nblocks, + bool ra) { - struct inode *inode = mapping->host; + struct inode *const inode = mapping->host; + struct super_block *const sb = inode->i_sb; erofs_off_t current_block = (erofs_off_t)page->index; int err; @@ -206,34 +142,28 @@ static inline struct bio *erofs_read_raw_page( goto has_updated; } - if (cleancache_get_page(page) == 0) { - err = 0; - SetPageUptodate(page); - goto has_updated; - } - /* note that for readpage case, bio also equals to NULL */ - if (bio != NULL && - /* not continuous */ - *last_block + 1 != current_block) { + if (bio && + /* not continuous */ + *last_block + 1 != current_block) { submit_bio_retry: - __submit_bio(bio, REQ_OP_READ, 0); + submit_bio(bio); bio = NULL; } - if (bio == NULL) { + if (!bio) { struct erofs_map_blocks map = { .m_la = blknr_to_addr(current_block), }; erofs_blk_t blknr; - unsigned blkoff; + unsigned int blkoff; err = erofs_map_blocks(inode, &map, EROFS_GET_BLOCKS_RAW); - if (unlikely(err)) + if (err) goto err_out; /* zero out the holed page */ - if (unlikely(!(map.m_flags & EROFS_MAP_MAPPED))) { + if (!(map.m_flags & EROFS_MAP_MAPPED)) { zero_user_segment(page, 0, PAGE_SIZE); SetPageUptodate(page); @@ -254,7 +184,7 @@ static inline struct bio *erofs_read_raw_page( DBG_BUGON(map.m_plen > PAGE_SIZE); - ipage = erofs_get_meta_page(inode->i_sb, blknr, 0); + ipage = erofs_get_meta_page(inode->i_sb, blknr); if (IS_ERR(ipage)) { err = PTR_ERR(ipage); @@ -287,7 +217,13 @@ static inline struct bio *erofs_read_raw_page( if (nblocks > BIO_MAX_PAGES) nblocks = BIO_MAX_PAGES; - bio = prepare_bio(inode->i_sb, blknr, nblocks, read_endio); + bio = bio_alloc(GFP_NOIO, nblocks); + + bio->bi_end_io = erofs_readendio; + bio_set_dev(bio, sb->s_bdev); + bio->bi_iter.bi_sector = (sector_t)blknr << + LOG_SECTORS_PER_BLOCK; + bio->bi_opf = REQ_OP_READ | (ra ? REQ_RAHEAD : 0); } err = bio_add_page(bio, page, PAGE_SIZE, 0); @@ -298,7 +234,7 @@ static inline struct bio *erofs_read_raw_page( *last_block = current_block; /* shift in advance in case of it followed by too many gaps */ - if (unlikely(bio->bi_vcnt >= bio->bi_max_vecs)) { + if (bio->bi_iter.bi_size >= bio->bi_max_vecs * PAGE_SIZE) { /* err should reassign to 0 after submitting */ err = 0; goto submit_bio_out; @@ -316,11 +252,10 @@ static inline struct bio *erofs_read_raw_page( unlock_page(page); /* if updated manually, continuous pages has a gap */ - if (bio != NULL) + if (bio) submit_bio_out: - __submit_bio(bio, REQ_OP_READ, 0); - - return unlikely(err) ? ERR_PTR(err) : NULL; + submit_bio(bio); + return err ? ERR_PTR(err) : NULL; } /* @@ -335,7 +270,7 @@ static int erofs_raw_access_readpage(struct file *file, struct page *page) trace_erofs_readpage(page, true); bio = erofs_read_raw_page(NULL, page->mapping, - page, &last_block, 1, false); + page, &last_block, 1, false); if (IS_ERR(bio)) return PTR_ERR(bio); @@ -345,8 +280,9 @@ static int erofs_raw_access_readpage(struct file *file, struct page *page) } static int erofs_raw_access_readpages(struct file *filp, - struct address_space *mapping, - struct list_head *pages, unsigned nr_pages) + struct address_space *mapping, + struct list_head *pages, + unsigned int nr_pages) { erofs_off_t last_block; struct bio *bio = NULL; @@ -363,13 +299,13 @@ static int erofs_raw_access_readpages(struct file *filp, if (!add_to_page_cache_lru(page, mapping, page->index, gfp)) { bio = erofs_read_raw_page(bio, mapping, page, - &last_block, nr_pages, true); + &last_block, nr_pages, true); /* all the page errors are ignored when readahead */ if (IS_ERR(bio)) { pr_err("%s, readahead error at page %lu of nid %llu\n", - __func__, page->index, - EROFS_V(mapping->host)->nid); + __func__, page->index, + EROFS_I(mapping->host)->nid); bio = NULL; } @@ -381,8 +317,28 @@ static int erofs_raw_access_readpages(struct file *filp, DBG_BUGON(!list_empty(pages)); /* the rare case (end in gaps) */ - if (unlikely(bio != NULL)) - __submit_bio(bio, REQ_OP_READ, 0); + if (bio) + submit_bio(bio); + return 0; +} + +static sector_t erofs_bmap(struct address_space *mapping, sector_t block) +{ + struct inode *inode = mapping->host; + struct erofs_map_blocks map = { + .m_la = blknr_to_addr(block), + }; + + if (EROFS_I(inode)->datalayout == EROFS_INODE_FLAT_INLINE) { + erofs_blk_t blks = i_size_read(inode) >> LOG_BLOCK_SIZE; + + if (block >> LOG_SECTORS_PER_BLOCK >= blks) + return 0; + } + + if (!erofs_map_blocks(inode, &map, EROFS_GET_BLOCKS_RAW)) + return erofs_blknr(map.m_pa); + return 0; } @@ -390,5 +346,5 @@ static int erofs_raw_access_readpages(struct file *filp, const struct address_space_operations erofs_raw_access_aops = { .readpage = erofs_raw_access_readpage, .readpages = erofs_raw_access_readpages, + .bmap = erofs_bmap, }; - diff --git a/drivers/staging/erofs/decompressor.c b/drivers/staging/erofs/decompressor.c new file mode 100644 index 000000000000..7822ab4a8262 --- /dev/null +++ b/drivers/staging/erofs/decompressor.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 HUAWEI, Inc. + * https://www.huawei.com/ + */ +#include "compress.h" +#include +#include + +#ifndef LZ4_DISTANCE_MAX /* history window size */ +#define LZ4_DISTANCE_MAX 65535 /* set to maximum value by default */ +#endif + +#define LZ4_MAX_DISTANCE_PAGES (DIV_ROUND_UP(LZ4_DISTANCE_MAX, PAGE_SIZE) + 1) +#ifndef LZ4_DECOMPRESS_INPLACE_MARGIN +#define LZ4_DECOMPRESS_INPLACE_MARGIN(srcsize) (((srcsize) >> 8) + 32) +#endif + +struct z_erofs_decompressor { + /* + * if destpages have sparsed pages, fill them with bounce pages. + * it also check whether destpages indicate continuous physical memory. + */ + int (*prepare_destpages)(struct z_erofs_decompress_req *rq, + struct list_head *pagepool); + int (*decompress)(struct z_erofs_decompress_req *rq, u8 *out); + char *name; +}; + +static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, + struct list_head *pagepool) +{ + const unsigned int nr = + PAGE_ALIGN(rq->pageofs_out + rq->outputsize) >> PAGE_SHIFT; + struct page *availables[LZ4_MAX_DISTANCE_PAGES] = { NULL }; + unsigned long bounced[DIV_ROUND_UP(LZ4_MAX_DISTANCE_PAGES, + BITS_PER_LONG)] = { 0 }; + void *kaddr = NULL; + unsigned int i, j, top; + + top = 0; + for (i = j = 0; i < nr; ++i, ++j) { + struct page *const page = rq->out[i]; + struct page *victim; + + if (j >= LZ4_MAX_DISTANCE_PAGES) + j = 0; + + /* 'valid' bounced can only be tested after a complete round */ + if (test_bit(j, bounced)) { + DBG_BUGON(i < LZ4_MAX_DISTANCE_PAGES); + DBG_BUGON(top >= LZ4_MAX_DISTANCE_PAGES); + availables[top++] = rq->out[i - LZ4_MAX_DISTANCE_PAGES]; + } + + if (page) { + __clear_bit(j, bounced); + if (kaddr) { + if (kaddr + PAGE_SIZE == page_address(page)) + kaddr += PAGE_SIZE; + else + kaddr = NULL; + } else if (!i) { + kaddr = page_address(page); + } + continue; + } + kaddr = NULL; + __set_bit(j, bounced); + + if (top) { + victim = availables[--top]; + get_page(victim); + } else { + victim = erofs_allocpage(pagepool, GFP_KERNEL); + if (!victim) + return -ENOMEM; + victim->mapping = Z_EROFS_MAPPING_STAGING; + } + rq->out[i] = victim; + } + return kaddr ? 1 : 0; +} + +static void *generic_copy_inplace_data(struct z_erofs_decompress_req *rq, + u8 *src, unsigned int pageofs_in) +{ + /* + * if in-place decompression is ongoing, those decompressed + * pages should be copied in order to avoid being overlapped. + */ + struct page **in = rq->in; + u8 *const tmp = erofs_get_pcpubuf(0); + u8 *tmpp = tmp; + unsigned int inlen = rq->inputsize - pageofs_in; + unsigned int count = min_t(uint, inlen, PAGE_SIZE - pageofs_in); + + while (tmpp < tmp + inlen) { + if (!src) + src = kmap_atomic(*in); + memcpy(tmpp, src + pageofs_in, count); + kunmap_atomic(src); + src = NULL; + tmpp += count; + pageofs_in = 0; + count = PAGE_SIZE; + ++in; + } + return tmp; +} + +static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) +{ + unsigned int inputmargin, inlen; + u8 *src; + bool copied, support_0padding; + int ret; + + if (rq->inputsize > PAGE_SIZE) + return -EOPNOTSUPP; + + src = kmap_atomic(*rq->in); + inputmargin = 0; + support_0padding = false; + + /* decompression inplace is only safe when 0padding is enabled */ + if (EROFS_SB(rq->sb)->feature_incompat & + EROFS_FEATURE_INCOMPAT_LZ4_0PADDING) { + support_0padding = true; + + while (!src[inputmargin & ~PAGE_MASK]) + if (!(++inputmargin & ~PAGE_MASK)) + break; + + if (inputmargin >= rq->inputsize) { + kunmap_atomic(src); + return -EIO; + } + } + + copied = false; + inlen = rq->inputsize - inputmargin; + if (rq->inplace_io) { + const uint oend = (rq->pageofs_out + + rq->outputsize) & ~PAGE_MASK; + const uint nr = PAGE_ALIGN(rq->pageofs_out + + rq->outputsize) >> PAGE_SHIFT; + + if (rq->partial_decoding || !support_0padding || + rq->out[nr - 1] != rq->in[0] || + rq->inputsize - oend < + LZ4_DECOMPRESS_INPLACE_MARGIN(inlen)) { + src = generic_copy_inplace_data(rq, src, inputmargin); + inputmargin = 0; + copied = true; + } + } + + /* legacy format could compress extra data in a pcluster. */ + if (rq->partial_decoding || !support_0padding) + ret = LZ4_decompress_safe_partial(src + inputmargin, out, + inlen, rq->outputsize, + rq->outputsize); + else + ret = LZ4_decompress_safe(src + inputmargin, out, + inlen, rq->outputsize); + + if (ret != rq->outputsize) { + erofs_err(rq->sb, "failed to decompress %d in[%u, %u] out[%u]", + ret, inlen, inputmargin, rq->outputsize); + + WARN_ON(1); + print_hex_dump(KERN_DEBUG, "[ in]: ", DUMP_PREFIX_OFFSET, + 16, 1, src + inputmargin, inlen, true); + print_hex_dump(KERN_DEBUG, "[out]: ", DUMP_PREFIX_OFFSET, + 16, 1, out, rq->outputsize, true); + + if (ret >= 0) + memset(out + ret, 0, rq->outputsize - ret); + ret = -EIO; + } + + if (copied) + erofs_put_pcpubuf(src); + else + kunmap_atomic(src); + return ret; +} + +static struct z_erofs_decompressor decompressors[] = { + [Z_EROFS_COMPRESSION_SHIFTED] = { + .name = "shifted" + }, + [Z_EROFS_COMPRESSION_LZ4] = { + .prepare_destpages = z_erofs_lz4_prepare_destpages, + .decompress = z_erofs_lz4_decompress, + .name = "lz4" + }, +}; + +static void copy_from_pcpubuf(struct page **out, const char *dst, + unsigned short pageofs_out, + unsigned int outputsize) +{ + const char *end = dst + outputsize; + const unsigned int righthalf = PAGE_SIZE - pageofs_out; + const char *cur = dst - pageofs_out; + + while (cur < end) { + struct page *const page = *out++; + + if (page) { + char *buf = kmap_atomic(page); + + if (cur >= dst) { + memcpy(buf, cur, min_t(uint, PAGE_SIZE, + end - cur)); + } else { + memcpy(buf + pageofs_out, cur + pageofs_out, + min_t(uint, righthalf, end - cur)); + } + kunmap_atomic(buf); + } + cur += PAGE_SIZE; + } +} + +static int z_erofs_decompress_generic(struct z_erofs_decompress_req *rq, + struct list_head *pagepool) +{ + const unsigned int nrpages_out = + PAGE_ALIGN(rq->pageofs_out + rq->outputsize) >> PAGE_SHIFT; + const struct z_erofs_decompressor *alg = decompressors + rq->alg; + unsigned int dst_maptype; + void *dst; + int ret, i; + + if (nrpages_out == 1 && !rq->inplace_io) { + DBG_BUGON(!*rq->out); + dst = kmap_atomic(*rq->out); + dst_maptype = 0; + goto dstmap_out; + } + + /* + * For the case of small output size (especially much less + * than PAGE_SIZE), memcpy the decompressed data rather than + * compressed data is preferred. + */ + if (rq->outputsize <= PAGE_SIZE * 7 / 8) { + dst = erofs_get_pcpubuf(0); + if (IS_ERR(dst)) + return PTR_ERR(dst); + + rq->inplace_io = false; + ret = alg->decompress(rq, dst); + if (!ret) + copy_from_pcpubuf(rq->out, dst, rq->pageofs_out, + rq->outputsize); + + erofs_put_pcpubuf(dst); + return ret; + } + + ret = alg->prepare_destpages(rq, pagepool); + if (ret < 0) { + return ret; + } else if (ret) { + dst = page_address(*rq->out); + dst_maptype = 1; + goto dstmap_out; + } + + i = 0; + while (1) { + dst = vm_map_ram(rq->out, nrpages_out, -1, PAGE_KERNEL); + + /* retry two more times (totally 3 times) */ + if (dst || ++i >= 3) + break; + vm_unmap_aliases(); + } + + if (!dst) + return -ENOMEM; + + dst_maptype = 2; + +dstmap_out: + ret = alg->decompress(rq, dst + rq->pageofs_out); + + if (!dst_maptype) + kunmap_atomic(dst); + else if (dst_maptype == 2) + vm_unmap_ram(dst, nrpages_out); + return ret; +} + +static int z_erofs_shifted_transform(const struct z_erofs_decompress_req *rq, + struct list_head *pagepool) +{ + const unsigned int nrpages_out = + PAGE_ALIGN(rq->pageofs_out + rq->outputsize) >> PAGE_SHIFT; + const unsigned int righthalf = PAGE_SIZE - rq->pageofs_out; + unsigned char *src, *dst; + + if (nrpages_out > 2) { + DBG_BUGON(1); + return -EIO; + } + + if (rq->out[0] == *rq->in) { + DBG_BUGON(nrpages_out != 1); + return 0; + } + + src = kmap_atomic(*rq->in); + if (rq->out[0]) { + dst = kmap_atomic(rq->out[0]); + memcpy(dst + rq->pageofs_out, src, righthalf); + kunmap_atomic(dst); + } + + if (nrpages_out == 2) { + DBG_BUGON(!rq->out[1]); + if (rq->out[1] == *rq->in) { + memmove(src, src + righthalf, rq->pageofs_out); + } else { + dst = kmap_atomic(rq->out[1]); + memcpy(dst, src + righthalf, rq->pageofs_out); + kunmap_atomic(dst); + } + } + kunmap_atomic(src); + return 0; +} + +int z_erofs_decompress(struct z_erofs_decompress_req *rq, + struct list_head *pagepool) +{ + if (rq->alg == Z_EROFS_COMPRESSION_SHIFTED) + return z_erofs_shifted_transform(rq, pagepool); + return z_erofs_decompress_generic(rq, pagepool); +} diff --git a/drivers/staging/erofs/dir.c b/drivers/staging/erofs/dir.c index fe6683effd05..722b653c7a77 100644 --- a/drivers/staging/erofs/dir.c +++ b/drivers/staging/erofs/dir.c @@ -1,14 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * linux/drivers/staging/erofs/dir.c - * * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ #include "internal.h" @@ -33,19 +26,18 @@ static void debug_one_dentry(unsigned char d_type, const char *de_name, memcpy(dbg_namebuf, de_name, de_namelen); dbg_namebuf[de_namelen] = '\0'; - debugln("found dirent %s de_len %u d_type %d", dbg_namebuf, - de_namelen, d_type); + erofs_dbg("found dirent %s de_len %u d_type %d", dbg_namebuf, + de_namelen, d_type); #endif } -static int erofs_fill_dentries(struct dir_context *ctx, - void *dentry_blk, unsigned *ofs, - unsigned nameoff, unsigned maxsize) +static int erofs_fill_dentries(struct inode *dir, struct dir_context *ctx, + void *dentry_blk, unsigned int *ofs, + unsigned int nameoff, unsigned int maxsize) { - struct erofs_dirent *de = dentry_blk; + struct erofs_dirent *de = dentry_blk + *ofs; const struct erofs_dirent *end = dentry_blk + nameoff; - de = dentry_blk + *ofs; while (de < end) { const char *de_name; unsigned int de_namelen; @@ -66,16 +58,18 @@ static int erofs_fill_dentries(struct dir_context *ctx, de_namelen = le16_to_cpu(de[1].nameoff) - nameoff; /* a corrupted entry is found */ - if (unlikely(nameoff + de_namelen > maxsize || - de_namelen > EROFS_NAME_LEN)) { + if (nameoff + de_namelen > maxsize || + de_namelen > EROFS_NAME_LEN) { + erofs_err(dir->i_sb, "bogus dirent @ nid %llu", + EROFS_I(dir)->nid); DBG_BUGON(1); - return -EIO; + return -EFSCORRUPTED; } debug_one_dentry(d_type, de_name, de_namelen); if (!dir_emit(ctx, de_name, de_namelen, - le64_to_cpu(de->nid), d_type)) - /* stoped by some reason */ + le64_to_cpu(de->nid), d_type)) + /* stopped by some reason */ return 1; ++de; *ofs += sizeof(struct erofs_dirent); @@ -89,62 +83,63 @@ static int erofs_readdir(struct file *f, struct dir_context *ctx) struct inode *dir = file_inode(f); struct address_space *mapping = dir->i_mapping; const size_t dirsize = i_size_read(dir); - unsigned i = ctx->pos / EROFS_BLKSIZ; - unsigned ofs = ctx->pos % EROFS_BLKSIZ; + unsigned int i = ctx->pos / EROFS_BLKSIZ; + unsigned int ofs = ctx->pos % EROFS_BLKSIZ; int err = 0; bool initial = true; while (ctx->pos < dirsize) { struct page *dentry_page; struct erofs_dirent *de; - unsigned nameoff, maxsize; + unsigned int nameoff, maxsize; dentry_page = read_mapping_page(mapping, i, NULL); if (dentry_page == ERR_PTR(-ENOMEM)) { err = -ENOMEM; break; } else if (IS_ERR(dentry_page)) { - errln("fail to readdir of logical block %u of nid %llu", - i, EROFS_V(dir)->nid); - err = PTR_ERR(dentry_page); + erofs_err(dir->i_sb, + "fail to readdir of logical block %u of nid %llu", + i, EROFS_I(dir)->nid); + err = -EFSCORRUPTED; break; } - lock_page(dentry_page); de = (struct erofs_dirent *)kmap(dentry_page); nameoff = le16_to_cpu(de->nameoff); - if (unlikely(nameoff < sizeof(struct erofs_dirent) || - nameoff >= PAGE_SIZE)) { - errln("%s, invalid de[0].nameoff %u", - __func__, nameoff); - - err = -EIO; + if (nameoff < sizeof(struct erofs_dirent) || + nameoff >= PAGE_SIZE) { + erofs_err(dir->i_sb, + "invalid de[0].nameoff %u @ nid %llu", + nameoff, EROFS_I(dir)->nid); + err = -EFSCORRUPTED; goto skip_this; } - maxsize = min_t(unsigned, dirsize - ctx->pos + ofs, PAGE_SIZE); + maxsize = min_t(unsigned int, + dirsize - ctx->pos + ofs, PAGE_SIZE); /* search dirents at the arbitrary position */ - if (unlikely(initial)) { + if (initial) { initial = false; ofs = roundup(ofs, sizeof(struct erofs_dirent)); - if (unlikely(ofs >= nameoff)) + if (ofs >= nameoff) goto skip_this; } - err = erofs_fill_dentries(ctx, de, &ofs, nameoff, maxsize); + err = erofs_fill_dentries(dir, ctx, de, &ofs, + nameoff, maxsize); skip_this: kunmap(dentry_page); - unlock_page(dentry_page); put_page(dentry_page); ctx->pos = blknr_to_addr(i) + ofs; - if (unlikely(err)) + if (err) break; ++i; ofs = 0; @@ -155,6 +150,5 @@ static int erofs_readdir(struct file *f, struct dir_context *ctx) const struct file_operations erofs_dir_fops = { .llseek = generic_file_llseek, .read = generic_read_dir, - .iterate = erofs_readdir, + .iterate_shared = erofs_readdir, }; - diff --git a/drivers/staging/erofs/erofs_fs.h b/drivers/staging/erofs/erofs_fs.h index d8838ce66941..011c3e281f7f 100644 --- a/drivers/staging/erofs/erofs_fs.h +++ b/drivers/staging/erofs/erofs_fs.h @@ -1,115 +1,93 @@ -/* SPDX-License-Identifier: GPL-2.0 OR Apache-2.0 - * - * linux/drivers/staging/erofs/erofs_fs.h +/* SPDX-License-Identifier: GPL-2.0-only OR Apache-2.0 */ +/* + * EROFS (Enhanced ROM File System) on-disk format definition * * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is dual-licensed; you may select either the GNU General Public - * License version 2 or Apache License, Version 2.0. See the file COPYING - * in the main directory of the Linux distribution for more details. + * https://www.huawei.com/ */ #ifndef __EROFS_FS_H #define __EROFS_FS_H -/* Enhanced(Extended) ROM File System */ -#define EROFS_SUPER_MAGIC_V1 0xE0F5E1E2 +#define EROFS_SUPER_MAGIC_V1 0xE0F5E1E2 #define EROFS_SUPER_OFFSET 1024 +#define EROFS_FEATURE_COMPAT_SB_CHKSUM 0x00000001 + /* - * Any bits that aren't in EROFS_ALL_REQUIREMENTS should be - * incompatible with this kernel version. + * Any bits that aren't in EROFS_ALL_FEATURE_INCOMPAT should + * be incompatible with this kernel version. */ -#define EROFS_ALL_REQUIREMENTS 0 +#define EROFS_FEATURE_INCOMPAT_LZ4_0PADDING 0x00000001 +#define EROFS_ALL_FEATURE_INCOMPAT EROFS_FEATURE_INCOMPAT_LZ4_0PADDING +/* 128-byte erofs on-disk super block */ struct erofs_super_block { -/* 0 */__le32 magic; /* in the little endian */ -/* 4 */__le32 checksum; /* crc32c(super_block) */ -/* 8 */__le32 features; /* (aka. feature_compat) */ -/* 12 */__u8 blkszbits; /* support block_size == PAGE_SIZE only */ -/* 13 */__u8 reserved; + __le32 magic; /* file system magic number */ + __le32 checksum; /* crc32c(super_block) */ + __le32 feature_compat; + __u8 blkszbits; /* support block_size == PAGE_SIZE only */ + __u8 reserved; -/* 14 */__le16 root_nid; -/* 16 */__le64 inos; /* total valid ino # (== f_files - f_favail) */ + __le16 root_nid; /* nid of root directory */ + __le64 inos; /* total valid ino # (== f_files - f_favail) */ -/* 24 */__le64 build_time; /* inode v1 time derivation */ -/* 32 */__le32 build_time_nsec; -/* 36 */__le32 blocks; /* used for statfs */ -/* 40 */__le32 meta_blkaddr; -/* 44 */__le32 xattr_blkaddr; -/* 48 */__u8 uuid[16]; /* 128-bit uuid for volume */ -/* 64 */__u8 volume_name[16]; /* volume name */ -/* 80 */__le32 requirements; /* (aka. feature_incompat) */ - -/* 84 */__u8 reserved2[44]; -} __packed; /* 128 bytes */ - -#define __EROFS_BIT(_prefix, _cur, _pre) enum { \ - _prefix ## _cur ## _BIT = _prefix ## _pre ## _BIT + \ - _prefix ## _pre ## _BITS } + __le64 build_time; /* inode v1 time derivation */ + __le32 build_time_nsec; /* inode v1 time derivation in nano scale */ + __le32 blocks; /* used for statfs */ + __le32 meta_blkaddr; /* start block address of metadata area */ + __le32 xattr_blkaddr; /* start block address of shared xattr area */ + __u8 uuid[16]; /* 128-bit uuid for volume */ + __u8 volume_name[16]; /* volume name */ + __le32 feature_incompat; + __u8 reserved2[44]; +}; /* - * erofs inode data mapping: + * erofs inode datalayout (i_format in on-disk inode): * 0 - inode plain without inline data A: * inode, [xattrs], ... | ... | no-holed data - * 1 - inode VLE compression B: + * 1 - inode VLE compression B (legacy): * inode, [xattrs], extents ... | ... * 2 - inode plain with inline data C: * inode, [xattrs], last_inline_data, ... | ... | no-holed data - * 3~7 - reserved + * 3 - inode compression D: + * inode, [xattrs], map_header, extents ... | ... + * 4~7 - reserved */ enum { - EROFS_INODE_LAYOUT_PLAIN, - EROFS_INODE_LAYOUT_COMPRESSION, - EROFS_INODE_LAYOUT_INLINE, - EROFS_INODE_LAYOUT_MAX + EROFS_INODE_FLAT_PLAIN = 0, + EROFS_INODE_FLAT_COMPRESSION_LEGACY = 1, + EROFS_INODE_FLAT_INLINE = 2, + EROFS_INODE_FLAT_COMPRESSION = 3, + EROFS_INODE_DATALAYOUT_MAX }; + +static inline bool erofs_inode_is_data_compressed(unsigned int datamode) +{ + return datamode == EROFS_INODE_FLAT_COMPRESSION || + datamode == EROFS_INODE_FLAT_COMPRESSION_LEGACY; +} + +/* bit definitions of inode i_advise */ #define EROFS_I_VERSION_BITS 1 -#define EROFS_I_DATA_MAPPING_BITS 3 +#define EROFS_I_DATALAYOUT_BITS 3 #define EROFS_I_VERSION_BIT 0 -__EROFS_BIT(EROFS_I_, DATA_MAPPING, VERSION); +#define EROFS_I_DATALAYOUT_BIT 1 #define EROFS_I_ALL \ - ((1 << (EROFS_I_DATA_MAPPING_BIT + EROFS_I_DATA_MAPPING_BITS)) - 1) + ((1 << (EROFS_I_DATALAYOUT_BIT + EROFS_I_DATALAYOUT_BITS)) - 1) -struct erofs_inode_v1 { -/* 0 */__le16 i_advise; +/* 32-byte reduced form of an ondisk inode */ +struct erofs_inode_compact { + __le16 i_format; /* inode format hints */ /* 1 header + n-1 * 4 bytes inline xattr to keep continuity */ -/* 2 */__le16 i_xattr_icount; -/* 4 */__le16 i_mode; -/* 6 */__le16 i_nlink; -/* 8 */__le32 i_size; -/* 12 */__le32 i_reserved; -/* 16 */union { - /* file total compressed blocks for data mapping 1 */ - __le32 compressed_blocks; - __le32 raw_blkaddr; - - /* for device files, used to indicate old/new device # */ - __le32 rdev; - } i_u __packed; -/* 20 */__le32 i_ino; /* only used for 32-bit stat compatibility */ -/* 24 */__le16 i_uid; -/* 26 */__le16 i_gid; -/* 28 */__le32 i_checksum; -} __packed; - -/* 32 bytes on-disk inode */ -#define EROFS_INODE_LAYOUT_V1 0 -/* 64 bytes on-disk inode */ -#define EROFS_INODE_LAYOUT_V2 1 - -struct erofs_inode_v2 { - __le16 i_advise; - - /* 1 header + n-1 * 4 bytes inline xattr to keep continuity */ __le16 i_xattr_icount; __le16 i_mode; - __le16 i_reserved; /* 8 bytes */ - __le64 i_size; /* 16 bytes */ + __le16 i_nlink; + __le32 i_size; + __le32 i_reserved; union { /* file total compressed blocks for data mapping 1 */ __le32 compressed_blocks; @@ -117,19 +95,46 @@ struct erofs_inode_v2 { /* for device files, used to indicate old/new device # */ __le32 rdev; - } i_u __packed; + } i_u; + __le32 i_ino; /* only used for 32-bit stat compatibility */ + __le16 i_uid; + __le16 i_gid; + __le32 i_reserved2; +}; + +/* 32 bytes on-disk inode */ +#define EROFS_INODE_LAYOUT_COMPACT 0 +/* 64 bytes on-disk inode */ +#define EROFS_INODE_LAYOUT_EXTENDED 1 + +/* 64-byte complete form of an ondisk inode */ +struct erofs_inode_extended { + __le16 i_format; /* inode format hints */ + +/* 1 header + n-1 * 4 bytes inline xattr to keep continuity */ + __le16 i_xattr_icount; + __le16 i_mode; + __le16 i_reserved; + __le64 i_size; + union { + /* file total compressed blocks for data mapping 1 */ + __le32 compressed_blocks; + __le32 raw_blkaddr; + + /* for device files, used to indicate old/new device # */ + __le32 rdev; + } i_u; /* only used for 32-bit stat compatibility */ - __le32 i_ino; /* 24 bytes */ + __le32 i_ino; __le32 i_uid; __le32 i_gid; - __le64 i_ctime; /* 32 bytes */ + __le64 i_ctime; __le32 i_ctime_nsec; __le32 i_nlink; - __u8 i_reserved2[12]; - __le32 i_checksum; /* 64 bytes */ -} __packed; + __u8 i_reserved2[16]; +}; #define EROFS_MAX_SHARED_XATTRS (128) /* h_shared_count between 129 ... 255 are special # */ @@ -147,11 +152,11 @@ struct erofs_inode_v2 { * for read-only fs, no need to introduce h_refcount */ struct erofs_xattr_ibody_header { - __le32 h_checksum; + __le32 h_reserved; __u8 h_shared_count; - __u8 h_reserved[7]; + __u8 h_reserved2[7]; __le32 h_shared_xattrs[0]; /* shared xattr id array */ -} __packed; +}; /* Name indexes */ #define EROFS_XATTR_INDEX_USER 1 @@ -168,27 +173,61 @@ struct erofs_xattr_entry { __le16 e_value_size; /* size of attribute value */ /* followed by e_name and e_value */ char e_name[0]; /* attribute name */ -} __packed; +}; -#define ondisk_xattr_ibody_size(count) ({\ - u32 __count = le16_to_cpu(count); \ - ((__count) == 0) ? 0 : \ - sizeof(struct erofs_xattr_ibody_header) + \ - sizeof(__u32) * ((__count) - 1); }) +static inline unsigned int erofs_xattr_ibody_size(__le16 i_xattr_icount) +{ + if (!i_xattr_icount) + return 0; + + return sizeof(struct erofs_xattr_ibody_header) + + sizeof(__u32) * (le16_to_cpu(i_xattr_icount) - 1); +} #define EROFS_XATTR_ALIGN(size) round_up(size, sizeof(struct erofs_xattr_entry)) -#define EROFS_XATTR_ENTRY_SIZE(entry) EROFS_XATTR_ALIGN( \ - sizeof(struct erofs_xattr_entry) + \ - (entry)->e_name_len + le16_to_cpu((entry)->e_value_size)) -/* have to be aligned with 8 bytes on disk */ -struct erofs_extent_header { - __le32 eh_checksum; - __le32 eh_reserved[3]; -} __packed; +static inline unsigned int erofs_xattr_entry_size(struct erofs_xattr_entry *e) +{ + return EROFS_XATTR_ALIGN(sizeof(struct erofs_xattr_entry) + + e->e_name_len + le16_to_cpu(e->e_value_size)); +} + +/* available compression algorithm types (for h_algorithmtype) */ +enum { + Z_EROFS_COMPRESSION_LZ4 = 0, + Z_EROFS_COMPRESSION_MAX +}; /* - * Z_EROFS Variable-sized Logical Extent cluster type: + * bit 0 : COMPACTED_2B indexes (0 - off; 1 - on) + * e.g. for 4k logical cluster size, 4B if compacted 2B is off; + * (4B) + 2B + (4B) if compacted 2B is on. + */ +#define Z_EROFS_ADVISE_COMPACTED_2B_BIT 0 + +#define Z_EROFS_ADVISE_COMPACTED_2B (1 << Z_EROFS_ADVISE_COMPACTED_2B_BIT) + +struct z_erofs_map_header { + __le32 h_reserved1; + __le16 h_advise; + /* + * bit 0-3 : algorithm type of head 1 (logical cluster type 01); + * bit 4-7 : algorithm type of head 2 (logical cluster type 11). + */ + __u8 h_algorithmtype; + /* + * bit 0-2 : logical cluster bits - 12, e.g. 0 for 4096; + * bit 3-4 : (physical - logical) cluster bits of head 1: + * For example, if logical clustersize = 4096, 1 for 8192. + * bit 5-7 : (physical - logical) cluster bits of head 2. + */ + __u8 h_clusterbits; +}; + +#define Z_EROFS_VLE_LEGACY_HEADER_PADDING 8 + +/* + * Fixed-sized output compression ondisk Logical Extent cluster type: * 0 - literal (uncompressed) cluster * 1 - compressed cluster (for the head logical cluster) * 2 - compressed cluster (for the other logical clusters) @@ -212,6 +251,14 @@ struct erofs_extent_header { * di_u.delta[1] = distance to its corresponding tail cluster * (di_advise could be 0, 1 or 2) */ +enum { + Z_EROFS_VLE_CLUSTER_TYPE_PLAIN = 0, + Z_EROFS_VLE_CLUSTER_TYPE_HEAD = 1, + Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD = 2, + Z_EROFS_VLE_CLUSTER_TYPE_RESERVED = 3, + Z_EROFS_VLE_CLUSTER_TYPE_MAX +}; + #define Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS 2 #define Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT 0 @@ -230,18 +277,19 @@ struct z_erofs_vle_decompressed_index { * [1] - pointing to the tail cluster */ __le16 delta[2]; - } di_u __packed; /* 8 bytes */ -} __packed; + } di_u; +}; -#define Z_EROFS_VLE_EXTENT_ALIGN(size) round_up(size, \ - sizeof(struct z_erofs_vle_decompressed_index)) +#define Z_EROFS_VLE_LEGACY_INDEX_ALIGN(size) \ + (round_up(size, sizeof(struct z_erofs_vle_decompressed_index)) + \ + sizeof(struct z_erofs_map_header) + Z_EROFS_VLE_LEGACY_HEADER_PADDING) /* dirent sorts in alphabet order, thus we can do binary search */ struct erofs_dirent { - __le64 nid; /* 0, node number */ - __le16 nameoff; /* 8, start offset of file name */ - __u8 file_type; /* 10, file type */ - __u8 reserved; /* 11, reserved */ + __le64 nid; /* node number */ + __le16 nameoff; /* start offset of file name */ + __u8 file_type; /* file type */ + __u8 reserved; /* reserved */ } __packed; /* file types used in inode_info->flags */ @@ -263,14 +311,16 @@ enum { static inline void erofs_check_ondisk_layout_definitions(void) { BUILD_BUG_ON(sizeof(struct erofs_super_block) != 128); - BUILD_BUG_ON(sizeof(struct erofs_inode_v1) != 32); - BUILD_BUG_ON(sizeof(struct erofs_inode_v2) != 64); + BUILD_BUG_ON(sizeof(struct erofs_inode_compact) != 32); + BUILD_BUG_ON(sizeof(struct erofs_inode_extended) != 64); BUILD_BUG_ON(sizeof(struct erofs_xattr_ibody_header) != 12); BUILD_BUG_ON(sizeof(struct erofs_xattr_entry) != 4); - BUILD_BUG_ON(sizeof(struct erofs_extent_header) != 16); + BUILD_BUG_ON(sizeof(struct z_erofs_map_header) != 8); BUILD_BUG_ON(sizeof(struct z_erofs_vle_decompressed_index) != 8); BUILD_BUG_ON(sizeof(struct erofs_dirent) != 12); + + BUILD_BUG_ON(BIT(Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) < + Z_EROFS_VLE_CLUSTER_TYPE_MAX - 1); } #endif - diff --git a/drivers/staging/erofs/inode.c b/drivers/staging/erofs/inode.c index 02398c7eb4a4..5f9c6fb79ac0 100644 --- a/drivers/staging/erofs/inode.c +++ b/drivers/staging/erofs/inode.c @@ -1,14 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * linux/drivers/staging/erofs/inode.c - * * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ #include "xattr.h" @@ -19,56 +12,59 @@ * the inode payload page if it's an extended inode) in order to fill * inline data if possible. */ -static struct page *read_inode(struct inode *inode, unsigned int *ofs) +static struct page *erofs_read_inode(struct inode *inode, + unsigned int *ofs) { struct super_block *sb = inode->i_sb; struct erofs_sb_info *sbi = EROFS_SB(sb); - struct erofs_vnode *vi = EROFS_V(inode); + struct erofs_inode *vi = EROFS_I(inode); const erofs_off_t inode_loc = iloc(sbi, vi->nid); - erofs_blk_t blkaddr; + + erofs_blk_t blkaddr, nblks = 0; struct page *page; - struct erofs_inode_v1 *v1; - struct erofs_inode_v2 *v2, *copied = NULL; + struct erofs_inode_compact *dic; + struct erofs_inode_extended *die, *copied = NULL; unsigned int ifmt; int err; blkaddr = erofs_blknr(inode_loc); *ofs = erofs_blkoff(inode_loc); - debugln("%s, reading inode nid %llu at %u of blkaddr %u", - __func__, vi->nid, *ofs, blkaddr); + erofs_dbg("%s, reading inode nid %llu at %u of blkaddr %u", + __func__, vi->nid, *ofs, blkaddr); - page = erofs_get_meta_page(sb, blkaddr, false); + page = erofs_get_meta_page(sb, blkaddr); if (IS_ERR(page)) { - errln("failed to get inode (nid: %llu) page, err %ld", - vi->nid, PTR_ERR(page)); + erofs_err(sb, "failed to get inode (nid: %llu) page, err %ld", + vi->nid, PTR_ERR(page)); return page; } - v1 = page_address(page) + *ofs; - ifmt = le16_to_cpu(v1->i_advise); + dic = page_address(page) + *ofs; + ifmt = le16_to_cpu(dic->i_format); if (ifmt & ~EROFS_I_ALL) { - errln("unsupported i_format %u of nid %llu", ifmt, vi->nid); + erofs_err(inode->i_sb, "unsupported i_format %u of nid %llu", + ifmt, vi->nid); err = -EOPNOTSUPP; goto err_out; } - vi->data_mapping_mode = __inode_data_mapping(ifmt); - if (unlikely(vi->data_mapping_mode >= EROFS_INODE_LAYOUT_MAX)) { - errln("unknown data mapping mode %u of nid %llu", - vi->data_mapping_mode, vi->nid); + vi->datalayout = erofs_inode_datalayout(ifmt); + if (vi->datalayout >= EROFS_INODE_DATALAYOUT_MAX) { + erofs_err(inode->i_sb, "unsupported datalayout %u of nid %llu", + vi->datalayout, vi->nid); err = -EOPNOTSUPP; goto err_out; } - switch (__inode_version(ifmt)) { - case EROFS_INODE_LAYOUT_V2: - vi->inode_isize = sizeof(struct erofs_inode_v2); + switch (erofs_inode_version(ifmt)) { + case EROFS_INODE_LAYOUT_EXTENDED: + vi->inode_isize = sizeof(struct erofs_inode_extended); /* check if the inode acrosses page boundary */ if (*ofs + vi->inode_isize <= PAGE_SIZE) { *ofs += vi->inode_isize; - v2 = (struct erofs_inode_v2 *)v1; + die = (struct erofs_inode_extended *)dic; } else { const unsigned int gotten = PAGE_SIZE - *ofs; @@ -77,78 +73,98 @@ static struct page *read_inode(struct inode *inode, unsigned int *ofs) err = -ENOMEM; goto err_out; } - memcpy(copied, v1, gotten); + memcpy(copied, dic, gotten); unlock_page(page); put_page(page); - page = erofs_get_meta_page(sb, blkaddr + 1, false); + page = erofs_get_meta_page(sb, blkaddr + 1); if (IS_ERR(page)) { - errln("failed to get inode payload page (nid: %llu), err %ld", - vi->nid, PTR_ERR(page)); + erofs_err(sb, "failed to get inode payload page (nid: %llu), err %ld", + vi->nid, PTR_ERR(page)); kfree(copied); return page; } *ofs = vi->inode_isize - gotten; memcpy((u8 *)copied + gotten, page_address(page), *ofs); - v2 = copied; + die = copied; } - vi->xattr_isize = ondisk_xattr_ibody_size(v2->i_xattr_icount); + vi->xattr_isize = erofs_xattr_ibody_size(die->i_xattr_icount); - inode->i_mode = le16_to_cpu(v2->i_mode); - if (S_ISREG(inode->i_mode) || S_ISDIR(inode->i_mode) || - S_ISLNK(inode->i_mode)) { - vi->raw_blkaddr = le32_to_cpu(v2->i_u.raw_blkaddr); - } else if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode)) { + inode->i_mode = le16_to_cpu(die->i_mode); + switch (inode->i_mode & S_IFMT) { + case S_IFREG: + case S_IFDIR: + case S_IFLNK: + vi->raw_blkaddr = le32_to_cpu(die->i_u.raw_blkaddr); + break; + case S_IFCHR: + case S_IFBLK: inode->i_rdev = - new_decode_dev(le32_to_cpu(v2->i_u.rdev)); - } else if (S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) { + new_decode_dev(le32_to_cpu(die->i_u.rdev)); + break; + case S_IFIFO: + case S_IFSOCK: inode->i_rdev = 0; - } else { + break; + default: goto bogusimode; } - - i_uid_write(inode, le32_to_cpu(v2->i_uid)); - i_gid_write(inode, le32_to_cpu(v2->i_gid)); - set_nlink(inode, le32_to_cpu(v2->i_nlink)); + i_uid_write(inode, le32_to_cpu(die->i_uid)); + i_gid_write(inode, le32_to_cpu(die->i_gid)); + set_nlink(inode, le32_to_cpu(die->i_nlink)); /* extended inode has its own timestamp */ - inode->i_ctime.tv_sec = le64_to_cpu(v2->i_ctime); - inode->i_ctime.tv_nsec = le32_to_cpu(v2->i_ctime_nsec); + inode->i_ctime.tv_sec = le64_to_cpu(die->i_ctime); + inode->i_ctime.tv_nsec = le32_to_cpu(die->i_ctime_nsec); + + inode->i_size = le64_to_cpu(die->i_size); + + /* total blocks for compressed files */ + if (erofs_inode_is_data_compressed(vi->datalayout)) + nblks = le32_to_cpu(die->i_u.compressed_blocks); - inode->i_size = le64_to_cpu(v2->i_size); kfree(copied); break; - case EROFS_INODE_LAYOUT_V1: - vi->inode_isize = sizeof(struct erofs_inode_v1); + case EROFS_INODE_LAYOUT_COMPACT: + vi->inode_isize = sizeof(struct erofs_inode_compact); *ofs += vi->inode_isize; - vi->xattr_isize = ondisk_xattr_ibody_size(v1->i_xattr_icount); + vi->xattr_isize = erofs_xattr_ibody_size(dic->i_xattr_icount); - inode->i_mode = le16_to_cpu(v1->i_mode); - if (S_ISREG(inode->i_mode) || S_ISDIR(inode->i_mode) || - S_ISLNK(inode->i_mode)) { - vi->raw_blkaddr = le32_to_cpu(v1->i_u.raw_blkaddr); - } else if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode)) { + inode->i_mode = le16_to_cpu(dic->i_mode); + switch (inode->i_mode & S_IFMT) { + case S_IFREG: + case S_IFDIR: + case S_IFLNK: + vi->raw_blkaddr = le32_to_cpu(dic->i_u.raw_blkaddr); + break; + case S_IFCHR: + case S_IFBLK: inode->i_rdev = - new_decode_dev(le32_to_cpu(v1->i_u.rdev)); - } else if (S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) { + new_decode_dev(le32_to_cpu(dic->i_u.rdev)); + break; + case S_IFIFO: + case S_IFSOCK: inode->i_rdev = 0; - } else { + break; + default: goto bogusimode; } - - i_uid_write(inode, le16_to_cpu(v1->i_uid)); - i_gid_write(inode, le16_to_cpu(v1->i_gid)); - set_nlink(inode, le16_to_cpu(v1->i_nlink)); + i_uid_write(inode, le16_to_cpu(dic->i_uid)); + i_gid_write(inode, le16_to_cpu(dic->i_gid)); + set_nlink(inode, le16_to_cpu(dic->i_nlink)); /* use build time for compact inodes */ inode->i_ctime.tv_sec = sbi->build_time; inode->i_ctime.tv_nsec = sbi->build_time_nsec; - inode->i_size = le32_to_cpu(v1->i_size); + inode->i_size = le32_to_cpu(dic->i_size); + if (erofs_inode_is_data_compressed(vi->datalayout)) + nblks = le32_to_cpu(dic->i_u.compressed_blocks); break; default: - errln("unsupported on-disk inode version %u of nid %llu", - __inode_version(ifmt), vi->nid); + erofs_err(inode->i_sb, + "unsupported on-disk inode version %u of nid %llu", + erofs_inode_version(ifmt), vi->nid); err = -EOPNOTSUPP; goto err_out; } @@ -158,12 +174,17 @@ static struct page *read_inode(struct inode *inode, unsigned int *ofs) inode->i_mtime.tv_nsec = inode->i_ctime.tv_nsec; inode->i_atime.tv_nsec = inode->i_ctime.tv_nsec; - /* measure inode.i_blocks as the generic filesystem */ - inode->i_blocks = ((inode->i_size - 1) >> 9) + 1; + if (!nblks) + /* measure inode.i_blocks as generic filesystems */ + inode->i_blocks = roundup(inode->i_size, EROFS_BLKSIZ) >> 9; + else + inode->i_blocks = nblks << LOG_SECTORS_PER_BLOCK; return page; + bogusimode: - errln("bogus i_mode (%o) @ nid %llu", inode->i_mode, vi->nid); - err = -EIO; + erofs_err(inode->i_sb, "bogus i_mode (%o) @ nid %llu", + inode->i_mode, vi->nid); + err = -EFSCORRUPTED; err_out: DBG_BUGON(1); kfree(copied); @@ -172,56 +193,45 @@ static struct page *read_inode(struct inode *inode, unsigned int *ofs) return ERR_PTR(err); } -/* - * try_lock can be required since locking order is: - * file data(fs_inode) - * meta(bd_inode) - * but the majority of the callers is "iget", - * in that case we are pretty sure no deadlock since - * no data operations exist. However I tend to - * try_lock since it takes no much overhead and - * will success immediately. - */ -static int fill_inline_data(struct inode *inode, void *data, unsigned m_pofs) +static int erofs_fill_symlink(struct inode *inode, void *data, + unsigned int m_pofs) { - struct erofs_vnode *vi = EROFS_V(inode); - struct erofs_sb_info *sbi = EROFS_I_SB(inode); - int mode = vi->data_mapping_mode; + struct erofs_inode *vi = EROFS_I(inode); + char *lnk; - DBG_BUGON(mode >= EROFS_INODE_LAYOUT_MAX); - - /* should be inode inline C */ - if (mode != EROFS_INODE_LAYOUT_INLINE) + /* if it cannot be handled with fast symlink scheme */ + if (vi->datalayout != EROFS_INODE_FLAT_INLINE || + inode->i_size >= PAGE_SIZE) { + inode->i_op = &erofs_symlink_iops; return 0; - - /* fast symlink (following ext4) */ - if (S_ISLNK(inode->i_mode) && inode->i_size < PAGE_SIZE) { - char *lnk = erofs_kmalloc(sbi, inode->i_size + 1, GFP_KERNEL); - - if (unlikely(lnk == NULL)) - return -ENOMEM; - - m_pofs += vi->xattr_isize; - - /* inline symlink data shouldn't across page boundary as well */ - if (unlikely(m_pofs + inode->i_size > PAGE_SIZE)) { - DBG_BUGON(1); - kfree(lnk); - return -EIO; - } - - /* get in-page inline data */ - memcpy(lnk, data + m_pofs, inode->i_size); - lnk[inode->i_size] = '\0'; - - inode->i_link = lnk; - set_inode_fast_symlink(inode); } - return -EAGAIN; + + lnk = kmalloc(inode->i_size + 1, GFP_KERNEL); + if (!lnk) + return -ENOMEM; + + m_pofs += vi->xattr_isize; + /* inline symlink data shouldn't cross page boundary as well */ + if (m_pofs + inode->i_size > PAGE_SIZE) { + kfree(lnk); + erofs_err(inode->i_sb, + "inline data cross block boundary @ nid %llu", + vi->nid); + DBG_BUGON(1); + return -EFSCORRUPTED; + } + + memcpy(lnk, data + m_pofs, inode->i_size); + lnk[inode->i_size] = '\0'; + + inode->i_link = lnk; + inode->i_op = &erofs_fast_symlink_iops; + return 0; } -static int fill_inode(struct inode *inode, int isdir) +static int erofs_fill_inode(struct inode *inode, int isdir) { + struct erofs_inode *vi = EROFS_I(inode); struct page *page; unsigned int ofs; int err = 0; @@ -229,81 +239,95 @@ static int fill_inode(struct inode *inode, int isdir) trace_erofs_fill_inode(inode, isdir); /* read inode base data from disk */ - page = read_inode(inode, &ofs); - if (IS_ERR(page)) { + page = erofs_read_inode(inode, &ofs); + if (IS_ERR(page)) return PTR_ERR(page); - } else { - /* setup the new inode */ - if (S_ISREG(inode->i_mode)) { -#ifdef CONFIG_EROFS_FS_XATTR - inode->i_op = &erofs_generic_xattr_iops; -#endif - inode->i_fop = &generic_ro_fops; - } else if (S_ISDIR(inode->i_mode)) { - inode->i_op = -#ifdef CONFIG_EROFS_FS_XATTR - &erofs_dir_xattr_iops; -#else - &erofs_dir_iops; -#endif - inode->i_fop = &erofs_dir_fops; - } else if (S_ISLNK(inode->i_mode)) { - /* by default, page_get_link is used for symlink */ - inode->i_op = -#ifdef CONFIG_EROFS_FS_XATTR - &erofs_symlink_xattr_iops, -#else - &page_symlink_inode_operations; -#endif - inode_nohighmem(inode); - } else if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode) || - S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) { -#ifdef CONFIG_EROFS_FS_XATTR - inode->i_op = &erofs_special_inode_operations; -#endif - init_special_inode(inode, inode->i_mode, inode->i_rdev); - } else { - err = -EIO; + + /* setup the new inode */ + switch (inode->i_mode & S_IFMT) { + case S_IFREG: + inode->i_op = &erofs_generic_iops; + inode->i_fop = &generic_ro_fops; + break; + case S_IFDIR: + inode->i_op = &erofs_dir_iops; + inode->i_fop = &erofs_dir_fops; + break; + case S_IFLNK: + err = erofs_fill_symlink(inode, page_address(page), ofs); + if (err) goto out_unlock; - } - - if (is_inode_layout_compression(inode)) { -#ifdef CONFIG_EROFS_FS_ZIP - inode->i_mapping->a_ops = - &z_erofs_vle_normalaccess_aops; -#else - err = -ENOTSUPP; -#endif - goto out_unlock; - } - - inode->i_mapping->a_ops = &erofs_raw_access_aops; - - /* fill last page if inline data is available */ - fill_inline_data(inode, page_address(page), ofs); + inode_nohighmem(inode); + break; + case S_IFCHR: + case S_IFBLK: + case S_IFIFO: + case S_IFSOCK: + inode->i_op = &erofs_generic_iops; + init_special_inode(inode, inode->i_mode, inode->i_rdev); + goto out_unlock; + default: + err = -EFSCORRUPTED; + goto out_unlock; } + if (erofs_inode_is_data_compressed(vi->datalayout)) { + err = z_erofs_fill_inode(inode); + goto out_unlock; + } + inode->i_mapping->a_ops = &erofs_raw_access_aops; + out_unlock: unlock_page(page); put_page(page); return err; } -struct inode *erofs_iget(struct super_block *sb, - erofs_nid_t nid, bool isdir) +/* + * erofs nid is 64bits, but i_ino is 'unsigned long', therefore + * we should do more for 32-bit platform to find the right inode. + */ +static int erofs_ilookup_test_actor(struct inode *inode, void *opaque) { - struct inode *inode = iget_locked(sb, nid); + const erofs_nid_t nid = *(erofs_nid_t *)opaque; - if (unlikely(inode == NULL)) + return EROFS_I(inode)->nid == nid; +} + +static int erofs_iget_set_actor(struct inode *inode, void *opaque) +{ + const erofs_nid_t nid = *(erofs_nid_t *)opaque; + + inode->i_ino = erofs_inode_hash(nid); + return 0; +} + +static inline struct inode *erofs_iget_locked(struct super_block *sb, + erofs_nid_t nid) +{ + const unsigned long hashval = erofs_inode_hash(nid); + + return iget5_locked(sb, hashval, erofs_ilookup_test_actor, + erofs_iget_set_actor, &nid); +} + +struct inode *erofs_iget(struct super_block *sb, + erofs_nid_t nid, + bool isdir) +{ + struct inode *inode = erofs_iget_locked(sb, nid); + + if (!inode) return ERR_PTR(-ENOMEM); if (inode->i_state & I_NEW) { int err; - struct erofs_vnode *vi = EROFS_V(inode); + struct erofs_inode *vi = EROFS_I(inode); + vi->nid = nid; - err = fill_inode(inode, isdir); - if (likely(!err)) + err = erofs_fill_inode(inode, isdir); + if (!err) unlock_new_inode(inode); else { iget_failed(inode); @@ -313,29 +337,38 @@ struct inode *erofs_iget(struct super_block *sb, return inode; } -#ifdef CONFIG_EROFS_FS_XATTR -const struct inode_operations erofs_generic_xattr_iops = { - .listxattr = erofs_listxattr, -}; -#endif +int erofs_getattr(const struct path *path, struct kstat *stat, + u32 request_mask, unsigned int query_flags) +{ + struct inode *const inode = d_inode(path->dentry); -#ifdef CONFIG_EROFS_FS_XATTR -const struct inode_operations erofs_symlink_xattr_iops = { + if (erofs_inode_is_data_compressed(EROFS_I(inode)->datalayout)) + stat->attributes |= STATX_ATTR_COMPRESSED; + + stat->attributes |= STATX_ATTR_IMMUTABLE; + stat->attributes_mask |= (STATX_ATTR_COMPRESSED | + STATX_ATTR_IMMUTABLE); + + generic_fillattr(inode, stat); + return 0; +} + +const struct inode_operations erofs_generic_iops = { + .getattr = erofs_getattr, + .listxattr = erofs_listxattr, + .get_acl = erofs_get_acl, +}; + +const struct inode_operations erofs_symlink_iops = { .get_link = page_get_link, + .getattr = erofs_getattr, .listxattr = erofs_listxattr, -}; -#endif - -const struct inode_operations erofs_special_inode_operations = { -#ifdef CONFIG_EROFS_FS_XATTR - .listxattr = erofs_listxattr, -#endif + .get_acl = erofs_get_acl, }; -#ifdef CONFIG_EROFS_FS_XATTR -const struct inode_operations erofs_fast_symlink_xattr_iops = { +const struct inode_operations erofs_fast_symlink_iops = { .get_link = simple_get_link, + .getattr = erofs_getattr, .listxattr = erofs_listxattr, + .get_acl = erofs_get_acl, }; -#endif - diff --git a/drivers/staging/erofs/internal.h b/drivers/staging/erofs/internal.h index 8ce37091db20..5ee2368a18d5 100644 --- a/drivers/staging/erofs/internal.h +++ b/drivers/staging/erofs/internal.h @@ -1,17 +1,10 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * linux/drivers/staging/erofs/internal.h - * +/* SPDX-License-Identifier: GPL-2.0-only */ +/* * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ -#ifndef __INTERNAL_H -#define __INTERNAL_H +#ifndef __EROFS_INTERNAL_H +#define __EROFS_INTERNAL_H #include #include @@ -19,7 +12,7 @@ #include #include #include -#include +#include #include #include #include "erofs_fs.h" @@ -28,58 +21,50 @@ #undef pr_fmt #define pr_fmt(fmt) "erofs: " fmt -#define errln(x, ...) pr_err(x "\n", ##__VA_ARGS__) -#define infoln(x, ...) pr_info(x "\n", ##__VA_ARGS__) +__printf(3, 4) void _erofs_err(struct super_block *sb, + const char *function, const char *fmt, ...); +#define erofs_err(sb, fmt, ...) \ + _erofs_err(sb, __func__, fmt "\n", ##__VA_ARGS__) +__printf(3, 4) void _erofs_info(struct super_block *sb, + const char *function, const char *fmt, ...); +#define erofs_info(sb, fmt, ...) \ + _erofs_info(sb, __func__, fmt "\n", ##__VA_ARGS__) #ifdef CONFIG_EROFS_FS_DEBUG -#define debugln(x, ...) pr_debug(x "\n", ##__VA_ARGS__) - -#define dbg_might_sleep might_sleep +#define erofs_dbg(x, ...) pr_debug(x "\n", ##__VA_ARGS__) #define DBG_BUGON BUG_ON #else -#define debugln(x, ...) ((void)0) - -#define dbg_might_sleep() ((void)0) +#define erofs_dbg(x, ...) ((void)0) #define DBG_BUGON(x) ((void)(x)) -#endif - -#ifdef CONFIG_EROFS_FAULT_INJECTION -enum { - FAULT_KMALLOC, - FAULT_MAX, -}; - -extern char *erofs_fault_name[FAULT_MAX]; -#define IS_FAULT_SET(fi, type) ((fi)->inject_type & (1 << (type))) - -struct erofs_fault_info { - atomic_t inject_ops; - unsigned int inject_rate; - unsigned int inject_type; -}; -#endif - -#ifdef CONFIG_EROFS_FS_ZIP_CACHE_BIPOLAR -#define EROFS_FS_ZIP_CACHE_LVL (2) -#elif defined(EROFS_FS_ZIP_CACHE_UNIPOLAR) -#define EROFS_FS_ZIP_CACHE_LVL (1) -#else -#define EROFS_FS_ZIP_CACHE_LVL (0) -#endif - -#if (!defined(EROFS_FS_HAS_MANAGED_CACHE) && (EROFS_FS_ZIP_CACHE_LVL > 0)) -#define EROFS_FS_HAS_MANAGED_CACHE -#endif +#endif /* !CONFIG_EROFS_FS_DEBUG */ /* EROFS_SUPER_MAGIC_V1 to represent the whole file system */ #define EROFS_SUPER_MAGIC EROFS_SUPER_MAGIC_V1 typedef u64 erofs_nid_t; +typedef u64 erofs_off_t; +/* data type for filesystem-wide blocks number */ +typedef u32 erofs_blk_t; struct erofs_sb_info { +#ifdef CONFIG_EROFS_FS_ZIP /* list for all registered superblocks, mainly for shrinker */ struct list_head list; struct mutex umount_mutex; + /* the dedicated workstation for compression */ + struct radix_tree_root workstn_tree; + + /* threshold for decompression synchronously */ + unsigned int max_sync_decompress_pages; + + unsigned int shrinker_run_no; + + /* current strategy of how to use managed cache */ + unsigned char cache_strategy; + + /* pseudo inode to manage cached pages */ + struct inode *managed_cache; +#endif /* CONFIG_EROFS_FS_ZIP */ u32 blocks; u32 meta_blkaddr; #ifdef CONFIG_EROFS_FS_XATTR @@ -88,18 +73,6 @@ struct erofs_sb_info { /* inode slot unit size in bit shift */ unsigned char islotbits; -#ifdef CONFIG_EROFS_FS_ZIP - /* cluster size in bit shift */ - unsigned char clusterbits; - - /* the dedicated workstation for compression */ - struct radix_tree_root workstn_tree; - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - struct inode *managed_cache; -#endif - -#endif u32 build_time_nsec; u64 build_time; @@ -111,69 +84,31 @@ struct erofs_sb_info { u8 uuid[16]; /* 128-bit uuid for volume */ u8 volume_name[16]; /* volume name */ - u32 requirements; - - char *dev_name; + u32 feature_compat; + u32 feature_incompat; unsigned int mount_opt; - unsigned int shrinker_run_no; - -#ifdef CONFIG_EROFS_FAULT_INJECTION - struct erofs_fault_info fault_info; /* For fault injection */ -#endif }; -#ifdef CONFIG_EROFS_FAULT_INJECTION -#define erofs_show_injection_info(type) \ - infoln("inject %s in %s of %pS", erofs_fault_name[type], \ - __func__, __builtin_return_address(0)) - -static inline bool time_to_inject(struct erofs_sb_info *sbi, int type) -{ - struct erofs_fault_info *ffi = &sbi->fault_info; - - if (!ffi->inject_rate) - return false; - - if (!IS_FAULT_SET(ffi, type)) - return false; - - atomic_inc(&ffi->inject_ops); - if (atomic_read(&ffi->inject_ops) >= ffi->inject_rate) { - atomic_set(&ffi->inject_ops, 0); - return true; - } - return false; -} -#endif - -static inline void *erofs_kmalloc(struct erofs_sb_info *sbi, - size_t size, gfp_t flags) -{ -#ifdef CONFIG_EROFS_FAULT_INJECTION - if (time_to_inject(sbi, FAULT_KMALLOC)) { - erofs_show_injection_info(FAULT_KMALLOC); - return NULL; - } -#endif - return kmalloc(size, flags); -} - #define EROFS_SB(sb) ((struct erofs_sb_info *)(sb)->s_fs_info) #define EROFS_I_SB(inode) ((struct erofs_sb_info *)(inode)->i_sb->s_fs_info) /* Mount flags set via mount options or defaults */ #define EROFS_MOUNT_XATTR_USER 0x00000010 #define EROFS_MOUNT_POSIX_ACL 0x00000020 -#define EROFS_MOUNT_FAULT_INJECTION 0x00000040 #define clear_opt(sbi, option) ((sbi)->mount_opt &= ~EROFS_MOUNT_##option) #define set_opt(sbi, option) ((sbi)->mount_opt |= EROFS_MOUNT_##option) #define test_opt(sbi, option) ((sbi)->mount_opt & EROFS_MOUNT_##option) #ifdef CONFIG_EROFS_FS_ZIP -#define erofs_workstn_lock(sbi) xa_lock(&(sbi)->workstn_tree) -#define erofs_workstn_unlock(sbi) xa_unlock(&(sbi)->workstn_tree) +enum { + EROFS_ZIP_CACHE_DISABLED, + EROFS_ZIP_CACHE_READAHEAD, + EROFS_ZIP_CACHE_READAROUND +}; + +#define EROFS_LOCKED_MAGIC (INT_MIN | 0xE0F510CCL) /* basic unit of the workstation of a super_block */ struct erofs_workgroup { @@ -184,8 +119,6 @@ struct erofs_workgroup { atomic_t refcount; }; -#define EROFS_LOCKED_MAGIC (INT_MIN | 0xE0F510CCL) - #if defined(CONFIG_SMP) static inline bool erofs_workgroup_try_to_freeze(struct erofs_workgroup *grp, int val) @@ -242,54 +175,14 @@ static inline int erofs_wait_on_workgroup_freezed(struct erofs_workgroup *grp) DBG_BUGON(v == EROFS_LOCKED_MAGIC); return v; } -#endif +#endif /* !CONFIG_SMP */ -static inline bool erofs_workgroup_get(struct erofs_workgroup *grp, int *ocnt) -{ - int o; - -repeat: - o = erofs_wait_on_workgroup_freezed(grp); - - if (unlikely(o <= 0)) - return -1; - - if (unlikely(atomic_cmpxchg(&grp->refcount, o, o + 1) != o)) - goto repeat; - - *ocnt = o; - return 0; -} - -#define __erofs_workgroup_get(grp) atomic_inc(&(grp)->refcount) -#define __erofs_workgroup_put(grp) atomic_dec(&(grp)->refcount) - -extern int erofs_workgroup_put(struct erofs_workgroup *grp); - -extern struct erofs_workgroup *erofs_find_workgroup( - struct super_block *sb, pgoff_t index, bool *tag); - -extern int erofs_register_workgroup(struct super_block *sb, - struct erofs_workgroup *grp, bool tag); - -extern unsigned long erofs_shrink_workstation(struct erofs_sb_info *sbi, - unsigned long nr_shrink, bool cleanup); - -static inline void erofs_workstation_cleanup_all(struct super_block *sb) -{ - erofs_shrink_workstation(EROFS_SB(sb), ~0UL, true); -} - -#ifdef EROFS_FS_HAS_MANAGED_CACHE -#define EROFS_UNALLOCATED_CACHED_PAGE ((void *)0x5F0EF00D) - -extern int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, - struct erofs_workgroup *egrp); -extern int erofs_try_to_free_cached_page(struct address_space *mapping, - struct page *page); -#endif - -#endif +/* hard limit of pages per compressed cluster */ +#define Z_EROFS_CLUSTER_MAX_PAGES (CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT) +#define EROFS_PCPUBUF_NR_PAGES Z_EROFS_CLUSTER_MAX_PAGES +#else +#define EROFS_PCPUBUF_NR_PAGES 0 +#endif /* !CONFIG_EROFS_FS_ZIP */ /* we strictly follow PAGE_SIZE and no buffer head yet */ #define LOG_BLOCK_SIZE PAGE_SHIFT @@ -308,19 +201,6 @@ extern int erofs_try_to_free_cached_page(struct address_space *mapping, #define ROOT_NID(sb) ((sb)->root_nid) -#ifdef CONFIG_EROFS_FS_ZIP -/* hard limit of pages per compressed cluster */ -#define Z_EROFS_CLUSTER_MAX_PAGES (CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT) - -/* page count of a compressed cluster */ -#define erofs_clusterpages(sbi) ((1 << (sbi)->clusterbits) / PAGE_SIZE) -#endif - -typedef u64 erofs_off_t; - -/* data type for filesystem-wide blocks number */ -typedef u32 erofs_blk_t; - #define erofs_blknr(addr) ((addr) / EROFS_BLKSIZ) #define erofs_blkoff(addr) ((addr) % EROFS_BLKSIZ) #define blknr_to_addr(nr) ((erofs_off_t)(nr) * EROFS_BLKSIZ) @@ -331,75 +211,74 @@ static inline erofs_off_t iloc(struct erofs_sb_info *sbi, erofs_nid_t nid) } /* atomic flag definitions */ -#define EROFS_V_EA_INITED_BIT 0 +#define EROFS_I_EA_INITED_BIT 0 +#define EROFS_I_Z_INITED_BIT 1 /* bitlock definitions (arranged in reverse order) */ -#define EROFS_V_BL_XATTR_BIT (BITS_PER_LONG - 1) +#define EROFS_I_BL_XATTR_BIT (BITS_PER_LONG - 1) +#define EROFS_I_BL_Z_BIT (BITS_PER_LONG - 2) -struct erofs_vnode { +struct erofs_inode { erofs_nid_t nid; /* atomic flags (including bitlocks) */ unsigned long flags; - unsigned char data_mapping_mode; - /* inline size in bytes */ + unsigned char datalayout; unsigned char inode_isize; unsigned short xattr_isize; - unsigned xattr_shared_count; - unsigned *xattr_shared_xattrs; - - erofs_blk_t raw_blkaddr; + unsigned int xattr_shared_count; + unsigned int *xattr_shared_xattrs; + union { + erofs_blk_t raw_blkaddr; +#ifdef CONFIG_EROFS_FS_ZIP + struct { + unsigned short z_advise; + unsigned char z_algorithmtype[2]; + unsigned char z_logical_clusterbits; + unsigned char z_physical_clusterbits[2]; + }; +#endif /* CONFIG_EROFS_FS_ZIP */ + }; /* the corresponding vfs inode */ struct inode vfs_inode; }; -#define EROFS_V(ptr) \ - container_of(ptr, struct erofs_vnode, vfs_inode) +#define EROFS_I(ptr) \ + container_of(ptr, struct erofs_inode, vfs_inode) -#define __inode_advise(x, bit, bits) \ - (((x) >> (bit)) & ((1 << (bits)) - 1)) - -#define __inode_version(advise) \ - __inode_advise(advise, EROFS_I_VERSION_BIT, \ - EROFS_I_VERSION_BITS) - -#define __inode_data_mapping(advise) \ - __inode_advise(advise, EROFS_I_DATA_MAPPING_BIT,\ - EROFS_I_DATA_MAPPING_BITS) - -static inline unsigned long inode_datablocks(struct inode *inode) +static inline unsigned long erofs_inode_datablocks(struct inode *inode) { /* since i_size cannot be changed */ return DIV_ROUND_UP(inode->i_size, EROFS_BLKSIZ); } -static inline bool is_inode_layout_plain(struct inode *inode) +static inline unsigned int erofs_bitrange(unsigned int value, unsigned int bit, + unsigned int bits) { - return EROFS_V(inode)->data_mapping_mode == EROFS_INODE_LAYOUT_PLAIN; + + return (value >> bit) & ((1 << bits) - 1); } -static inline bool is_inode_layout_compression(struct inode *inode) + +static inline unsigned int erofs_inode_version(unsigned int value) { - return EROFS_V(inode)->data_mapping_mode == - EROFS_INODE_LAYOUT_COMPRESSION; + return erofs_bitrange(value, EROFS_I_VERSION_BIT, + EROFS_I_VERSION_BITS); } -static inline bool is_inode_layout_inline(struct inode *inode) +static inline unsigned int erofs_inode_datalayout(unsigned int value) { - return EROFS_V(inode)->data_mapping_mode == EROFS_INODE_LAYOUT_INLINE; + return erofs_bitrange(value, EROFS_I_DATALAYOUT_BIT, + EROFS_I_DATALAYOUT_BITS); } extern const struct super_operations erofs_sops; -extern const struct inode_operations erofs_dir_iops; -extern const struct file_operations erofs_dir_fops; extern const struct address_space_operations erofs_raw_access_aops; -#ifdef CONFIG_EROFS_FS_ZIP -extern const struct address_space_operations z_erofs_vle_normalaccess_aops; -#endif +extern const struct address_space_operations z_erofs_aops; /* * Logical to physical block mapping, used by erofs_map_blocks() @@ -428,6 +307,7 @@ extern const struct address_space_operations z_erofs_vle_normalaccess_aops; */ enum { BH_Zipped = BH_PrivateStart, + BH_FullMapped, }; /* Has a disk mapping */ @@ -436,150 +316,117 @@ enum { #define EROFS_MAP_META (1 << BH_Meta) /* The extent has been compressed */ #define EROFS_MAP_ZIPPED (1 << BH_Zipped) +/* The length of extent is full */ +#define EROFS_MAP_FULL_MAPPED (1 << BH_FullMapped) struct erofs_map_blocks { erofs_off_t m_pa, m_la; u64 m_plen, m_llen; unsigned int m_flags; + + struct page *mpage; }; /* Flags used by erofs_map_blocks() */ #define EROFS_GET_BLOCKS_RAW 0x0001 +/* zmap.c */ +#ifdef CONFIG_EROFS_FS_ZIP +int z_erofs_fill_inode(struct inode *inode); +int z_erofs_map_blocks_iter(struct inode *inode, + struct erofs_map_blocks *map, + int flags); +#else +static inline int z_erofs_fill_inode(struct inode *inode) { return -EOPNOTSUPP; } +static inline int z_erofs_map_blocks_iter(struct inode *inode, + struct erofs_map_blocks *map, + int flags) +{ + return -EOPNOTSUPP; +} +#endif /* !CONFIG_EROFS_FS_ZIP */ + /* data.c */ -static inline struct bio *prepare_bio( - struct super_block *sb, - erofs_blk_t blkaddr, unsigned nr_pages, - bio_end_io_t endio) -{ - gfp_t gfp = GFP_NOIO; - struct bio *bio = bio_alloc(gfp, nr_pages); +struct page *erofs_get_meta_page(struct super_block *sb, erofs_blk_t blkaddr); - if (unlikely(bio == NULL) && - (current->flags & PF_MEMALLOC)) { - do { - nr_pages /= 2; - if (unlikely(!nr_pages)) { - bio = bio_alloc(gfp | __GFP_NOFAIL, 1); - BUG_ON(bio == NULL); - break; - } - bio = bio_alloc(gfp, nr_pages); - } while (bio == NULL); - } - - bio->bi_end_io = endio; - bio_set_dev(bio, sb->s_bdev); - bio->bi_iter.bi_sector = blkaddr << LOG_SECTORS_PER_BLOCK; - return bio; -} - -static inline void __submit_bio(struct bio *bio, unsigned op, unsigned op_flags) -{ - bio_set_op_attrs(bio, op, op_flags); - submit_bio(bio); -} - -extern struct page *erofs_get_meta_page(struct super_block *sb, - erofs_blk_t blkaddr, bool prio); -extern int erofs_map_blocks(struct inode *, struct erofs_map_blocks *, int); -extern int erofs_map_blocks_iter(struct inode *, struct erofs_map_blocks *, - struct page **, int); - -struct erofs_map_blocks_iter { - struct erofs_map_blocks map; - struct page *mpage; -}; - - -static inline struct page * -erofs_get_inline_page(struct inode *inode, - erofs_blk_t blkaddr) -{ - return erofs_get_meta_page(inode->i_sb, - blkaddr, S_ISDIR(inode->i_mode)); -} +int erofs_map_blocks(struct inode *, struct erofs_map_blocks *, int); /* inode.c */ -extern struct inode *erofs_iget(struct super_block *sb, - erofs_nid_t nid, bool dir); +static inline unsigned long erofs_inode_hash(erofs_nid_t nid) +{ +#if BITS_PER_LONG == 32 + return (nid >> 32) ^ (nid & 0xffffffff); +#else + return nid; +#endif +} + +extern const struct inode_operations erofs_generic_iops; +extern const struct inode_operations erofs_symlink_iops; +extern const struct inode_operations erofs_fast_symlink_iops; + +struct inode *erofs_iget(struct super_block *sb, erofs_nid_t nid, bool dir); +int erofs_getattr(const struct path *path, struct kstat *stat, + u32 request_mask, unsigned int query_flags); + +/* namei.c */ +extern const struct inode_operations erofs_dir_iops; + +int erofs_namei(struct inode *dir, struct qstr *name, + erofs_nid_t *nid, unsigned int *d_type); /* dir.c */ -int erofs_namei(struct inode *dir, struct qstr *name, - erofs_nid_t *nid, unsigned *d_type); +extern const struct file_operations erofs_dir_fops; -/* xattr.c */ -#ifdef CONFIG_EROFS_FS_XATTR -extern const struct xattr_handler *erofs_xattr_handlers[]; -#endif +/* utils.c / zdata.c */ +struct page *erofs_allocpage(struct list_head *pool, gfp_t gfp); -/* symlink */ -#ifdef CONFIG_EROFS_FS_XATTR -extern const struct inode_operations erofs_symlink_xattr_iops; -extern const struct inode_operations erofs_fast_symlink_xattr_iops; -extern const struct inode_operations erofs_special_inode_operations; -#endif - -static inline void set_inode_fast_symlink(struct inode *inode) -{ -#ifdef CONFIG_EROFS_FS_XATTR - inode->i_op = &erofs_fast_symlink_xattr_iops; +#if (EROFS_PCPUBUF_NR_PAGES > 0) +void *erofs_get_pcpubuf(unsigned int pagenr); +#define erofs_put_pcpubuf(buf) do { \ + (void)&(buf); \ + preempt_enable(); \ +} while (0) #else - inode->i_op = &simple_symlink_inode_operations; -#endif +static inline void *erofs_get_pcpubuf(unsigned int pagenr) +{ + return ERR_PTR(-EOPNOTSUPP); } -static inline bool is_inode_fast_symlink(struct inode *inode) -{ -#ifdef CONFIG_EROFS_FS_XATTR - return inode->i_op == &erofs_fast_symlink_xattr_iops; -#else - return inode->i_op == &simple_symlink_inode_operations; +#define erofs_put_pcpubuf(buf) do {} while (0) #endif -} -static inline void *erofs_vmap(struct page **pages, unsigned int count) -{ -#ifdef CONFIG_EROFS_FS_USE_VM_MAP_RAM - int i = 0; - - while (1) { - void *addr = vm_map_ram(pages, count, -1, PAGE_KERNEL); - /* retry two more times (totally 3 times) */ - if (addr != NULL || ++i >= 3) - return addr; - vm_unmap_aliases(); - } - return NULL; +#ifdef CONFIG_EROFS_FS_ZIP +int erofs_workgroup_put(struct erofs_workgroup *grp); +struct erofs_workgroup *erofs_find_workgroup(struct super_block *sb, + pgoff_t index); +int erofs_register_workgroup(struct super_block *sb, + struct erofs_workgroup *grp); +void erofs_workgroup_free_rcu(struct erofs_workgroup *grp); +void erofs_shrinker_register(struct super_block *sb); +void erofs_shrinker_unregister(struct super_block *sb); +int __init erofs_init_shrinker(void); +void erofs_exit_shrinker(void); +int __init z_erofs_init_zip_subsystem(void); +void z_erofs_exit_zip_subsystem(void); +int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, + struct erofs_workgroup *egrp); +int erofs_try_to_free_cached_page(struct address_space *mapping, + struct page *page); #else - return vmap(pages, count, VM_MAP, PAGE_KERNEL); -#endif -} +static inline void erofs_shrinker_register(struct super_block *sb) {} +static inline void erofs_shrinker_unregister(struct super_block *sb) {} +static inline int erofs_init_shrinker(void) { return 0; } +static inline void erofs_exit_shrinker(void) {} +static inline int z_erofs_init_zip_subsystem(void) { return 0; } +static inline void z_erofs_exit_zip_subsystem(void) {} +#endif /* !CONFIG_EROFS_FS_ZIP */ -static inline void erofs_vunmap(const void *mem, unsigned int count) -{ -#ifdef CONFIG_EROFS_FS_USE_VM_MAP_RAM - vm_unmap_ram(mem, count); -#else - vunmap(mem); -#endif -} - -/* utils.c */ -extern struct page *erofs_allocpage(struct list_head *pool, gfp_t gfp); - -extern void erofs_register_super(struct super_block *sb); -extern void erofs_unregister_super(struct super_block *sb); - -extern unsigned long erofs_shrink_count(struct shrinker *shrink, - struct shrink_control *sc); -extern unsigned long erofs_shrink_scan(struct shrinker *shrink, - struct shrink_control *sc); +#define EFSCORRUPTED EUCLEAN /* Filesystem is corrupted */ #ifndef lru_to_page #define lru_to_page(head) (list_entry((head)->prev, struct page, lru)) #endif -#endif - +#endif /* __EROFS_INTERNAL_H */ diff --git a/drivers/staging/erofs/lz4defs.h b/drivers/staging/erofs/lz4defs.h deleted file mode 100644 index 00a0b58a0871..000000000000 --- a/drivers/staging/erofs/lz4defs.h +++ /dev/null @@ -1,227 +0,0 @@ -#ifndef __LZ4DEFS_H__ -#define __LZ4DEFS_H__ - -/* - * lz4defs.h -- common and architecture specific defines for the kernel usage - - * LZ4 - Fast LZ compression algorithm - * Copyright (C) 2011-2016, Yann Collet. - * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * You can contact the author at : - * - LZ4 homepage : http://www.lz4.org - * - LZ4 source repository : https://github.com/lz4/lz4 - * - * Changed for kernel usage by: - * Sven Schmidt <4sschmid@informatik.uni-hamburg.de> - */ - -#include -#include /* memset, memcpy */ - -#define FORCE_INLINE __always_inline - -/*-************************************ - * Basic Types - **************************************/ -#include - -typedef uint8_t BYTE; -typedef uint16_t U16; -typedef uint32_t U32; -typedef int32_t S32; -typedef uint64_t U64; -typedef uintptr_t uptrval; - -/*-************************************ - * Architecture specifics - **************************************/ -#if defined(CONFIG_64BIT) -#define LZ4_ARCH64 1 -#else -#define LZ4_ARCH64 0 -#endif - -#if defined(__LITTLE_ENDIAN) -#define LZ4_LITTLE_ENDIAN 1 -#else -#define LZ4_LITTLE_ENDIAN 0 -#endif - -/*-************************************ - * Constants - **************************************/ -#define MINMATCH 4 - -#define WILDCOPYLENGTH 8 -#define LASTLITERALS 5 -#define MFLIMIT (WILDCOPYLENGTH + MINMATCH) - -/* Increase this value ==> compression run slower on incompressible data */ -#define LZ4_SKIPTRIGGER 6 - -#define HASH_UNIT sizeof(size_t) - -#define KB (1 << 10) -#define MB (1 << 20) -#define GB (1U << 30) - -#define MAXD_LOG 16 -#define MAX_DISTANCE ((1 << MAXD_LOG) - 1) -#define STEPSIZE sizeof(size_t) - -#define ML_BITS 4 -#define ML_MASK ((1U << ML_BITS) - 1) -#define RUN_BITS (8 - ML_BITS) -#define RUN_MASK ((1U << RUN_BITS) - 1) - -/*-************************************ - * Reading and writing into memory - **************************************/ -static FORCE_INLINE U16 LZ4_read16(const void *ptr) -{ - return get_unaligned((const U16 *)ptr); -} - -static FORCE_INLINE U32 LZ4_read32(const void *ptr) -{ - return get_unaligned((const U32 *)ptr); -} - -static FORCE_INLINE size_t LZ4_read_ARCH(const void *ptr) -{ - return get_unaligned((const size_t *)ptr); -} - -static FORCE_INLINE void LZ4_write16(void *memPtr, U16 value) -{ - put_unaligned(value, (U16 *)memPtr); -} - -static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) -{ - put_unaligned(value, (U32 *)memPtr); -} - -static FORCE_INLINE U16 LZ4_readLE16(const void *memPtr) -{ - return get_unaligned_le16(memPtr); -} - -static FORCE_INLINE void LZ4_writeLE16(void *memPtr, U16 value) -{ - return put_unaligned_le16(value, memPtr); -} - -static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) -{ -#if LZ4_ARCH64 - U64 a = get_unaligned((const U64 *)src); - - put_unaligned(a, (U64 *)dst); -#else - U32 a = get_unaligned((const U32 *)src); - U32 b = get_unaligned((const U32 *)src + 1); - - put_unaligned(a, (U32 *)dst); - put_unaligned(b, (U32 *)dst + 1); -#endif -} - -/* - * customized variant of memcpy, - * which can overwrite up to 7 bytes beyond dstEnd - */ -static FORCE_INLINE void LZ4_wildCopy(void *dstPtr, - const void *srcPtr, void *dstEnd) -{ - BYTE *d = (BYTE *)dstPtr; - const BYTE *s = (const BYTE *)srcPtr; - BYTE *const e = (BYTE *)dstEnd; - - do { - LZ4_copy8(d, s); - d += 8; - s += 8; - } while (d < e); -} - -static FORCE_INLINE unsigned int LZ4_NbCommonBytes(register size_t val) -{ -#if LZ4_LITTLE_ENDIAN - return __ffs(val) >> 3; -#else - return (BITS_PER_LONG - 1 - __fls(val)) >> 3; -#endif -} - -static FORCE_INLINE unsigned int LZ4_count( - const BYTE *pIn, - const BYTE *pMatch, - const BYTE *pInLimit) -{ - const BYTE *const pStart = pIn; - - while (likely(pIn < pInLimit - (STEPSIZE - 1))) { - size_t const diff = LZ4_read_ARCH(pMatch) ^ LZ4_read_ARCH(pIn); - - if (!diff) { - pIn += STEPSIZE; - pMatch += STEPSIZE; - continue; - } - - pIn += LZ4_NbCommonBytes(diff); - - return (unsigned int)(pIn - pStart); - } - -#if LZ4_ARCH64 - if ((pIn < (pInLimit - 3)) - && (LZ4_read32(pMatch) == LZ4_read32(pIn))) { - pIn += 4; - pMatch += 4; - } -#endif - - if ((pIn < (pInLimit - 1)) - && (LZ4_read16(pMatch) == LZ4_read16(pIn))) { - pIn += 2; - pMatch += 2; - } - - if ((pIn < pInLimit) && (*pMatch == *pIn)) - pIn++; - - return (unsigned int)(pIn - pStart); -} - -typedef enum { noLimit = 0, limitedOutput = 1 } limitedOutput_directive; -typedef enum { byPtr, byU32, byU16 } tableType_t; - -typedef enum { noDict = 0, withPrefix64k, usingExtDict } dict_directive; -typedef enum { noDictIssue = 0, dictSmall } dictIssue_directive; - -typedef enum { endOnOutputSize = 0, endOnInputSize = 1 } endCondition_directive; -typedef enum { full = 0, partial = 1 } earlyEnd_directive; - -#endif diff --git a/drivers/staging/erofs/namei.c b/drivers/staging/erofs/namei.c index 023f64fa2c87..c5c0dd9d9033 100644 --- a/drivers/staging/erofs/namei.c +++ b/drivers/staging/erofs/namei.c @@ -1,16 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * linux/drivers/staging/erofs/namei.c - * * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ -#include "internal.h" #include "xattr.h" #include @@ -21,9 +13,9 @@ struct erofs_qstr { }; /* based on the end of qn is accurate and it must have the trailing '\0' */ -static inline int dirnamecmp(const struct erofs_qstr *qn, - const struct erofs_qstr *qd, - unsigned int *matched) +static inline int erofs_dirnamecmp(const struct erofs_qstr *qn, + const struct erofs_qstr *qd, + unsigned int *matched) { unsigned int i = *matched; @@ -71,16 +63,16 @@ static struct erofs_dirent *find_target_dirent(struct erofs_qstr *name, unsigned int matched = min(startprfx, endprfx); struct erofs_qstr dname = { .name = data + nameoff, - .end = unlikely(mid >= ndirents - 1) ? + .end = mid >= ndirents - 1 ? data + dirblksize : data + nameoff_from_disk(de[mid + 1].nameoff, dirblksize) }; /* string comparison without already matched prefix */ - int ret = dirnamecmp(name, &dname, &matched); + int ret = erofs_dirnamecmp(name, &dname, &matched); - if (unlikely(!ret)) { + if (!ret) { return de + mid; } else if (ret > 0) { head = mid + 1; @@ -105,7 +97,7 @@ static struct page *find_target_block_classic(struct inode *dir, startprfx = endprfx = 0; head = 0; - back = inode_datablocks(dir) - 1; + back = erofs_inode_datablocks(dir) - 1; while (head <= back) { const int mid = head + (back - head) / 2; @@ -120,11 +112,14 @@ static struct page *find_target_block_classic(struct inode *dir, unsigned int matched; struct erofs_qstr dname; - if (unlikely(!ndirents)) { - DBG_BUGON(1); + if (!ndirents) { kunmap_atomic(de); put_page(page); - page = ERR_PTR(-EIO); + erofs_err(dir->i_sb, + "corrupted dir block %d @ nid %llu", + mid, EROFS_I(dir)->nid); + DBG_BUGON(1); + page = ERR_PTR(-EFSCORRUPTED); goto out; } @@ -139,17 +134,17 @@ static struct page *find_target_block_classic(struct inode *dir, EROFS_BLKSIZ); /* string comparison without already matched prefix */ - diff = dirnamecmp(name, &dname, &matched); + diff = erofs_dirnamecmp(name, &dname, &matched); kunmap_atomic(de); - if (unlikely(!diff)) { + if (!diff) { *_ndirents = 0; goto out; } else if (diff > 0) { head = mid + 1; startprfx = matched; - if (likely(!IS_ERR(candidate))) + if (!IS_ERR(candidate)) put_page(candidate); candidate = page; *_ndirents = ndirents; @@ -179,7 +174,7 @@ int erofs_namei(struct inode *dir, struct erofs_dirent *de; struct erofs_qstr qn; - if (unlikely(!dir->i_size)) + if (!dir->i_size) return -ENOENT; qn.name = name->name; @@ -188,7 +183,7 @@ int erofs_namei(struct inode *dir, ndirents = 0; page = find_target_block_classic(dir, &qn, &ndirents); - if (unlikely(IS_ERR(page))) + if (IS_ERR(page)) return PTR_ERR(page); data = kmap_atomic(page); @@ -198,7 +193,7 @@ int erofs_namei(struct inode *dir, else de = (struct erofs_dirent *)data; - if (likely(!IS_ERR(de))) { + if (!IS_ERR(de)) { *nid = le64_to_cpu(de->nid); *d_type = de->file_type; } @@ -211,11 +206,12 @@ int erofs_namei(struct inode *dir, /* NOTE: i_mutex is already held by vfs */ static struct dentry *erofs_lookup(struct inode *dir, - struct dentry *dentry, unsigned int flags) + struct dentry *dentry, + unsigned int flags) { int err; erofs_nid_t nid; - unsigned d_type; + unsigned int d_type; struct inode *inode; DBG_BUGON(!d_really_is_negative(dentry)); @@ -225,7 +221,7 @@ static struct dentry *erofs_lookup(struct inode *dir, trace_erofs_lookup(dir, dentry, flags); /* file name exceeds fs limit */ - if (unlikely(dentry->d_name.len > EROFS_NAME_LEN)) + if (dentry->d_name.len > EROFS_NAME_LEN) return ERR_PTR(-ENAMETOOLONG); /* false uninitialized warnings on gcc 4.8.x */ @@ -234,29 +230,19 @@ static struct dentry *erofs_lookup(struct inode *dir, if (err == -ENOENT) { /* negative dentry */ inode = NULL; - goto negative_out; - } else if (unlikely(err)) - return ERR_PTR(err); - - debugln("%s, %s (nid %llu) found, d_type %u", __func__, - dentry->d_name.name, nid, d_type); - - inode = erofs_iget(dir->i_sb, nid, d_type == EROFS_FT_DIR); - if (IS_ERR(inode)) - return ERR_CAST(inode); - -negative_out: + } else if (err) { + inode = ERR_PTR(err); + } else { + erofs_dbg("%s, %s (nid %llu) found, d_type %u", __func__, + dentry->d_name.name, nid, d_type); + inode = erofs_iget(dir->i_sb, nid, d_type == EROFS_FT_DIR); + } return d_splice_alias(inode, dentry); } const struct inode_operations erofs_dir_iops = { .lookup = erofs_lookup, -}; - -const struct inode_operations erofs_dir_xattr_iops = { - .lookup = erofs_lookup, -#ifdef CONFIG_EROFS_FS_XATTR + .getattr = erofs_getattr, .listxattr = erofs_listxattr, -#endif + .get_acl = erofs_get_acl, }; - diff --git a/drivers/staging/erofs/super.c b/drivers/staging/erofs/super.c index b49ebdf6ebda..13977976c719 100644 --- a/drivers/staging/erofs/super.c +++ b/drivers/staging/erofs/super.c @@ -1,188 +1,248 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * linux/drivers/staging/erofs/super.c - * * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ #include #include #include #include #include -#include "internal.h" +#include +#include "xattr.h" #define CREATE_TRACE_POINTS #include static struct kmem_cache *erofs_inode_cachep __read_mostly; -static void init_once(void *ptr) +void _erofs_err(struct super_block *sb, const char *function, + const char *fmt, ...) { - struct erofs_vnode *vi = ptr; + struct va_format vaf; + va_list args; + + va_start(args, fmt); + + vaf.fmt = fmt; + vaf.va = &args; + + pr_err("(device %s): %s: %pV", sb->s_id, function, &vaf); + va_end(args); +} + +void _erofs_info(struct super_block *sb, const char *function, + const char *fmt, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, fmt); + + vaf.fmt = fmt; + vaf.va = &args; + + pr_info("(device %s): %pV", sb->s_id, &vaf); + va_end(args); +} + +static int erofs_superblock_csum_verify(struct super_block *sb, void *sbdata) +{ + struct erofs_super_block *dsb; + u32 expected_crc, crc; + + dsb = kmemdup(sbdata + EROFS_SUPER_OFFSET, + EROFS_BLKSIZ - EROFS_SUPER_OFFSET, GFP_KERNEL); + if (!dsb) + return -ENOMEM; + + expected_crc = le32_to_cpu(dsb->checksum); + dsb->checksum = 0; + /* to allow for x86 boot sectors and other oddities. */ + crc = crc32c(~0, dsb, EROFS_BLKSIZ - EROFS_SUPER_OFFSET); + kfree(dsb); + + if (crc != expected_crc) { + erofs_err(sb, "invalid checksum 0x%08x, 0x%08x expected", + crc, expected_crc); + return -EBADMSG; + } + return 0; +} + +static void erofs_inode_init_once(void *ptr) +{ + struct erofs_inode *vi = ptr; inode_init_once(&vi->vfs_inode); } -static int erofs_init_inode_cache(void) +static struct inode *erofs_alloc_inode(struct super_block *sb) { - erofs_inode_cachep = kmem_cache_create("erofs_inode", - sizeof(struct erofs_vnode), 0, - SLAB_RECLAIM_ACCOUNT, init_once); - - return erofs_inode_cachep != NULL ? 0 : -ENOMEM; -} - -static void erofs_exit_inode_cache(void) -{ - kmem_cache_destroy(erofs_inode_cachep); -} - -static struct inode *alloc_inode(struct super_block *sb) -{ - struct erofs_vnode *vi = + struct erofs_inode *vi = kmem_cache_alloc(erofs_inode_cachep, GFP_KERNEL); - if (vi == NULL) + if (!vi) return NULL; /* zero out everything except vfs_inode */ - memset(vi, 0, offsetof(struct erofs_vnode, vfs_inode)); + memset(vi, 0, offsetof(struct erofs_inode, vfs_inode)); return &vi->vfs_inode; } static void i_callback(struct rcu_head *head) { struct inode *inode = container_of(head, struct inode, i_rcu); - struct erofs_vnode *vi = EROFS_V(inode); + struct erofs_inode *vi = EROFS_I(inode); - /* be careful RCU symlink path (see ext4_inode_info->i_data)! */ - if (is_inode_fast_symlink(inode)) + /* be careful of RCU symlink path */ + if (inode->i_op == &erofs_fast_symlink_iops) kfree(inode->i_link); - kfree(vi->xattr_shared_xattrs); kmem_cache_free(erofs_inode_cachep, vi); } -static void destroy_inode(struct inode *inode) +static void erofs_destroy_inode(struct inode *inode) { call_rcu(&inode->i_rcu, i_callback); } static bool check_layout_compatibility(struct super_block *sb, - struct erofs_super_block *layout) + struct erofs_super_block *dsb) { - const unsigned int requirements = le32_to_cpu(layout->requirements); + const unsigned int feature = le32_to_cpu(dsb->feature_incompat); - EROFS_SB(sb)->requirements = requirements; + EROFS_SB(sb)->feature_incompat = feature; /* check if current kernel meets all mandatory requirements */ - if (requirements & (~EROFS_ALL_REQUIREMENTS)) { - errln("unidentified requirements %x, please upgrade kernel version", - requirements & ~EROFS_ALL_REQUIREMENTS); + if (feature & (~EROFS_ALL_FEATURE_INCOMPAT)) { + erofs_err(sb, + "unidentified incompatible feature %x, please upgrade kernel version", + feature & ~EROFS_ALL_FEATURE_INCOMPAT); return false; } return true; } -static int superblock_read(struct super_block *sb) +static int erofs_read_superblock(struct super_block *sb) { struct erofs_sb_info *sbi; - struct buffer_head *bh; - struct erofs_super_block *layout; - unsigned blkszbits; + struct page *page; + struct erofs_super_block *dsb; + unsigned int blkszbits; + void *data; int ret; - bh = sb_bread(sb, 0); - - if (bh == NULL) { - errln("cannot read erofs superblock"); - return -EIO; + page = read_mapping_page(sb->s_bdev->bd_inode->i_mapping, 0, NULL); + if (IS_ERR(page)) { + erofs_err(sb, "cannot read erofs superblock"); + return PTR_ERR(page); } sbi = EROFS_SB(sb); - layout = (struct erofs_super_block *)((u8 *)bh->b_data - + EROFS_SUPER_OFFSET); + + data = kmap(page); + dsb = (struct erofs_super_block *)(data + EROFS_SUPER_OFFSET); ret = -EINVAL; - if (le32_to_cpu(layout->magic) != EROFS_SUPER_MAGIC_V1) { - errln("cannot find valid erofs superblock"); + if (le32_to_cpu(dsb->magic) != EROFS_SUPER_MAGIC_V1) { + erofs_err(sb, "cannot find valid erofs superblock"); goto out; } - blkszbits = layout->blkszbits; + sbi->feature_compat = le32_to_cpu(dsb->feature_compat); + if (sbi->feature_compat & EROFS_FEATURE_COMPAT_SB_CHKSUM) { + ret = erofs_superblock_csum_verify(sb, data); + if (ret) + goto out; + } + + ret = -EINVAL; + blkszbits = dsb->blkszbits; /* 9(512 bytes) + LOG_SECTORS_PER_BLOCK == LOG_BLOCK_SIZE */ - if (unlikely(blkszbits != LOG_BLOCK_SIZE)) { - errln("blksize %u isn't supported on this platform", - 1 << blkszbits); + if (blkszbits != LOG_BLOCK_SIZE) { + erofs_err(sb, "blkszbits %u isn't supported on this platform", + blkszbits); goto out; } - if (!check_layout_compatibility(sb, layout)) + if (!check_layout_compatibility(sb, dsb)) goto out; - sbi->blocks = le32_to_cpu(layout->blocks); - sbi->meta_blkaddr = le32_to_cpu(layout->meta_blkaddr); + sbi->blocks = le32_to_cpu(dsb->blocks); + sbi->meta_blkaddr = le32_to_cpu(dsb->meta_blkaddr); #ifdef CONFIG_EROFS_FS_XATTR - sbi->xattr_blkaddr = le32_to_cpu(layout->xattr_blkaddr); + sbi->xattr_blkaddr = le32_to_cpu(dsb->xattr_blkaddr); #endif - sbi->islotbits = ffs(sizeof(struct erofs_inode_v1)) - 1; -#ifdef CONFIG_EROFS_FS_ZIP - sbi->clusterbits = 12; + sbi->islotbits = ilog2(sizeof(struct erofs_inode_compact)); + sbi->root_nid = le16_to_cpu(dsb->root_nid); + sbi->inos = le64_to_cpu(dsb->inos); - if (1 << (sbi->clusterbits - 12) > Z_EROFS_CLUSTER_MAX_PAGES) - errln("clusterbits %u is not supported on this kernel", - sbi->clusterbits); -#endif + sbi->build_time = le64_to_cpu(dsb->build_time); + sbi->build_time_nsec = le32_to_cpu(dsb->build_time_nsec); - sbi->root_nid = le16_to_cpu(layout->root_nid); - sbi->inos = le64_to_cpu(layout->inos); - - sbi->build_time = le64_to_cpu(layout->build_time); - sbi->build_time_nsec = le32_to_cpu(layout->build_time_nsec); - - memcpy(&sb->s_uuid, layout->uuid, sizeof(layout->uuid)); - memcpy(sbi->volume_name, layout->volume_name, - sizeof(layout->volume_name)); + memcpy(&sb->s_uuid, dsb->uuid, sizeof(dsb->uuid)); + ret = strscpy(sbi->volume_name, dsb->volume_name, + sizeof(dsb->volume_name)); + if (ret < 0) { /* -E2BIG */ + erofs_err(sb, "bad volume name without NIL terminator"); + ret = -EFSCORRUPTED; + goto out; + } ret = 0; out: - brelse(bh); + kunmap(page); + put_page(page); return ret; } -#ifdef CONFIG_EROFS_FAULT_INJECTION -char *erofs_fault_name[FAULT_MAX] = { - [FAULT_KMALLOC] = "kmalloc", -}; - -static void erofs_build_fault_attr(struct erofs_sb_info *sbi, - unsigned int rate) +#ifdef CONFIG_EROFS_FS_ZIP +static int erofs_build_cache_strategy(struct super_block *sb, + substring_t *args) { - struct erofs_fault_info *ffi = &sbi->fault_info; + struct erofs_sb_info *sbi = EROFS_SB(sb); + const char *cs = match_strdup(args); + int err = 0; - if (rate) { - atomic_set(&ffi->inject_ops, 0); - ffi->inject_rate = rate; - ffi->inject_type = (1 << FAULT_MAX) - 1; - } else { - memset(ffi, 0, sizeof(struct erofs_fault_info)); + if (!cs) { + erofs_err(sb, "Not enough memory to store cache strategy"); + return -ENOMEM; } + + if (!strcmp(cs, "disabled")) { + sbi->cache_strategy = EROFS_ZIP_CACHE_DISABLED; + } else if (!strcmp(cs, "readahead")) { + sbi->cache_strategy = EROFS_ZIP_CACHE_READAHEAD; + } else if (!strcmp(cs, "readaround")) { + sbi->cache_strategy = EROFS_ZIP_CACHE_READAROUND; + } else { + erofs_err(sb, "Unrecognized cache strategy \"%s\"", cs); + err = -EINVAL; + } + kfree(cs); + return err; +} +#else +static int erofs_build_cache_strategy(struct super_block *sb, + substring_t *args) +{ + erofs_info(sb, "EROFS compression is disabled, so cache strategy is ignored"); + return 0; } #endif -static void default_options(struct erofs_sb_info *sbi) +/* set up default EROFS parameters */ +static void erofs_default_options(struct erofs_sb_info *sbi) { +#ifdef CONFIG_EROFS_FS_ZIP + sbi->cache_strategy = EROFS_ZIP_CACHE_READAROUND; + sbi->max_sync_decompress_pages = 3; +#endif #ifdef CONFIG_EROFS_FS_XATTR set_opt(sbi, XATTR_USER); #endif - #ifdef CONFIG_EROFS_FS_POSIX_ACL set_opt(sbi, POSIX_ACL); #endif @@ -193,7 +253,7 @@ enum { Opt_nouser_xattr, Opt_acl, Opt_noacl, - Opt_fault_injection, + Opt_cache_strategy, Opt_err }; @@ -202,20 +262,20 @@ static match_table_t erofs_tokens = { {Opt_nouser_xattr, "nouser_xattr"}, {Opt_acl, "acl"}, {Opt_noacl, "noacl"}, - {Opt_fault_injection, "fault_injection=%u"}, + {Opt_cache_strategy, "cache_strategy=%s"}, {Opt_err, NULL} }; -static int parse_options(struct super_block *sb, char *options) +static int erofs_parse_options(struct super_block *sb, char *options) { substring_t args[MAX_OPT_ARGS]; char *p; - int arg = 0; + int err; if (!options) return 0; - while ((p = strsep(&options, ",")) != NULL) { + while ((p = strsep(&options, ","))) { int token; if (!*p) @@ -234,10 +294,10 @@ static int parse_options(struct super_block *sb, char *options) break; #else case Opt_user_xattr: - infoln("user_xattr options not supported"); + erofs_info(sb, "user_xattr options not supported"); break; case Opt_nouser_xattr: - infoln("nouser_xattr options not supported"); + erofs_info(sb, "nouser_xattr options not supported"); break; #endif #ifdef CONFIG_EROFS_FS_POSIX_ACL @@ -249,36 +309,29 @@ static int parse_options(struct super_block *sb, char *options) break; #else case Opt_acl: - infoln("acl options not supported"); + erofs_info(sb, "acl options not supported"); break; case Opt_noacl: - infoln("noacl options not supported"); + erofs_info(sb, "noacl options not supported"); break; #endif - case Opt_fault_injection: - if (args->from && match_int(args, &arg)) - return -EINVAL; -#ifdef CONFIG_EROFS_FAULT_INJECTION - erofs_build_fault_attr(EROFS_SB(sb), arg); - set_opt(EROFS_SB(sb), FAULT_INJECTION); -#else - infoln("FAULT_INJECTION was not selected"); -#endif + case Opt_cache_strategy: + err = erofs_build_cache_strategy(sb, args); + if (err) + return err; break; default: - errln("Unrecognized mount option \"%s\" " - "or missing value", p); + erofs_err(sb, "Unrecognized mount option \"%s\" or missing value", p); return -EINVAL; } } return 0; } -#ifdef EROFS_FS_HAS_MANAGED_CACHE - +#ifdef CONFIG_EROFS_FS_ZIP static const struct address_space_operations managed_cache_aops; -static int managed_cache_releasepage(struct page *page, gfp_t gfp_mask) +static int erofs_managed_cache_releasepage(struct page *page, gfp_t gfp_mask) { int ret = 1; /* 0 - busy */ struct address_space *const mapping = page->mapping; @@ -292,8 +345,9 @@ static int managed_cache_releasepage(struct page *page, gfp_t gfp_mask) return ret; } -static void managed_cache_invalidatepage(struct page *page, - unsigned int offset, unsigned int length) +static void erofs_managed_cache_invalidatepage(struct page *page, + unsigned int offset, + unsigned int length) { const unsigned int stop = length + offset; @@ -303,227 +357,147 @@ static void managed_cache_invalidatepage(struct page *page, DBG_BUGON(stop > PAGE_SIZE || stop < length); if (offset == 0 && stop == PAGE_SIZE) - while (!managed_cache_releasepage(page, GFP_NOFS)) + while (!erofs_managed_cache_releasepage(page, GFP_NOFS)) cond_resched(); } static const struct address_space_operations managed_cache_aops = { - .releasepage = managed_cache_releasepage, - .invalidatepage = managed_cache_invalidatepage, + .releasepage = erofs_managed_cache_releasepage, + .invalidatepage = erofs_managed_cache_invalidatepage, }; -static struct inode *erofs_init_managed_cache(struct super_block *sb) +static int erofs_init_managed_cache(struct super_block *sb) { - struct inode *inode = new_inode(sb); + struct erofs_sb_info *const sbi = EROFS_SB(sb); + struct inode *const inode = new_inode(sb); - if (unlikely(inode == NULL)) - return ERR_PTR(-ENOMEM); + if (!inode) + return -ENOMEM; set_nlink(inode, 1); inode->i_size = OFFSET_MAX; inode->i_mapping->a_ops = &managed_cache_aops; mapping_set_gfp_mask(inode->i_mapping, - GFP_NOFS | __GFP_HIGHMEM | - __GFP_MOVABLE | __GFP_NOFAIL); - return inode; + GFP_NOFS | __GFP_HIGHMEM | __GFP_MOVABLE); + sbi->managed_cache = inode; + return 0; } - +#else +static int erofs_init_managed_cache(struct super_block *sb) { return 0; } #endif -static int erofs_read_super(struct super_block *sb, - const char *dev_name, void *data, int silent) +static int erofs_fill_super(struct super_block *sb, void *data, int silent) { struct inode *inode; struct erofs_sb_info *sbi; - int err = -EINVAL; - - infoln("read_super, device -> %s", dev_name); - infoln("options -> %s", (char *)data); - - if (unlikely(!sb_set_blocksize(sb, EROFS_BLKSIZ))) { - errln("failed to set erofs blksize"); - goto err; - } - - sbi = kzalloc(sizeof(struct erofs_sb_info), GFP_KERNEL); - if (unlikely(sbi == NULL)) { - err = -ENOMEM; - goto err; - } - sb->s_fs_info = sbi; - - err = superblock_read(sb); - if (err) - goto err_sbread; + int err; sb->s_magic = EROFS_SUPER_MAGIC; + + if (!sb_set_blocksize(sb, EROFS_BLKSIZ)) { + erofs_err(sb, "failed to set erofs blksize"); + return -EINVAL; + } + + sbi = kzalloc(sizeof(*sbi), GFP_KERNEL); + if (!sbi) + return -ENOMEM; + + sb->s_fs_info = sbi; + err = erofs_read_superblock(sb); + if (err) + return err; + sb->s_flags |= SB_RDONLY | SB_NOATIME; sb->s_maxbytes = MAX_LFS_FILESIZE; sb->s_time_gran = 1; sb->s_op = &erofs_sops; - -#ifdef CONFIG_EROFS_FS_XATTR sb->s_xattr = erofs_xattr_handlers; -#endif /* set erofs default mount options */ - default_options(sbi); + erofs_default_options(sbi); - err = parse_options(sb, data); + err = erofs_parse_options(sb, data); if (err) - goto err_parseopt; + return err; - if (!silent) - infoln("root inode @ nid %llu", ROOT_NID(sbi)); + if (test_opt(sbi, POSIX_ACL)) + sb->s_flags |= SB_POSIXACL; + else + sb->s_flags &= ~SB_POSIXACL; #ifdef CONFIG_EROFS_FS_ZIP INIT_RADIX_TREE(&sbi->workstn_tree, GFP_ATOMIC); #endif -#ifdef EROFS_FS_HAS_MANAGED_CACHE - sbi->managed_cache = erofs_init_managed_cache(sb); - if (IS_ERR(sbi->managed_cache)) { - err = PTR_ERR(sbi->managed_cache); - goto err_init_managed_cache; - } -#endif - /* get the root inode */ inode = erofs_iget(sb, ROOT_NID(sbi), true); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto err_iget; - } + if (IS_ERR(inode)) + return PTR_ERR(inode); if (!S_ISDIR(inode->i_mode)) { - errln("rootino(nid %llu) is not a directory(i_mode %o)", - ROOT_NID(sbi), inode->i_mode); - err = -EINVAL; - goto err_isdir; + erofs_err(sb, "rootino(nid %llu) is not a directory(i_mode %o)", + ROOT_NID(sbi), inode->i_mode); + iput(inode); + return -EINVAL; } sb->s_root = d_make_root(inode); - if (sb->s_root == NULL) { - err = -ENOMEM; - goto err_makeroot; - } + if (!sb->s_root) + return -ENOMEM; - /* save the device name to sbi */ - sbi->dev_name = __getname(); - if (sbi->dev_name == NULL) { - err = -ENOMEM; - goto err_devname; - } + erofs_shrinker_register(sb); + /* sb->s_umount is already locked, SB_ACTIVE and SB_BORN are not set */ + err = erofs_init_managed_cache(sb); + if (err) + return err; - snprintf(sbi->dev_name, PATH_MAX, "%s", dev_name); - sbi->dev_name[PATH_MAX - 1] = '\0'; - - erofs_register_super(sb); - - if (!silent) - infoln("mounted on %s with opts: %s.", dev_name, - (char *)data); + erofs_info(sb, "mounted with opts: %s, root inode @ nid %llu.", + (char *)data, ROOT_NID(sbi)); return 0; - /* - * please add a label for each exit point and use - * the following name convention, thus new features - * can be integrated easily without renaming labels. - */ -err_devname: - dput(sb->s_root); -err_makeroot: -err_isdir: - if (sb->s_root == NULL) - iput(inode); -err_iget: -#ifdef EROFS_FS_HAS_MANAGED_CACHE - iput(sbi->managed_cache); -err_init_managed_cache: -#endif -err_parseopt: -err_sbread: - sb->s_fs_info = NULL; - kfree(sbi); -err: - return err; +} + +static struct dentry *erofs_mount(struct file_system_type *fs_type, int flags, + const char *dev_name, void *data) +{ + return mount_bdev(fs_type, flags, dev_name, data, erofs_fill_super); } /* * could be triggered after deactivate_locked_super() * is called, thus including umount and failed to initialize. */ -static void erofs_put_super(struct super_block *sb) +static void erofs_kill_sb(struct super_block *sb) { - struct erofs_sb_info *sbi = EROFS_SB(sb); - - /* for cases which are failed in "read_super" */ - if (sbi == NULL) - return; + struct erofs_sb_info *sbi; WARN_ON(sb->s_magic != EROFS_SUPER_MAGIC); - infoln("unmounted for %s", sbi->dev_name); - __putname(sbi->dev_name); - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - iput(sbi->managed_cache); -#endif - - mutex_lock(&sbi->umount_mutex); - -#ifdef CONFIG_EROFS_FS_ZIP - erofs_workstation_cleanup_all(sb); -#endif - - erofs_unregister_super(sb); - mutex_unlock(&sbi->umount_mutex); + kill_block_super(sb); + sbi = EROFS_SB(sb); + if (!sbi) + return; kfree(sbi); sb->s_fs_info = NULL; } - -struct erofs_mount_private { - const char *dev_name; - char *options; -}; - -/* support mount_bdev() with options */ -static int erofs_fill_super(struct super_block *sb, - void *_priv, int silent) +/* called when ->s_root is non-NULL */ +static void erofs_put_super(struct super_block *sb) { - struct erofs_mount_private *priv = _priv; + struct erofs_sb_info *const sbi = EROFS_SB(sb); - return erofs_read_super(sb, priv->dev_name, - priv->options, silent); + DBG_BUGON(!sbi); + + erofs_shrinker_unregister(sb); +#ifdef CONFIG_EROFS_FS_ZIP + iput(sbi->managed_cache); + sbi->managed_cache = NULL; +#endif } -static struct dentry *erofs_mount( - struct file_system_type *fs_type, int flags, - const char *dev_name, void *data) -{ - struct erofs_mount_private priv = { - .dev_name = dev_name, - .options = data - }; - - return mount_bdev(fs_type, flags, dev_name, - &priv, erofs_fill_super); -} - -static void erofs_kill_sb(struct super_block *sb) -{ - kill_block_super(sb); -} - -static struct shrinker erofs_shrinker_info = { - .scan_objects = erofs_shrink_scan, - .count_objects = erofs_shrink_count, - .seeks = DEFAULT_SEEKS, -}; - static struct file_system_type erofs_fs_type = { .owner = THIS_MODULE, .name = "erofs", @@ -533,47 +507,41 @@ static struct file_system_type erofs_fs_type = { }; MODULE_ALIAS_FS("erofs"); -#ifdef CONFIG_EROFS_FS_ZIP -extern int z_erofs_init_zip_subsystem(void); -extern void z_erofs_exit_zip_subsystem(void); -#endif - static int __init erofs_module_init(void) { int err; erofs_check_ondisk_layout_definitions(); - infoln("initializing erofs " EROFS_VERSION); - err = erofs_init_inode_cache(); - if (err) + erofs_inode_cachep = kmem_cache_create("erofs_inode", + sizeof(struct erofs_inode), 0, + SLAB_RECLAIM_ACCOUNT, + erofs_inode_init_once); + if (!erofs_inode_cachep) { + err = -ENOMEM; goto icache_err; + } - err = register_shrinker(&erofs_shrinker_info); + err = erofs_init_shrinker(); if (err) goto shrinker_err; -#ifdef CONFIG_EROFS_FS_ZIP err = z_erofs_init_zip_subsystem(); if (err) goto zip_err; -#endif err = register_filesystem(&erofs_fs_type); if (err) goto fs_err; - infoln("successfully to initialize erofs"); return 0; fs_err: -#ifdef CONFIG_EROFS_FS_ZIP z_erofs_exit_zip_subsystem(); zip_err: -#endif - unregister_shrinker(&erofs_shrinker_info); + erofs_exit_shrinker(); shrinker_err: - erofs_exit_inode_cache(); + kmem_cache_destroy(erofs_inode_cachep); icache_err: return err; } @@ -581,12 +549,12 @@ static int __init erofs_module_init(void) static void __exit erofs_module_exit(void) { unregister_filesystem(&erofs_fs_type); -#ifdef CONFIG_EROFS_FS_ZIP z_erofs_exit_zip_subsystem(); -#endif - unregister_shrinker(&erofs_shrinker_info); - erofs_exit_inode_cache(); - infoln("successfully finalize erofs"); + erofs_exit_shrinker(); + + /* Ensure all RCU free inodes are safe before cache is destroyed. */ + rcu_barrier(); + kmem_cache_destroy(erofs_inode_cachep); } /* get filesystem statistics */ @@ -627,26 +595,45 @@ static int erofs_show_options(struct seq_file *seq, struct dentry *root) else seq_puts(seq, ",noacl"); #endif -#ifdef CONFIG_EROFS_FAULT_INJECTION - if (test_opt(sbi, FAULT_INJECTION)) - seq_printf(seq, ",fault_injection=%u", - sbi->fault_info.inject_rate); +#ifdef CONFIG_EROFS_FS_ZIP + if (sbi->cache_strategy == EROFS_ZIP_CACHE_DISABLED) { + seq_puts(seq, ",cache_strategy=disabled"); + } else if (sbi->cache_strategy == EROFS_ZIP_CACHE_READAHEAD) { + seq_puts(seq, ",cache_strategy=readahead"); + } else if (sbi->cache_strategy == EROFS_ZIP_CACHE_READAROUND) { + seq_puts(seq, ",cache_strategy=readaround"); + } #endif return 0; } static int erofs_remount(struct super_block *sb, int *flags, char *data) { + struct erofs_sb_info *sbi = EROFS_SB(sb); + unsigned int org_mnt_opt = sbi->mount_opt; + int err; + DBG_BUGON(!sb_rdonly(sb)); + err = erofs_parse_options(sb, data); + if (err) + goto out; + + if (test_opt(sbi, POSIX_ACL)) + sb->s_flags |= SB_POSIXACL; + else + sb->s_flags &= ~SB_POSIXACL; *flags |= SB_RDONLY; return 0; +out: + sbi->mount_opt = org_mnt_opt; + return err; } const struct super_operations erofs_sops = { .put_super = erofs_put_super, - .alloc_inode = alloc_inode, - .destroy_inode = destroy_inode, + .alloc_inode = erofs_alloc_inode, + .destroy_inode = erofs_destroy_inode, .statfs = erofs_statfs, .show_options = erofs_show_options, .remount_fs = erofs_remount, @@ -656,6 +643,5 @@ module_init(erofs_module_init); module_exit(erofs_module_exit); MODULE_DESCRIPTION("Enhanced ROM File System"); -MODULE_AUTHOR("Gao Xiang, Yu Chao, Miao Xie, CONSUMER BG, HUAWEI Inc."); +MODULE_AUTHOR("Gao Xiang, Chao Yu, Miao Xie, CONSUMER BG, HUAWEI Inc."); MODULE_LICENSE("GPL"); - diff --git a/drivers/staging/erofs/include/linux/tagptr.h b/drivers/staging/erofs/tagptr.h similarity index 93% rename from drivers/staging/erofs/include/linux/tagptr.h rename to drivers/staging/erofs/tagptr.h index ccd106dbd48e..64ceb7270b5c 100644 --- a/drivers/staging/erofs/include/linux/tagptr.h +++ b/drivers/staging/erofs/tagptr.h @@ -1,11 +1,9 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Tagged pointer implementation - * - * Copyright (C) 2018 Gao Xiang +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * A tagged pointer implementation */ -#ifndef _LINUX_TAGPTR_H -#define _LINUX_TAGPTR_H +#ifndef __EROFS_FS_TAGPTR_H +#define __EROFS_FS_TAGPTR_H #include #include @@ -106,5 +104,4 @@ tagptr_init(o, cmpxchg(&ptptr->v, o.v, n.v)); }) ptptr->v &= ~tags; \ *ptptr; }) -#endif - +#endif /* __EROFS_FS_TAGPTR_H */ diff --git a/drivers/staging/erofs/unzip_lz4.c b/drivers/staging/erofs/unzip_lz4.c deleted file mode 100644 index b1ea23f66c4e..000000000000 --- a/drivers/staging/erofs/unzip_lz4.c +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -/* - * linux/drivers/staging/erofs/unzip_lz4.c - * - * Copyright (C) 2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * Original code taken from 'linux/lib/lz4/lz4_decompress.c' - */ - -/* - * LZ4 - Fast LZ compression algorithm - * Copyright (C) 2011 - 2016, Yann Collet. - * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php) - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * You can contact the author at : - * - LZ4 homepage : http://www.lz4.org - * - LZ4 source repository : https://github.com/lz4/lz4 - * - * Changed for kernel usage by: - * Sven Schmidt <4sschmid@informatik.uni-hamburg.de> - */ -#include "internal.h" -#include -#include "lz4defs.h" - -/* - * no public solution to solve our requirement yet. - * see: - * https://groups.google.com/forum/#!topic/lz4c/_3kkz5N6n00 - */ -static FORCE_INLINE int customized_lz4_decompress_safe_partial( - const void * const source, - void * const dest, - int inputSize, - int outputSize) -{ - /* Local Variables */ - const BYTE *ip = (const BYTE *) source; - const BYTE * const iend = ip + inputSize; - - BYTE *op = (BYTE *) dest; - BYTE * const oend = op + outputSize; - BYTE *cpy; - - static const unsigned int dec32table[] = { 0, 1, 2, 1, 4, 4, 4, 4 }; - static const int dec64table[] = { 0, 0, 0, -1, 0, 1, 2, 3 }; - - /* Empty output buffer */ - if (unlikely(outputSize == 0)) - return ((inputSize == 1) && (*ip == 0)) ? 0 : -1; - - /* Main Loop : decode sequences */ - while (1) { - size_t length; - const BYTE *match; - size_t offset; - - /* get literal length */ - unsigned int const token = *ip++; - - length = token>>ML_BITS; - - if (length == RUN_MASK) { - unsigned int s; - - do { - s = *ip++; - length += s; - } while ((ip < iend - RUN_MASK) & (s == 255)); - - if (unlikely((size_t)(op + length) < (size_t)(op))) { - /* overflow detection */ - goto _output_error; - } - if (unlikely((size_t)(ip + length) < (size_t)(ip))) { - /* overflow detection */ - goto _output_error; - } - } - - /* copy literals */ - cpy = op + length; - if ((cpy > oend - WILDCOPYLENGTH) || - (ip + length > iend - (2 + 1 + LASTLITERALS))) { - if (cpy > oend) { - memcpy(op, ip, length = oend - op); - op += length; - break; - } - - if (unlikely(ip + length > iend)) { - /* - * Error : - * read attempt beyond - * end of input buffer - */ - goto _output_error; - } - - memcpy(op, ip, length); - ip += length; - op += length; - - if (ip > iend - 2) - break; - /* Necessarily EOF, due to parsing restrictions */ - /* break; */ - } else { - LZ4_wildCopy(op, ip, cpy); - ip += length; - op = cpy; - } - - /* get offset */ - offset = LZ4_readLE16(ip); - ip += 2; - match = op - offset; - - if (unlikely(match < (const BYTE *)dest)) { - /* Error : offset outside buffers */ - goto _output_error; - } - - /* get matchlength */ - length = token & ML_MASK; - if (length == ML_MASK) { - unsigned int s; - - do { - s = *ip++; - - if (ip > iend - LASTLITERALS) - goto _output_error; - - length += s; - } while (s == 255); - - if (unlikely((size_t)(op + length) < (size_t)op)) { - /* overflow detection */ - goto _output_error; - } - } - - length += MINMATCH; - - /* copy match within block */ - cpy = op + length; - - if (unlikely(cpy >= oend - WILDCOPYLENGTH)) { - if (cpy >= oend) { - while (op < oend) - *op++ = *match++; - break; - } - goto __match; - } - - /* costs ~1%; silence an msan warning when offset == 0 */ - LZ4_write32(op, (U32)offset); - - if (unlikely(offset < 8)) { - const int dec64 = dec64table[offset]; - - op[0] = match[0]; - op[1] = match[1]; - op[2] = match[2]; - op[3] = match[3]; - match += dec32table[offset]; - memcpy(op + 4, match, 4); - match -= dec64; - } else { - LZ4_copy8(op, match); - match += 8; - } - - op += 8; - - if (unlikely(cpy > oend - 12)) { - BYTE * const oCopyLimit = oend - (WILDCOPYLENGTH - 1); - - if (op < oCopyLimit) { - LZ4_wildCopy(op, match, oCopyLimit); - match += oCopyLimit - op; - op = oCopyLimit; - } -__match: - while (op < cpy) - *op++ = *match++; - } else { - LZ4_copy8(op, match); - - if (length > 16) - LZ4_wildCopy(op + 8, match + 8, cpy); - } - - op = cpy; /* correction */ - } - DBG_BUGON((void *)ip - source > inputSize); - DBG_BUGON((void *)op - dest > outputSize); - - /* Nb of output bytes decoded */ - return (int) ((void *)op - dest); - - /* Overflow error detected */ -_output_error: - return -ERANGE; -} - -int z_erofs_unzip_lz4(void *in, void *out, size_t inlen, size_t outlen) -{ - int ret = customized_lz4_decompress_safe_partial(in, - out, inlen, outlen); - - if (ret >= 0) - return ret; - - /* - * LZ4_decompress_safe will return an error code - * (< 0) if decompression failed - */ - errln("%s, failed to decompress, in[%p, %zu] outlen[%p, %zu]", - __func__, in, inlen, out, outlen); - WARN_ON(1); - print_hex_dump(KERN_DEBUG, "raw data [in]: ", DUMP_PREFIX_OFFSET, - 16, 1, in, inlen, true); - print_hex_dump(KERN_DEBUG, "raw data [out]: ", DUMP_PREFIX_OFFSET, - 16, 1, out, outlen, true); - return -EIO; -} - diff --git a/drivers/staging/erofs/unzip_vle.c b/drivers/staging/erofs/unzip_vle.c deleted file mode 100644 index 0f1558c6747e..000000000000 --- a/drivers/staging/erofs/unzip_vle.c +++ /dev/null @@ -1,1695 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/drivers/staging/erofs/unzip_vle.c - * - * Copyright (C) 2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. - */ -#include "unzip_vle.h" -#include - -static struct workqueue_struct *z_erofs_workqueue __read_mostly; -static struct kmem_cache *z_erofs_workgroup_cachep __read_mostly; - -void z_erofs_exit_zip_subsystem(void) -{ - destroy_workqueue(z_erofs_workqueue); - kmem_cache_destroy(z_erofs_workgroup_cachep); -} - -static inline int init_unzip_workqueue(void) -{ - const unsigned onlinecpus = num_possible_cpus(); - - /* - * we don't need too many threads, limiting threads - * could improve scheduling performance. - */ - z_erofs_workqueue = alloc_workqueue("erofs_unzipd", - WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, - onlinecpus + onlinecpus / 4); - - return z_erofs_workqueue != NULL ? 0 : -ENOMEM; -} - -int z_erofs_init_zip_subsystem(void) -{ - z_erofs_workgroup_cachep = - kmem_cache_create("erofs_compress", - Z_EROFS_WORKGROUP_SIZE, 0, - SLAB_RECLAIM_ACCOUNT, NULL); - - if (z_erofs_workgroup_cachep != NULL) { - if (!init_unzip_workqueue()) - return 0; - - kmem_cache_destroy(z_erofs_workgroup_cachep); - } - return -ENOMEM; -} - -enum z_erofs_vle_work_role { - Z_EROFS_VLE_WORK_SECONDARY, - Z_EROFS_VLE_WORK_PRIMARY, - /* - * The current work was the tail of an exist chain, and the previous - * processed chained works are all decided to be hooked up to it. - * A new chain should be created for the remaining unprocessed works, - * therefore different from Z_EROFS_VLE_WORK_PRIMARY_FOLLOWED, - * the next work cannot reuse the whole page in the following scenario: - * ________________________________________________________________ - * | tail (partial) page | head (partial) page | - * | (belongs to the next work) | (belongs to the current work) | - * |_______PRIMARY_FOLLOWED_______|________PRIMARY_HOOKED___________| - */ - Z_EROFS_VLE_WORK_PRIMARY_HOOKED, - /* - * The current work has been linked with the processed chained works, - * and could be also linked with the potential remaining works, which - * means if the processing page is the tail partial page of the work, - * the current work can safely use the whole page (since the next work - * is under control) for in-place decompression, as illustrated below: - * ________________________________________________________________ - * | tail (partial) page | head (partial) page | - * | (of the current work) | (of the previous work) | - * | PRIMARY_FOLLOWED or | | - * |_____PRIMARY_HOOKED____|____________PRIMARY_FOLLOWED____________| - * - * [ (*) the above page can be used for the current work itself. ] - */ - Z_EROFS_VLE_WORK_PRIMARY_FOLLOWED, - Z_EROFS_VLE_WORK_MAX -}; - -struct z_erofs_vle_work_builder { - enum z_erofs_vle_work_role role; - /* - * 'hosted = false' means that the current workgroup doesn't belong to - * the owned chained workgroups. In the other words, it is none of our - * business to submit this workgroup. - */ - bool hosted; - - struct z_erofs_vle_workgroup *grp; - struct z_erofs_vle_work *work; - struct z_erofs_pagevec_ctor vector; - - /* pages used for reading the compressed data */ - struct page **compressed_pages; - unsigned compressed_deficit; -}; - -#define VLE_WORK_BUILDER_INIT() \ - { .work = NULL, .role = Z_EROFS_VLE_WORK_PRIMARY_FOLLOWED } - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - -static bool grab_managed_cache_pages(struct address_space *mapping, - erofs_blk_t start, - struct page **compressed_pages, - int clusterblks, - bool reserve_allocation) -{ - bool noio = true; - unsigned int i; - - /* TODO: optimize by introducing find_get_pages_range */ - for (i = 0; i < clusterblks; ++i) { - struct page *page, *found; - - if (READ_ONCE(compressed_pages[i]) != NULL) - continue; - - page = found = find_get_page(mapping, start + i); - if (found == NULL) { - noio = false; - if (!reserve_allocation) - continue; - page = EROFS_UNALLOCATED_CACHED_PAGE; - } - - if (NULL == cmpxchg(compressed_pages + i, NULL, page)) - continue; - - if (found != NULL) - put_page(found); - } - return noio; -} - -/* called by erofs_shrinker to get rid of all compressed_pages */ -int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, - struct erofs_workgroup *egrp) -{ - struct z_erofs_vle_workgroup *const grp = - container_of(egrp, struct z_erofs_vle_workgroup, obj); - struct address_space *const mapping = sbi->managed_cache->i_mapping; - const int clusterpages = erofs_clusterpages(sbi); - int i; - - /* - * refcount of workgroup is now freezed as 1, - * therefore no need to worry about available decompression users. - */ - for (i = 0; i < clusterpages; ++i) { - struct page *page = grp->compressed_pages[i]; - - if (page == NULL || page->mapping != mapping) - continue; - - /* block other users from reclaiming or migrating the page */ - if (!trylock_page(page)) - return -EBUSY; - - /* barrier is implied in the following 'unlock_page' */ - WRITE_ONCE(grp->compressed_pages[i], NULL); - - set_page_private(page, 0); - ClearPagePrivate(page); - - unlock_page(page); - put_page(page); - } - return 0; -} - -int erofs_try_to_free_cached_page(struct address_space *mapping, - struct page *page) -{ - struct erofs_sb_info *const sbi = EROFS_SB(mapping->host->i_sb); - const unsigned int clusterpages = erofs_clusterpages(sbi); - - struct z_erofs_vle_workgroup *grp; - int ret = 0; /* 0 - busy */ - - /* prevent the workgroup from being freed */ - rcu_read_lock(); - grp = (void *)page_private(page); - - if (erofs_workgroup_try_to_freeze(&grp->obj, 1)) { - unsigned int i; - - for (i = 0; i < clusterpages; ++i) { - if (grp->compressed_pages[i] == page) { - WRITE_ONCE(grp->compressed_pages[i], NULL); - ret = 1; - break; - } - } - erofs_workgroup_unfreeze(&grp->obj, 1); - } - rcu_read_unlock(); - - if (ret) { - ClearPagePrivate(page); - put_page(page); - } - return ret; -} -#endif - -/* page_type must be Z_EROFS_PAGE_TYPE_EXCLUSIVE */ -static inline bool try_to_reuse_as_compressed_page( - struct z_erofs_vle_work_builder *b, - struct page *page) -{ - while (b->compressed_deficit) { - --b->compressed_deficit; - if (NULL == cmpxchg(b->compressed_pages++, NULL, page)) - return true; - } - - return false; -} - -/* callers must be with work->lock held */ -static int z_erofs_vle_work_add_page( - struct z_erofs_vle_work_builder *builder, - struct page *page, - enum z_erofs_page_type type) -{ - int ret; - bool occupied; - - /* give priority for the compressed data storage */ - if (builder->role >= Z_EROFS_VLE_WORK_PRIMARY && - type == Z_EROFS_PAGE_TYPE_EXCLUSIVE && - try_to_reuse_as_compressed_page(builder, page)) - return 0; - - ret = z_erofs_pagevec_ctor_enqueue(&builder->vector, - page, type, &occupied); - builder->work->vcnt += (unsigned)ret; - - return ret ? 0 : -EAGAIN; -} - -static enum z_erofs_vle_work_role -try_to_claim_workgroup(struct z_erofs_vle_workgroup *grp, - z_erofs_vle_owned_workgrp_t *owned_head, - bool *hosted) -{ - DBG_BUGON(*hosted == true); - - /* let's claim these following types of workgroup */ -retry: - if (grp->next == Z_EROFS_VLE_WORKGRP_NIL) { - /* type 1, nil workgroup */ - if (Z_EROFS_VLE_WORKGRP_NIL != cmpxchg(&grp->next, - Z_EROFS_VLE_WORKGRP_NIL, *owned_head)) - goto retry; - - *owned_head = grp; - *hosted = true; - /* lucky, I am the followee :) */ - return Z_EROFS_VLE_WORK_PRIMARY_FOLLOWED; - - } else if (grp->next == Z_EROFS_VLE_WORKGRP_TAIL) { - /* - * type 2, link to the end of a existing open chain, - * be careful that its submission itself is governed - * by the original owned chain. - */ - if (Z_EROFS_VLE_WORKGRP_TAIL != cmpxchg(&grp->next, - Z_EROFS_VLE_WORKGRP_TAIL, *owned_head)) - goto retry; - *owned_head = Z_EROFS_VLE_WORKGRP_TAIL; - return Z_EROFS_VLE_WORK_PRIMARY_HOOKED; - } - - return Z_EROFS_VLE_WORK_PRIMARY; /* :( better luck next time */ -} - -static struct z_erofs_vle_work * -z_erofs_vle_work_lookup(struct super_block *sb, - pgoff_t idx, unsigned pageofs, - struct z_erofs_vle_workgroup **grp_ret, - enum z_erofs_vle_work_role *role, - z_erofs_vle_owned_workgrp_t *owned_head, - bool *hosted) -{ - bool tag, primary; - struct erofs_workgroup *egrp; - struct z_erofs_vle_workgroup *grp; - struct z_erofs_vle_work *work; - - egrp = erofs_find_workgroup(sb, idx, &tag); - if (egrp == NULL) { - *grp_ret = NULL; - return NULL; - } - - *grp_ret = grp = container_of(egrp, - struct z_erofs_vle_workgroup, obj); - - work = z_erofs_vle_grab_work(grp, pageofs); - /* if multiref is disabled, `primary' is always true */ - primary = true; - - if (work->pageofs != pageofs) { - DBG_BUGON(1); - erofs_workgroup_put(egrp); - return ERR_PTR(-EIO); - } - - /* - * lock must be taken first to avoid grp->next == NIL between - * claiming workgroup and adding pages: - * grp->next != NIL - * grp->next = NIL - * mutex_unlock_all - * mutex_lock(&work->lock) - * add all pages to pagevec - * - * [correct locking case 1]: - * mutex_lock(grp->work[a]) - * ... - * mutex_lock(grp->work[b]) mutex_lock(grp->work[c]) - * ... *role = SECONDARY - * add all pages to pagevec - * ... - * mutex_unlock(grp->work[c]) - * mutex_lock(grp->work[c]) - * ... - * grp->next = NIL - * mutex_unlock_all - * - * [correct locking case 2]: - * mutex_lock(grp->work[b]) - * ... - * mutex_lock(grp->work[a]) - * ... - * mutex_lock(grp->work[c]) - * ... - * grp->next = NIL - * mutex_unlock_all - * mutex_lock(grp->work[a]) - * *role = PRIMARY_OWNER - * add all pages to pagevec - * ... - */ - mutex_lock(&work->lock); - - *hosted = false; - if (!primary) - *role = Z_EROFS_VLE_WORK_SECONDARY; - else /* claim the workgroup if possible */ - *role = try_to_claim_workgroup(grp, owned_head, hosted); - return work; -} - -static struct z_erofs_vle_work * -z_erofs_vle_work_register(struct super_block *sb, - struct z_erofs_vle_workgroup **grp_ret, - struct erofs_map_blocks *map, - pgoff_t index, unsigned pageofs, - enum z_erofs_vle_work_role *role, - z_erofs_vle_owned_workgrp_t *owned_head, - bool *hosted) -{ - bool newgrp = false; - struct z_erofs_vle_workgroup *grp = *grp_ret; - struct z_erofs_vle_work *work; - - /* if multiref is disabled, grp should never be nullptr */ - if (unlikely(grp)) { - DBG_BUGON(1); - return ERR_PTR(-EINVAL); - } - - /* no available workgroup, let's allocate one */ - grp = kmem_cache_zalloc(z_erofs_workgroup_cachep, GFP_NOFS); - if (unlikely(grp == NULL)) - return ERR_PTR(-ENOMEM); - - grp->obj.index = index; - grp->llen = map->m_llen; - - z_erofs_vle_set_workgrp_fmt(grp, - (map->m_flags & EROFS_MAP_ZIPPED) ? - Z_EROFS_VLE_WORKGRP_FMT_LZ4 : - Z_EROFS_VLE_WORKGRP_FMT_PLAIN); - atomic_set(&grp->obj.refcount, 1); - - /* new workgrps have been claimed as type 1 */ - WRITE_ONCE(grp->next, *owned_head); - /* primary and followed work for all new workgrps */ - *role = Z_EROFS_VLE_WORK_PRIMARY_FOLLOWED; - /* it should be submitted by ourselves */ - *hosted = true; - - newgrp = true; - work = z_erofs_vle_grab_primary_work(grp); - work->pageofs = pageofs; - - mutex_init(&work->lock); - - if (newgrp) { - int err = erofs_register_workgroup(sb, &grp->obj, 0); - - if (err) { - kmem_cache_free(z_erofs_workgroup_cachep, grp); - return ERR_PTR(-EAGAIN); - } - } - - *owned_head = *grp_ret = grp; - - mutex_lock(&work->lock); - return work; -} - -static inline void __update_workgrp_llen(struct z_erofs_vle_workgroup *grp, - unsigned int llen) -{ - while (1) { - unsigned int orig_llen = grp->llen; - - if (orig_llen >= llen || orig_llen == - cmpxchg(&grp->llen, orig_llen, llen)) - break; - } -} - -#define builder_is_hooked(builder) \ - ((builder)->role >= Z_EROFS_VLE_WORK_PRIMARY_HOOKED) - -#define builder_is_followed(builder) \ - ((builder)->role >= Z_EROFS_VLE_WORK_PRIMARY_FOLLOWED) - -static int z_erofs_vle_work_iter_begin(struct z_erofs_vle_work_builder *builder, - struct super_block *sb, - struct erofs_map_blocks *map, - z_erofs_vle_owned_workgrp_t *owned_head) -{ - const unsigned clusterpages = erofs_clusterpages(EROFS_SB(sb)); - const erofs_blk_t index = erofs_blknr(map->m_pa); - const unsigned pageofs = map->m_la & ~PAGE_MASK; - struct z_erofs_vle_workgroup *grp; - struct z_erofs_vle_work *work; - - DBG_BUGON(builder->work != NULL); - - /* must be Z_EROFS_WORK_TAIL or the next chained work */ - DBG_BUGON(*owned_head == Z_EROFS_VLE_WORKGRP_NIL); - DBG_BUGON(*owned_head == Z_EROFS_VLE_WORKGRP_TAIL_CLOSED); - - DBG_BUGON(erofs_blkoff(map->m_pa)); - -repeat: - work = z_erofs_vle_work_lookup(sb, index, - pageofs, &grp, &builder->role, owned_head, &builder->hosted); - if (work != NULL) { - __update_workgrp_llen(grp, map->m_llen); - goto got_it; - } - - work = z_erofs_vle_work_register(sb, &grp, map, index, pageofs, - &builder->role, owned_head, &builder->hosted); - - if (unlikely(work == ERR_PTR(-EAGAIN))) - goto repeat; - - if (unlikely(IS_ERR(work))) - return PTR_ERR(work); -got_it: - z_erofs_pagevec_ctor_init(&builder->vector, - Z_EROFS_VLE_INLINE_PAGEVECS, work->pagevec, work->vcnt); - - if (builder->role >= Z_EROFS_VLE_WORK_PRIMARY) { - /* enable possibly in-place decompression */ - builder->compressed_pages = grp->compressed_pages; - builder->compressed_deficit = clusterpages; - } else { - builder->compressed_pages = NULL; - builder->compressed_deficit = 0; - } - - builder->grp = grp; - builder->work = work; - return 0; -} - -/* - * keep in mind that no referenced workgroups will be freed - * only after a RCU grace period, so rcu_read_lock() could - * prevent a workgroup from being freed. - */ -static void z_erofs_rcu_callback(struct rcu_head *head) -{ - struct z_erofs_vle_work *work = container_of(head, - struct z_erofs_vle_work, rcu); - struct z_erofs_vle_workgroup *grp = - z_erofs_vle_work_workgroup(work, true); - - kmem_cache_free(z_erofs_workgroup_cachep, grp); -} - -void erofs_workgroup_free_rcu(struct erofs_workgroup *grp) -{ - struct z_erofs_vle_workgroup *const vgrp = container_of(grp, - struct z_erofs_vle_workgroup, obj); - struct z_erofs_vle_work *const work = &vgrp->work; - - call_rcu(&work->rcu, z_erofs_rcu_callback); -} - -static void __z_erofs_vle_work_release(struct z_erofs_vle_workgroup *grp, - struct z_erofs_vle_work *work __maybe_unused) -{ - erofs_workgroup_put(&grp->obj); -} - -void z_erofs_vle_work_release(struct z_erofs_vle_work *work) -{ - struct z_erofs_vle_workgroup *grp = - z_erofs_vle_work_workgroup(work, true); - - __z_erofs_vle_work_release(grp, work); -} - -static inline bool -z_erofs_vle_work_iter_end(struct z_erofs_vle_work_builder *builder) -{ - struct z_erofs_vle_work *work = builder->work; - - if (work == NULL) - return false; - - z_erofs_pagevec_ctor_exit(&builder->vector, false); - mutex_unlock(&work->lock); - - /* - * if all pending pages are added, don't hold work reference - * any longer if the current work isn't hosted by ourselves. - */ - if (!builder->hosted) - __z_erofs_vle_work_release(builder->grp, work); - - builder->work = NULL; - builder->grp = NULL; - return true; -} - -static inline struct page *__stagingpage_alloc(struct list_head *pagepool, - gfp_t gfp) -{ - struct page *page = erofs_allocpage(pagepool, gfp); - - if (unlikely(page == NULL)) - return NULL; - - page->mapping = Z_EROFS_MAPPING_STAGING; - return page; -} - -struct z_erofs_vle_frontend { - struct inode *const inode; - - struct z_erofs_vle_work_builder builder; - struct erofs_map_blocks_iter m_iter; - - z_erofs_vle_owned_workgrp_t owned_head; - - bool initial; -#if (EROFS_FS_ZIP_CACHE_LVL >= 2) - erofs_off_t cachedzone_la; -#endif -}; - -#define VLE_FRONTEND_INIT(__i) { \ - .inode = __i, \ - .m_iter = { \ - { .m_llen = 0, .m_plen = 0 }, \ - .mpage = NULL \ - }, \ - .builder = VLE_WORK_BUILDER_INIT(), \ - .owned_head = Z_EROFS_VLE_WORKGRP_TAIL, \ - .initial = true, } - -static int z_erofs_do_read_page(struct z_erofs_vle_frontend *fe, - struct page *page, - struct list_head *page_pool) -{ - struct super_block *const sb = fe->inode->i_sb; - struct erofs_sb_info *const sbi __maybe_unused = EROFS_SB(sb); - struct erofs_map_blocks_iter *const m = &fe->m_iter; - struct erofs_map_blocks *const map = &m->map; - struct z_erofs_vle_work_builder *const builder = &fe->builder; - const loff_t offset = page_offset(page); - - bool tight = builder_is_hooked(builder); - struct z_erofs_vle_work *work = builder->work; - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - struct address_space *const mngda = sbi->managed_cache->i_mapping; - struct z_erofs_vle_workgroup *grp; - bool noio_outoforder; -#endif - - enum z_erofs_page_type page_type; - unsigned cur, end, spiltted, index; - int err = 0; - - /* register locked file pages as online pages in pack */ - z_erofs_onlinepage_init(page); - - spiltted = 0; - end = PAGE_SIZE; -repeat: - cur = end - 1; - - /* lucky, within the range of the current map_blocks */ - if (offset + cur >= map->m_la && - offset + cur < map->m_la + map->m_llen) { - /* didn't get a valid unzip work previously (very rare) */ - if (!builder->work) - goto restart_now; - goto hitted; - } - - /* go ahead the next map_blocks */ - debugln("%s: [out-of-range] pos %llu", __func__, offset + cur); - - if (z_erofs_vle_work_iter_end(builder)) - fe->initial = false; - - map->m_la = offset + cur; - map->m_llen = 0; - err = erofs_map_blocks_iter(fe->inode, map, &m->mpage, 0); - if (unlikely(err)) - goto err_out; - -restart_now: - if (unlikely(!(map->m_flags & EROFS_MAP_MAPPED))) - goto hitted; - - DBG_BUGON(map->m_plen != 1 << sbi->clusterbits); - DBG_BUGON(erofs_blkoff(map->m_pa)); - - err = z_erofs_vle_work_iter_begin(builder, sb, map, &fe->owned_head); - if (unlikely(err)) - goto err_out; - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - grp = fe->builder.grp; - - /* let's do out-of-order decompression for noio */ - noio_outoforder = grab_managed_cache_pages(mngda, - erofs_blknr(map->m_pa), - grp->compressed_pages, erofs_blknr(map->m_plen), - /* compressed page caching selection strategy */ - fe->initial | (EROFS_FS_ZIP_CACHE_LVL >= 2 ? - map->m_la < fe->cachedzone_la : 0)); - - if (noio_outoforder && builder_is_followed(builder)) - builder->role = Z_EROFS_VLE_WORK_PRIMARY; -#endif - - tight &= builder_is_hooked(builder); - work = builder->work; -hitted: - cur = end - min_t(unsigned, offset + end - map->m_la, end); - if (unlikely(!(map->m_flags & EROFS_MAP_MAPPED))) { - zero_user_segment(page, cur, end); - goto next_part; - } - - /* let's derive page type */ - page_type = cur ? Z_EROFS_VLE_PAGE_TYPE_HEAD : - (!spiltted ? Z_EROFS_PAGE_TYPE_EXCLUSIVE : - (tight ? Z_EROFS_PAGE_TYPE_EXCLUSIVE : - Z_EROFS_VLE_PAGE_TYPE_TAIL_SHARED)); - - if (cur) - tight &= builder_is_followed(builder); - -retry: - err = z_erofs_vle_work_add_page(builder, page, page_type); - /* should allocate an additional staging page for pagevec */ - if (err == -EAGAIN) { - struct page *const newpage = - __stagingpage_alloc(page_pool, GFP_NOFS); - - err = z_erofs_vle_work_add_page(builder, - newpage, Z_EROFS_PAGE_TYPE_EXCLUSIVE); - if (likely(!err)) - goto retry; - } - - if (unlikely(err)) - goto err_out; - - index = page->index - map->m_la / PAGE_SIZE; - - /* FIXME! avoid the last relundant fixup & endio */ - z_erofs_onlinepage_fixup(page, index, true); - - /* bump up the number of spiltted parts of a page */ - ++spiltted; - /* also update nr_pages */ - work->nr_pages = max_t(pgoff_t, work->nr_pages, index + 1); -next_part: - /* can be used for verification */ - map->m_llen = offset + cur - map->m_la; - - end = cur; - if (end > 0) - goto repeat; - -out: - /* FIXME! avoid the last relundant fixup & endio */ - z_erofs_onlinepage_endio(page); - - debugln("%s, finish page: %pK spiltted: %u map->m_llen %llu", - __func__, page, spiltted, map->m_llen); - return err; - - /* if some error occurred while processing this page */ -err_out: - SetPageError(page); - goto out; -} - -static void z_erofs_vle_unzip_kickoff(void *ptr, int bios) -{ - tagptr1_t t = tagptr_init(tagptr1_t, ptr); - struct z_erofs_vle_unzip_io *io = tagptr_unfold_ptr(t); - bool background = tagptr_unfold_tags(t); - - if (!background) { - unsigned long flags; - - spin_lock_irqsave(&io->u.wait.lock, flags); - if (!atomic_add_return(bios, &io->pending_bios)) - wake_up_locked(&io->u.wait); - spin_unlock_irqrestore(&io->u.wait.lock, flags); - return; - } - - if (!atomic_add_return(bios, &io->pending_bios)) - queue_work(z_erofs_workqueue, &io->u.work); -} - -static inline void z_erofs_vle_read_endio(struct bio *bio) -{ - const blk_status_t err = bio->bi_status; - unsigned i; - struct bio_vec *bvec; -#ifdef EROFS_FS_HAS_MANAGED_CACHE - struct address_space *mngda = NULL; -#endif - - bio_for_each_segment_all(bvec, bio, i) { - struct page *page = bvec->bv_page; - bool cachemngd = false; - - DBG_BUGON(PageUptodate(page)); - DBG_BUGON(!page->mapping); - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - if (unlikely(mngda == NULL && !z_erofs_is_stagingpage(page))) { - struct inode *const inode = page->mapping->host; - struct super_block *const sb = inode->i_sb; - - mngda = EROFS_SB(sb)->managed_cache->i_mapping; - } - - /* - * If mngda has not gotten, it equals NULL, - * however, page->mapping never be NULL if working properly. - */ - cachemngd = (page->mapping == mngda); -#endif - - if (unlikely(err)) - SetPageError(page); - else if (cachemngd) - SetPageUptodate(page); - - if (cachemngd) - unlock_page(page); - } - - z_erofs_vle_unzip_kickoff(bio->bi_private, -1); - bio_put(bio); -} - -static struct page *z_pagemap_global[Z_EROFS_VLE_VMAP_GLOBAL_PAGES]; -static DEFINE_MUTEX(z_pagemap_global_lock); - -static int z_erofs_vle_unzip(struct super_block *sb, - struct z_erofs_vle_workgroup *grp, - struct list_head *page_pool) -{ - struct erofs_sb_info *const sbi = EROFS_SB(sb); -#ifdef EROFS_FS_HAS_MANAGED_CACHE - struct address_space *const mngda = sbi->managed_cache->i_mapping; -#endif - const unsigned clusterpages = erofs_clusterpages(sbi); - - struct z_erofs_pagevec_ctor ctor; - unsigned int nr_pages; - unsigned int sparsemem_pages = 0; - struct page *pages_onstack[Z_EROFS_VLE_VMAP_ONSTACK_PAGES]; - struct page **pages, **compressed_pages, *page; - unsigned i, llen; - - enum z_erofs_page_type page_type; - bool overlapped; - struct z_erofs_vle_work *work; - void *vout; - int err; - - might_sleep(); - work = z_erofs_vle_grab_primary_work(grp); - DBG_BUGON(!READ_ONCE(work->nr_pages)); - - mutex_lock(&work->lock); - nr_pages = work->nr_pages; - - if (likely(nr_pages <= Z_EROFS_VLE_VMAP_ONSTACK_PAGES)) - pages = pages_onstack; - else if (nr_pages <= Z_EROFS_VLE_VMAP_GLOBAL_PAGES && - mutex_trylock(&z_pagemap_global_lock)) - pages = z_pagemap_global; - else { -repeat: - pages = kvmalloc_array(nr_pages, - sizeof(struct page *), GFP_KERNEL); - - /* fallback to global pagemap for the lowmem scenario */ - if (unlikely(pages == NULL)) { - if (nr_pages > Z_EROFS_VLE_VMAP_GLOBAL_PAGES) - goto repeat; - else { - mutex_lock(&z_pagemap_global_lock); - pages = z_pagemap_global; - } - } - } - - for (i = 0; i < nr_pages; ++i) - pages[i] = NULL; - - err = 0; - z_erofs_pagevec_ctor_init(&ctor, - Z_EROFS_VLE_INLINE_PAGEVECS, work->pagevec, 0); - - for (i = 0; i < work->vcnt; ++i) { - unsigned pagenr; - - page = z_erofs_pagevec_ctor_dequeue(&ctor, &page_type); - - /* all pages in pagevec ought to be valid */ - DBG_BUGON(page == NULL); - DBG_BUGON(page->mapping == NULL); - - if (z_erofs_gather_if_stagingpage(page_pool, page)) - continue; - - if (page_type == Z_EROFS_VLE_PAGE_TYPE_HEAD) - pagenr = 0; - else - pagenr = z_erofs_onlinepage_index(page); - - DBG_BUGON(pagenr >= nr_pages); - - /* - * currently EROFS doesn't support multiref(dedup), - * so here erroring out one multiref page. - */ - if (pages[pagenr]) { - DBG_BUGON(1); - SetPageError(pages[pagenr]); - z_erofs_onlinepage_endio(pages[pagenr]); - err = -EIO; - } - pages[pagenr] = page; - } - sparsemem_pages = i; - - z_erofs_pagevec_ctor_exit(&ctor, true); - - overlapped = false; - compressed_pages = grp->compressed_pages; - - for (i = 0; i < clusterpages; ++i) { - unsigned pagenr; - - page = compressed_pages[i]; - - /* all compressed pages ought to be valid */ - DBG_BUGON(page == NULL); - DBG_BUGON(page->mapping == NULL); - - if (!z_erofs_is_stagingpage(page)) { -#ifdef EROFS_FS_HAS_MANAGED_CACHE - if (page->mapping == mngda) { - if (unlikely(!PageUptodate(page))) - err = -EIO; - continue; - } -#endif - - /* - * only if non-head page can be selected - * for inplace decompression - */ - pagenr = z_erofs_onlinepage_index(page); - - DBG_BUGON(pagenr >= nr_pages); - if (pages[pagenr]) { - DBG_BUGON(1); - SetPageError(pages[pagenr]); - z_erofs_onlinepage_endio(pages[pagenr]); - err = -EIO; - } - ++sparsemem_pages; - pages[pagenr] = page; - - overlapped = true; - } - - /* PG_error needs checking for inplaced and staging pages */ - if (unlikely(PageError(page))) { - DBG_BUGON(PageUptodate(page)); - err = -EIO; - } - } - - if (unlikely(err)) - goto out; - - llen = (nr_pages << PAGE_SHIFT) - work->pageofs; - - if (z_erofs_vle_workgrp_fmt(grp) == Z_EROFS_VLE_WORKGRP_FMT_PLAIN) { - err = z_erofs_vle_plain_copy(compressed_pages, clusterpages, - pages, nr_pages, work->pageofs); - goto out; - } - - if (llen > grp->llen) - llen = grp->llen; - - err = z_erofs_vle_unzip_fast_percpu(compressed_pages, clusterpages, - pages, llen, work->pageofs); - if (err != -ENOTSUPP) - goto out; - - if (sparsemem_pages >= nr_pages) - goto skip_allocpage; - - for (i = 0; i < nr_pages; ++i) { - if (pages[i] != NULL) - continue; - - pages[i] = __stagingpage_alloc(page_pool, GFP_NOFS); - } - -skip_allocpage: - vout = erofs_vmap(pages, nr_pages); - if (!vout) { - err = -ENOMEM; - goto out; - } - - err = z_erofs_vle_unzip_vmap(compressed_pages, - clusterpages, vout, llen, work->pageofs, overlapped); - - erofs_vunmap(vout, nr_pages); - -out: - /* must handle all compressed pages before endding pages */ - for (i = 0; i < clusterpages; ++i) { - page = compressed_pages[i]; - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - if (page->mapping == mngda) - continue; -#endif - /* recycle all individual staging pages */ - (void)z_erofs_gather_if_stagingpage(page_pool, page); - - WRITE_ONCE(compressed_pages[i], NULL); - } - - for (i = 0; i < nr_pages; ++i) { - page = pages[i]; - if (!page) - continue; - - DBG_BUGON(page->mapping == NULL); - - /* recycle all individual staging pages */ - if (z_erofs_gather_if_stagingpage(page_pool, page)) - continue; - - if (unlikely(err < 0)) - SetPageError(page); - - z_erofs_onlinepage_endio(page); - } - - if (pages == z_pagemap_global) - mutex_unlock(&z_pagemap_global_lock); - else if (unlikely(pages != pages_onstack)) - kvfree(pages); - - work->nr_pages = 0; - work->vcnt = 0; - - /* all work locks MUST be taken before the following line */ - - WRITE_ONCE(grp->next, Z_EROFS_VLE_WORKGRP_NIL); - - /* all work locks SHOULD be released right now */ - mutex_unlock(&work->lock); - - z_erofs_vle_work_release(work); - return err; -} - -static void z_erofs_vle_unzip_all(struct super_block *sb, - struct z_erofs_vle_unzip_io *io, - struct list_head *page_pool) -{ - z_erofs_vle_owned_workgrp_t owned = io->head; - - while (owned != Z_EROFS_VLE_WORKGRP_TAIL_CLOSED) { - struct z_erofs_vle_workgroup *grp; - - /* no possible that 'owned' equals Z_EROFS_WORK_TPTR_TAIL */ - DBG_BUGON(owned == Z_EROFS_VLE_WORKGRP_TAIL); - - /* no possible that 'owned' equals NULL */ - DBG_BUGON(owned == Z_EROFS_VLE_WORKGRP_NIL); - - grp = owned; - owned = READ_ONCE(grp->next); - - z_erofs_vle_unzip(sb, grp, page_pool); - } -} - -static void z_erofs_vle_unzip_wq(struct work_struct *work) -{ - struct z_erofs_vle_unzip_io_sb *iosb = container_of(work, - struct z_erofs_vle_unzip_io_sb, io.u.work); - LIST_HEAD(page_pool); - - DBG_BUGON(iosb->io.head == Z_EROFS_VLE_WORKGRP_TAIL_CLOSED); - z_erofs_vle_unzip_all(iosb->sb, &iosb->io, &page_pool); - - put_pages_list(&page_pool); - kvfree(iosb); -} - -static inline struct z_erofs_vle_unzip_io * -prepare_io_handler(struct super_block *sb, - struct z_erofs_vle_unzip_io *io, - bool background) -{ - struct z_erofs_vle_unzip_io_sb *iosb; - - if (!background) { - /* waitqueue available for foreground io */ - BUG_ON(io == NULL); - - init_waitqueue_head(&io->u.wait); - atomic_set(&io->pending_bios, 0); - goto out; - } - - if (io != NULL) - BUG(); - else { - /* allocate extra io descriptor for background io */ - iosb = kvzalloc(sizeof(struct z_erofs_vle_unzip_io_sb), - GFP_KERNEL | __GFP_NOFAIL); - BUG_ON(iosb == NULL); - - io = &iosb->io; - } - - iosb->sb = sb; - INIT_WORK(&io->u.work, z_erofs_vle_unzip_wq); -out: - io->head = Z_EROFS_VLE_WORKGRP_TAIL_CLOSED; - return io; -} - -#ifdef EROFS_FS_HAS_MANAGED_CACHE -/* true - unlocked (noio), false - locked (need submit io) */ -static inline bool recover_managed_page(struct z_erofs_vle_workgroup *grp, - struct page *page) -{ - wait_on_page_locked(page); - if (PagePrivate(page) && PageUptodate(page)) - return true; - - lock_page(page); - ClearPageError(page); - - if (unlikely(!PagePrivate(page))) { - set_page_private(page, (unsigned long)grp); - SetPagePrivate(page); - } - if (unlikely(PageUptodate(page))) { - unlock_page(page); - return true; - } - return false; -} - -#define __FSIO_1 1 -#else -#define __FSIO_1 0 -#endif - -static bool z_erofs_vle_submit_all(struct super_block *sb, - z_erofs_vle_owned_workgrp_t owned_head, - struct list_head *pagepool, - struct z_erofs_vle_unzip_io *fg_io, - bool force_fg) -{ - struct erofs_sb_info *const sbi = EROFS_SB(sb); - const unsigned clusterpages = erofs_clusterpages(sbi); - const gfp_t gfp = GFP_NOFS; -#ifdef EROFS_FS_HAS_MANAGED_CACHE - struct address_space *const mngda = sbi->managed_cache->i_mapping; - struct z_erofs_vle_workgroup *lstgrp_noio = NULL, *lstgrp_io = NULL; -#endif - struct z_erofs_vle_unzip_io *ios[1 + __FSIO_1]; - struct bio *bio; - tagptr1_t bi_private; - /* since bio will be NULL, no need to initialize last_index */ - pgoff_t uninitialized_var(last_index); - bool force_submit = false; - unsigned nr_bios; - - if (unlikely(owned_head == Z_EROFS_VLE_WORKGRP_TAIL)) - return false; - - /* - * force_fg == 1, (io, fg_io[0]) no io, (io, fg_io[1]) need submit io - * force_fg == 0, (io, fg_io[0]) no io; (io[1], bg_io) need submit io - */ -#ifdef EROFS_FS_HAS_MANAGED_CACHE - ios[0] = prepare_io_handler(sb, fg_io + 0, false); -#endif - - if (force_fg) { - ios[__FSIO_1] = prepare_io_handler(sb, fg_io + __FSIO_1, false); - bi_private = tagptr_fold(tagptr1_t, ios[__FSIO_1], 0); - } else { - ios[__FSIO_1] = prepare_io_handler(sb, NULL, true); - bi_private = tagptr_fold(tagptr1_t, ios[__FSIO_1], 1); - } - - nr_bios = 0; - force_submit = false; - bio = NULL; - - /* by default, all need io submission */ - ios[__FSIO_1]->head = owned_head; - - do { - struct z_erofs_vle_workgroup *grp; - struct page **compressed_pages, *oldpage, *page; - pgoff_t first_index; - unsigned i = 0; -#ifdef EROFS_FS_HAS_MANAGED_CACHE - unsigned int noio = 0; - bool cachemngd; -#endif - int err; - - /* no possible 'owned_head' equals the following */ - DBG_BUGON(owned_head == Z_EROFS_VLE_WORKGRP_TAIL_CLOSED); - DBG_BUGON(owned_head == Z_EROFS_VLE_WORKGRP_NIL); - - grp = owned_head; - - /* close the main owned chain at first */ - owned_head = cmpxchg(&grp->next, Z_EROFS_VLE_WORKGRP_TAIL, - Z_EROFS_VLE_WORKGRP_TAIL_CLOSED); - - first_index = grp->obj.index; - compressed_pages = grp->compressed_pages; - - force_submit |= (first_index != last_index + 1); -repeat: - /* fulfill all compressed pages */ - oldpage = page = READ_ONCE(compressed_pages[i]); - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - cachemngd = false; - - if (page == EROFS_UNALLOCATED_CACHED_PAGE) { - cachemngd = true; - goto do_allocpage; - } else if (page != NULL) { - if (page->mapping != mngda) - BUG_ON(PageUptodate(page)); - else if (recover_managed_page(grp, page)) { - /* page is uptodate, skip io submission */ - force_submit = true; - ++noio; - goto skippage; - } - } else { -do_allocpage: -#else - if (page != NULL) - BUG_ON(PageUptodate(page)); - else { -#endif - page = __stagingpage_alloc(pagepool, gfp); - - if (oldpage != cmpxchg(compressed_pages + i, - oldpage, page)) { - list_add(&page->lru, pagepool); - goto repeat; -#ifdef EROFS_FS_HAS_MANAGED_CACHE - } else if (cachemngd && !add_to_page_cache_lru(page, - mngda, first_index + i, gfp)) { - set_page_private(page, (unsigned long)grp); - SetPagePrivate(page); -#endif - } - } - - if (bio != NULL && force_submit) { -submit_bio_retry: - __submit_bio(bio, REQ_OP_READ, 0); - bio = NULL; - } - - if (bio == NULL) { - bio = prepare_bio(sb, first_index + i, - BIO_MAX_PAGES, z_erofs_vle_read_endio); - bio->bi_private = tagptr_cast_ptr(bi_private); - - ++nr_bios; - } - - err = bio_add_page(bio, page, PAGE_SIZE, 0); - if (err < PAGE_SIZE) - goto submit_bio_retry; - - force_submit = false; - last_index = first_index + i; -#ifdef EROFS_FS_HAS_MANAGED_CACHE -skippage: -#endif - if (++i < clusterpages) - goto repeat; - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - if (noio < clusterpages) { - lstgrp_io = grp; - } else { - z_erofs_vle_owned_workgrp_t iogrp_next = - owned_head == Z_EROFS_VLE_WORKGRP_TAIL ? - Z_EROFS_VLE_WORKGRP_TAIL_CLOSED : - owned_head; - - if (lstgrp_io == NULL) - ios[1]->head = iogrp_next; - else - WRITE_ONCE(lstgrp_io->next, iogrp_next); - - if (lstgrp_noio == NULL) - ios[0]->head = grp; - else - WRITE_ONCE(lstgrp_noio->next, grp); - - lstgrp_noio = grp; - } -#endif - } while (owned_head != Z_EROFS_VLE_WORKGRP_TAIL); - - if (bio != NULL) - __submit_bio(bio, REQ_OP_READ, 0); - -#ifndef EROFS_FS_HAS_MANAGED_CACHE - BUG_ON(!nr_bios); -#else - if (lstgrp_noio != NULL) - WRITE_ONCE(lstgrp_noio->next, Z_EROFS_VLE_WORKGRP_TAIL_CLOSED); - - if (!force_fg && !nr_bios) { - kvfree(container_of(ios[1], - struct z_erofs_vle_unzip_io_sb, io)); - return true; - } -#endif - - z_erofs_vle_unzip_kickoff(tagptr_cast_ptr(bi_private), nr_bios); - return true; -} - -static void z_erofs_submit_and_unzip(struct z_erofs_vle_frontend *f, - struct list_head *pagepool, - bool force_fg) -{ - struct super_block *sb = f->inode->i_sb; - struct z_erofs_vle_unzip_io io[1 + __FSIO_1]; - - if (!z_erofs_vle_submit_all(sb, f->owned_head, pagepool, io, force_fg)) - return; - -#ifdef EROFS_FS_HAS_MANAGED_CACHE - z_erofs_vle_unzip_all(sb, &io[0], pagepool); -#endif - if (!force_fg) - return; - - /* wait until all bios are completed */ - wait_event(io[__FSIO_1].u.wait, - !atomic_read(&io[__FSIO_1].pending_bios)); - - /* let's synchronous decompression */ - z_erofs_vle_unzip_all(sb, &io[__FSIO_1], pagepool); -} - -static int z_erofs_vle_normalaccess_readpage(struct file *file, - struct page *page) -{ - struct inode *const inode = page->mapping->host; - struct z_erofs_vle_frontend f = VLE_FRONTEND_INIT(inode); - int err; - LIST_HEAD(pagepool); - -#if (EROFS_FS_ZIP_CACHE_LVL >= 2) - f.cachedzone_la = page->index << PAGE_SHIFT; -#endif - err = z_erofs_do_read_page(&f, page, &pagepool); - (void)z_erofs_vle_work_iter_end(&f.builder); - - /* if some compressed cluster ready, need submit them anyway */ - z_erofs_submit_and_unzip(&f, &pagepool, true); - - if (err) - errln("%s, failed to read, err [%d]", __func__, err); - - if (f.m_iter.mpage != NULL) - put_page(f.m_iter.mpage); - - /* clean up the remaining free pages */ - put_pages_list(&pagepool); - return err; -} - -static inline int __z_erofs_vle_normalaccess_readpages( - struct file *filp, - struct address_space *mapping, - struct list_head *pages, unsigned nr_pages, bool sync) -{ - struct inode *const inode = mapping->host; - - struct z_erofs_vle_frontend f = VLE_FRONTEND_INIT(inode); - gfp_t gfp = mapping_gfp_constraint(mapping, GFP_KERNEL); - struct page *head = NULL; - LIST_HEAD(pagepool); - -#if (EROFS_FS_ZIP_CACHE_LVL >= 2) - f.cachedzone_la = lru_to_page(pages)->index << PAGE_SHIFT; -#endif - for (; nr_pages; --nr_pages) { - struct page *page = lru_to_page(pages); - - prefetchw(&page->flags); - list_del(&page->lru); - - if (add_to_page_cache_lru(page, mapping, page->index, gfp)) { - list_add(&page->lru, &pagepool); - continue; - } - - set_page_private(page, (unsigned long)head); - head = page; - } - - while (head != NULL) { - struct page *page = head; - int err; - - /* traversal in reverse order */ - head = (void *)page_private(page); - - err = z_erofs_do_read_page(&f, page, &pagepool); - if (err) { - struct erofs_vnode *vi = EROFS_V(inode); - - errln("%s, readahead error at page %lu of nid %llu", - __func__, page->index, vi->nid); - } - - put_page(page); - } - - (void)z_erofs_vle_work_iter_end(&f.builder); - - z_erofs_submit_and_unzip(&f, &pagepool, sync); - - if (f.m_iter.mpage != NULL) - put_page(f.m_iter.mpage); - - /* clean up the remaining free pages */ - put_pages_list(&pagepool); - return 0; -} - -static int z_erofs_vle_normalaccess_readpages( - struct file *filp, - struct address_space *mapping, - struct list_head *pages, unsigned nr_pages) -{ - return __z_erofs_vle_normalaccess_readpages(filp, - mapping, pages, nr_pages, - nr_pages < 4 /* sync */); -} - -const struct address_space_operations z_erofs_vle_normalaccess_aops = { - .readpage = z_erofs_vle_normalaccess_readpage, - .readpages = z_erofs_vle_normalaccess_readpages, -}; - -#define __vle_cluster_advise(x, bit, bits) \ - ((le16_to_cpu(x) >> (bit)) & ((1 << (bits)) - 1)) - -#define __vle_cluster_type(advise) __vle_cluster_advise(advise, \ - Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT, Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) - -enum { - Z_EROFS_VLE_CLUSTER_TYPE_PLAIN, - Z_EROFS_VLE_CLUSTER_TYPE_HEAD, - Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD, - Z_EROFS_VLE_CLUSTER_TYPE_RESERVED, - Z_EROFS_VLE_CLUSTER_TYPE_MAX -}; - -#define vle_cluster_type(di) \ - __vle_cluster_type((di)->di_advise) - -static inline unsigned -vle_compressed_index_clusterofs(unsigned clustersize, - struct z_erofs_vle_decompressed_index *di) -{ - debugln("%s, vle=%pK, advise=%x (type %u), clusterofs=%x blkaddr=%x", - __func__, di, di->di_advise, vle_cluster_type(di), - di->di_clusterofs, di->di_u.blkaddr); - - switch (vle_cluster_type(di)) { - case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: - break; - case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: - case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: - return di->di_clusterofs; - default: - BUG_ON(1); - } - return clustersize; -} - -static inline erofs_blk_t -vle_extent_blkaddr(struct inode *inode, pgoff_t index) -{ - struct erofs_sb_info *sbi = EROFS_I_SB(inode); - struct erofs_vnode *vi = EROFS_V(inode); - - unsigned ofs = Z_EROFS_VLE_EXTENT_ALIGN(vi->inode_isize + - vi->xattr_isize) + sizeof(struct erofs_extent_header) + - index * sizeof(struct z_erofs_vle_decompressed_index); - - return erofs_blknr(iloc(sbi, vi->nid) + ofs); -} - -static inline unsigned int -vle_extent_blkoff(struct inode *inode, pgoff_t index) -{ - struct erofs_sb_info *sbi = EROFS_I_SB(inode); - struct erofs_vnode *vi = EROFS_V(inode); - - unsigned ofs = Z_EROFS_VLE_EXTENT_ALIGN(vi->inode_isize + - vi->xattr_isize) + sizeof(struct erofs_extent_header) + - index * sizeof(struct z_erofs_vle_decompressed_index); - - return erofs_blkoff(iloc(sbi, vi->nid) + ofs); -} - -/* - * Variable-sized Logical Extent (Fixed Physical Cluster) Compression Mode - * --- - * VLE compression mode attempts to compress a number of logical data into - * a physical cluster with a fixed size. - * VLE compression mode uses "struct z_erofs_vle_decompressed_index". - */ -static erofs_off_t vle_get_logical_extent_head( - struct inode *inode, - struct page **page_iter, - void **kaddr_iter, - unsigned lcn, /* logical cluster number */ - erofs_blk_t *pcn, - unsigned *flags) -{ - /* for extent meta */ - struct page *page = *page_iter; - erofs_blk_t blkaddr = vle_extent_blkaddr(inode, lcn); - struct z_erofs_vle_decompressed_index *di; - unsigned long long ofs; - const unsigned int clusterbits = EROFS_SB(inode->i_sb)->clusterbits; - const unsigned int clustersize = 1 << clusterbits; - unsigned int delta0; - - if (page->index != blkaddr) { - kunmap_atomic(*kaddr_iter); - unlock_page(page); - put_page(page); - - *page_iter = page = erofs_get_meta_page(inode->i_sb, - blkaddr, false); - *kaddr_iter = kmap_atomic(page); - } - - di = *kaddr_iter + vle_extent_blkoff(inode, lcn); - switch (vle_cluster_type(di)) { - case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: - delta0 = le16_to_cpu(di->di_u.delta[0]); - DBG_BUGON(!delta0); - DBG_BUGON(lcn < delta0); - - ofs = vle_get_logical_extent_head(inode, - page_iter, kaddr_iter, - lcn - delta0, pcn, flags); - break; - case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: - *flags ^= EROFS_MAP_ZIPPED; - case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: - /* clustersize should be a power of two */ - ofs = ((unsigned long long)lcn << clusterbits) + - (le16_to_cpu(di->di_clusterofs) & (clustersize - 1)); - *pcn = le32_to_cpu(di->di_u.blkaddr); - break; - default: - BUG_ON(1); - } - return ofs; -} - -int z_erofs_map_blocks_iter(struct inode *inode, - struct erofs_map_blocks *map, - struct page **mpage_ret, int flags) -{ - /* logicial extent (start, end) offset */ - unsigned long long ofs, end; - struct z_erofs_vle_decompressed_index *di; - erofs_blk_t e_blkaddr, pcn; - unsigned lcn, logical_cluster_ofs, cluster_type; - u32 ofs_rem; - struct page *mpage = *mpage_ret; - void *kaddr; - bool initial; - const unsigned int clusterbits = EROFS_SB(inode->i_sb)->clusterbits; - const unsigned int clustersize = 1 << clusterbits; - int err = 0; - - /* if both m_(l,p)len are 0, regularize l_lblk, l_lofs, etc... */ - initial = !map->m_llen; - - /* when trying to read beyond EOF, leave it unmapped */ - if (unlikely(map->m_la >= inode->i_size)) { - BUG_ON(!initial); - map->m_llen = map->m_la + 1 - inode->i_size; - map->m_la = inode->i_size - 1; - map->m_flags = 0; - goto out; - } - - debugln("%s, m_la %llu m_llen %llu --- start", __func__, - map->m_la, map->m_llen); - - ofs = map->m_la + map->m_llen; - - /* clustersize should be power of two */ - lcn = ofs >> clusterbits; - ofs_rem = ofs & (clustersize - 1); - - e_blkaddr = vle_extent_blkaddr(inode, lcn); - - if (mpage == NULL || mpage->index != e_blkaddr) { - if (mpage != NULL) - put_page(mpage); - - mpage = erofs_get_meta_page(inode->i_sb, e_blkaddr, false); - *mpage_ret = mpage; - } else { - lock_page(mpage); - DBG_BUGON(!PageUptodate(mpage)); - } - - kaddr = kmap_atomic(mpage); - di = kaddr + vle_extent_blkoff(inode, lcn); - - debugln("%s, lcn %u e_blkaddr %u e_blkoff %u", __func__, lcn, - e_blkaddr, vle_extent_blkoff(inode, lcn)); - - logical_cluster_ofs = vle_compressed_index_clusterofs(clustersize, di); - if (!initial) { - /* [walking mode] 'map' has been already initialized */ - map->m_llen += logical_cluster_ofs; - goto unmap_out; - } - - /* by default, compressed */ - map->m_flags |= EROFS_MAP_ZIPPED; - - end = (u64)(lcn + 1) * clustersize; - - cluster_type = vle_cluster_type(di); - - switch (cluster_type) { - case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: - if (ofs_rem >= logical_cluster_ofs) - map->m_flags ^= EROFS_MAP_ZIPPED; - /* fallthrough */ - case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: - if (ofs_rem == logical_cluster_ofs) { - pcn = le32_to_cpu(di->di_u.blkaddr); - goto exact_hitted; - } - - if (ofs_rem > logical_cluster_ofs) { - ofs = lcn * clustersize | logical_cluster_ofs; - pcn = le32_to_cpu(di->di_u.blkaddr); - break; - } - - /* logical cluster number should be >= 1 */ - if (unlikely(!lcn)) { - errln("invalid logical cluster 0 at nid %llu", - EROFS_V(inode)->nid); - err = -EIO; - goto unmap_out; - } - end = (lcn-- * clustersize) | logical_cluster_ofs; - /* fallthrough */ - case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: - /* get the correspoinding first chunk */ - ofs = vle_get_logical_extent_head(inode, mpage_ret, - &kaddr, lcn, &pcn, &map->m_flags); - mpage = *mpage_ret; - break; - default: - errln("unknown cluster type %u at offset %llu of nid %llu", - cluster_type, ofs, EROFS_V(inode)->nid); - err = -EIO; - goto unmap_out; - } - - map->m_la = ofs; -exact_hitted: - map->m_llen = end - ofs; - map->m_plen = clustersize; - map->m_pa = blknr_to_addr(pcn); - map->m_flags |= EROFS_MAP_MAPPED; -unmap_out: - kunmap_atomic(kaddr); - unlock_page(mpage); -out: - debugln("%s, m_la %llu m_pa %llu m_llen %llu m_plen %llu m_flags 0%o", - __func__, map->m_la, map->m_pa, - map->m_llen, map->m_plen, map->m_flags); - - /* aggressively BUG_ON iff CONFIG_EROFS_FS_DEBUG is on */ - DBG_BUGON(err < 0); - return err; -} - diff --git a/drivers/staging/erofs/unzip_vle_lz4.c b/drivers/staging/erofs/unzip_vle_lz4.c deleted file mode 100644 index 3a7428317f0a..000000000000 --- a/drivers/staging/erofs/unzip_vle_lz4.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/drivers/staging/erofs/unzip_vle_lz4.c - * - * Copyright (C) 2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. - */ -#include "unzip_vle.h" - -#if Z_EROFS_CLUSTER_MAX_PAGES > Z_EROFS_VLE_INLINE_PAGEVECS -#define EROFS_PERCPU_NR_PAGES Z_EROFS_CLUSTER_MAX_PAGES -#else -#define EROFS_PERCPU_NR_PAGES Z_EROFS_VLE_INLINE_PAGEVECS -#endif - -static struct { - char data[PAGE_SIZE * EROFS_PERCPU_NR_PAGES]; -} erofs_pcpubuf[NR_CPUS]; - -int z_erofs_vle_plain_copy(struct page **compressed_pages, - unsigned clusterpages, - struct page **pages, - unsigned nr_pages, - unsigned short pageofs) -{ - unsigned i, j; - void *src = NULL; - const unsigned righthalf = PAGE_SIZE - pageofs; - char *percpu_data; - bool mirrored[Z_EROFS_CLUSTER_MAX_PAGES] = { 0 }; - - preempt_disable(); - percpu_data = erofs_pcpubuf[smp_processor_id()].data; - - j = 0; - for (i = 0; i < nr_pages; j = i++) { - struct page *page = pages[i]; - void *dst; - - if (page == NULL) { - if (src != NULL) { - if (!mirrored[j]) - kunmap_atomic(src); - src = NULL; - } - continue; - } - - dst = kmap_atomic(page); - - for (; j < clusterpages; ++j) { - if (compressed_pages[j] != page) - continue; - - DBG_BUGON(mirrored[j]); - memcpy(percpu_data + j * PAGE_SIZE, dst, PAGE_SIZE); - mirrored[j] = true; - break; - } - - if (i) { - if (src == NULL) - src = mirrored[i-1] ? - percpu_data + (i-1) * PAGE_SIZE : - kmap_atomic(compressed_pages[i-1]); - - memcpy(dst, src + righthalf, pageofs); - - if (!mirrored[i-1]) - kunmap_atomic(src); - - if (unlikely(i >= clusterpages)) { - kunmap_atomic(dst); - break; - } - } - - if (!righthalf) - src = NULL; - else { - src = mirrored[i] ? percpu_data + i * PAGE_SIZE : - kmap_atomic(compressed_pages[i]); - - memcpy(dst + pageofs, src, righthalf); - } - - kunmap_atomic(dst); - } - - if (src != NULL && !mirrored[j]) - kunmap_atomic(src); - - preempt_enable(); - return 0; -} - -extern int z_erofs_unzip_lz4(void *in, void *out, size_t inlen, size_t outlen); - -int z_erofs_vle_unzip_fast_percpu(struct page **compressed_pages, - unsigned clusterpages, - struct page **pages, - unsigned outlen, - unsigned short pageofs) -{ - void *vin, *vout; - unsigned nr_pages, i, j; - int ret; - - if (outlen + pageofs > EROFS_PERCPU_NR_PAGES * PAGE_SIZE) - return -ENOTSUPP; - - nr_pages = DIV_ROUND_UP(outlen + pageofs, PAGE_SIZE); - - if (clusterpages == 1) { - vin = kmap_atomic(compressed_pages[0]); - } else { - vin = erofs_vmap(compressed_pages, clusterpages); - if (!vin) - return -ENOMEM; - } - - preempt_disable(); - vout = erofs_pcpubuf[smp_processor_id()].data; - - ret = z_erofs_unzip_lz4(vin, vout + pageofs, - clusterpages * PAGE_SIZE, outlen); - - if (ret < 0) - goto out; - ret = 0; - - for (i = 0; i < nr_pages; ++i) { - j = min((unsigned)PAGE_SIZE - pageofs, outlen); - - if (pages[i] != NULL) { - if (clusterpages == 1 && - pages[i] == compressed_pages[0]) { - memcpy(vin + pageofs, vout + pageofs, j); - } else { - void *dst = kmap_atomic(pages[i]); - - memcpy(dst + pageofs, vout + pageofs, j); - kunmap_atomic(dst); - } - } - vout += PAGE_SIZE; - outlen -= j; - pageofs = 0; - } - -out: - preempt_enable(); - - if (clusterpages == 1) - kunmap_atomic(vin); - else - erofs_vunmap(vin, clusterpages); - - return ret; -} - -int z_erofs_vle_unzip_vmap(struct page **compressed_pages, - unsigned clusterpages, - void *vout, - unsigned llen, - unsigned short pageofs, - bool overlapped) -{ - void *vin; - unsigned i; - int ret; - - if (overlapped) { - preempt_disable(); - vin = erofs_pcpubuf[smp_processor_id()].data; - - for (i = 0; i < clusterpages; ++i) { - void *t = kmap_atomic(compressed_pages[i]); - - memcpy(vin + PAGE_SIZE *i, t, PAGE_SIZE); - kunmap_atomic(t); - } - } else if (clusterpages == 1) - vin = kmap_atomic(compressed_pages[0]); - else { - vin = erofs_vmap(compressed_pages, clusterpages); - } - - ret = z_erofs_unzip_lz4(vin, vout + pageofs, - clusterpages * PAGE_SIZE, llen); - if (ret > 0) - ret = 0; - - if (!overlapped) { - if (clusterpages == 1) - kunmap_atomic(vin); - else { - erofs_vunmap(vin, clusterpages); - } - } else - preempt_enable(); - - return ret; -} - diff --git a/drivers/staging/erofs/utils.c b/drivers/staging/erofs/utils.c index 4de9c39535eb..aab4a607f028 100644 --- a/drivers/staging/erofs/utils.c +++ b/drivers/staging/erofs/utils.c @@ -1,16 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * linux/drivers/staging/erofs/utils.c - * * Copyright (C) 2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ - #include "internal.h" #include @@ -20,43 +12,67 @@ struct page *erofs_allocpage(struct list_head *pool, gfp_t gfp) if (!list_empty(pool)) { page = lru_to_page(pool); + DBG_BUGON(page_ref_count(page) != 1); list_del(&page->lru); } else { - page = alloc_pages(gfp | __GFP_NOFAIL, 0); + page = alloc_page(gfp); } return page; } +#if (EROFS_PCPUBUF_NR_PAGES > 0) +static struct { + u8 data[PAGE_SIZE * EROFS_PCPUBUF_NR_PAGES]; +} ____cacheline_aligned_in_smp erofs_pcpubuf[NR_CPUS]; + +void *erofs_get_pcpubuf(unsigned int pagenr) +{ + preempt_disable(); + return &erofs_pcpubuf[smp_processor_id()].data[pagenr * PAGE_SIZE]; +} +#endif + +#ifdef CONFIG_EROFS_FS_ZIP /* global shrink count (for all mounted EROFS instances) */ static atomic_long_t erofs_global_shrink_cnt; -#ifdef CONFIG_EROFS_FS_ZIP +#define __erofs_workgroup_get(grp) atomic_inc(&(grp)->refcount) +#define __erofs_workgroup_put(grp) atomic_dec(&(grp)->refcount) -/* radix_tree and the future XArray both don't use tagptr_t yet */ -struct erofs_workgroup *erofs_find_workgroup( - struct super_block *sb, pgoff_t index, bool *tag) +static int erofs_workgroup_get(struct erofs_workgroup *grp) +{ + int o; + +repeat: + o = erofs_wait_on_workgroup_freezed(grp); + if (o <= 0) + return -1; + + if (atomic_cmpxchg(&grp->refcount, o, o + 1) != o) + goto repeat; + + /* decrease refcount paired by erofs_workgroup_put */ + if (o == 1) + atomic_long_dec(&erofs_global_shrink_cnt); + return 0; +} + +struct erofs_workgroup *erofs_find_workgroup(struct super_block *sb, + pgoff_t index) { struct erofs_sb_info *sbi = EROFS_SB(sb); struct erofs_workgroup *grp; - int oldcount; repeat: rcu_read_lock(); grp = radix_tree_lookup(&sbi->workstn_tree, index); - if (grp != NULL) { - *tag = radix_tree_exceptional_entry(grp); - grp = (void *)((unsigned long)grp & - ~RADIX_TREE_EXCEPTIONAL_ENTRY); - - if (erofs_workgroup_get(grp, &oldcount)) { + if (grp) { + if (erofs_workgroup_get(grp)) { /* prefer to relax rcu read side */ rcu_read_unlock(); goto repeat; } - /* decrease refcount added by erofs_workgroup_put */ - if (unlikely(oldcount == 1)) - atomic_long_dec(&erofs_global_shrink_cnt); DBG_BUGON(index != grp->index); } rcu_read_unlock(); @@ -64,14 +80,13 @@ struct erofs_workgroup *erofs_find_workgroup( } int erofs_register_workgroup(struct super_block *sb, - struct erofs_workgroup *grp, - bool tag) + struct erofs_workgroup *grp) { struct erofs_sb_info *sbi; int err; /* grp shouldn't be broken or used before */ - if (unlikely(atomic_read(&grp->refcount) != 1)) { + if (atomic_read(&grp->refcount) != 1) { DBG_BUGON(1); return -EINVAL; } @@ -81,35 +96,28 @@ int erofs_register_workgroup(struct super_block *sb, return err; sbi = EROFS_SB(sb); - erofs_workstn_lock(sbi); - - if (tag) - grp = (void *)((unsigned long)grp | - 1UL << RADIX_TREE_EXCEPTIONAL_SHIFT); + xa_lock(&sbi->workstn_tree); /* * Bump up reference count before making this workgroup * visible to other users in order to avoid potential UAF - * without serialized by erofs_workstn_lock. + * without serialized by workstn_lock. */ __erofs_workgroup_get(grp); - err = radix_tree_insert(&sbi->workstn_tree, - grp->index, grp); - if (unlikely(err)) + err = radix_tree_insert(&sbi->workstn_tree, grp->index, grp); + if (err) /* * it's safe to decrease since the workgroup isn't visible * and refcount >= 2 (cannot be freezed). */ __erofs_workgroup_put(grp); - erofs_workstn_unlock(sbi); + xa_unlock(&sbi->workstn_tree); radix_tree_preload_end(); return err; } -extern void erofs_workgroup_free_rcu(struct erofs_workgroup *grp); - static void __erofs_workgroup_free(struct erofs_workgroup *grp) { atomic_long_dec(&erofs_global_shrink_cnt); @@ -127,33 +135,22 @@ int erofs_workgroup_put(struct erofs_workgroup *grp) return count; } -#ifdef EROFS_FS_HAS_MANAGED_CACHE -/* for cache-managed case, customized reclaim paths exist */ -static void erofs_workgroup_unfreeze_final(struct erofs_workgroup *grp) +static bool erofs_try_to_release_workgroup(struct erofs_sb_info *sbi, + struct erofs_workgroup *grp) { - erofs_workgroup_unfreeze(grp, 0); - __erofs_workgroup_free(grp); -} - -bool erofs_try_to_release_workgroup(struct erofs_sb_info *sbi, - struct erofs_workgroup *grp, - bool cleanup) -{ - void *entry; - /* - * for managed cache enabled, the refcount of workgroups - * themselves could be < 0 (freezed). So there is no guarantee - * that all refcount > 0 if managed cache is enabled. + * If managed cache is on, refcount of workgroups + * themselves could be < 0 (freezed). In other words, + * there is no guarantee that all refcounts > 0. */ if (!erofs_workgroup_try_to_freeze(grp, 1)) return false; /* - * note that all cached pages should be unlinked - * before delete it from the radix tree. - * Otherwise some cached pages of an orphan old workgroup - * could be still linked after the new one is available. + * Note that all cached pages should be unattached + * before deleted from the radix tree. Otherwise some + * cached pages could be still attached to the orphan + * old workgroup when the new one is available in the tree. */ if (erofs_try_to_free_all_cached_pages(sbi, grp)) { erofs_workgroup_unfreeze(grp, 1); @@ -161,87 +158,52 @@ bool erofs_try_to_release_workgroup(struct erofs_sb_info *sbi, } /* - * it is impossible to fail after the workgroup is freezed, + * It's impossible to fail after the workgroup is freezed, * however in order to avoid some race conditions, add a * DBG_BUGON to observe this in advance. */ - entry = radix_tree_delete(&sbi->workstn_tree, grp->index); - DBG_BUGON((void *)((unsigned long)entry & - ~RADIX_TREE_EXCEPTIONAL_ENTRY) != grp); + DBG_BUGON(radix_tree_delete(&sbi->workstn_tree, grp->index) != grp); - /* - * if managed cache is enable, the last refcount - * should indicate the related workstation. - */ - erofs_workgroup_unfreeze_final(grp); + /* last refcount should be connected with its managed pslot. */ + erofs_workgroup_unfreeze(grp, 0); + __erofs_workgroup_free(grp); return true; } -#else -/* for nocache case, no customized reclaim path at all */ -bool erofs_try_to_release_workgroup(struct erofs_sb_info *sbi, - struct erofs_workgroup *grp, - bool cleanup) -{ - int cnt = atomic_read(&grp->refcount); - void *entry; - - DBG_BUGON(cnt <= 0); - DBG_BUGON(cleanup && cnt != 1); - - if (cnt > 1) - return false; - - entry = radix_tree_delete(&sbi->workstn_tree, grp->index); - DBG_BUGON((void *)((unsigned long)entry & - ~RADIX_TREE_EXCEPTIONAL_ENTRY) != grp); - - /* (rarely) could be grabbed again when freeing */ - erofs_workgroup_put(grp); - return true; -} - -#endif - -unsigned long erofs_shrink_workstation(struct erofs_sb_info *sbi, - unsigned long nr_shrink, - bool cleanup) +static unsigned long erofs_shrink_workstation(struct erofs_sb_info *sbi, + unsigned long nr_shrink) { pgoff_t first_index = 0; void *batch[PAGEVEC_SIZE]; - unsigned freed = 0; + unsigned int freed = 0; int i, found; repeat: - erofs_workstn_lock(sbi); + xa_lock(&sbi->workstn_tree); found = radix_tree_gang_lookup(&sbi->workstn_tree, - batch, first_index, PAGEVEC_SIZE); + batch, first_index, PAGEVEC_SIZE); for (i = 0; i < found; ++i) { - struct erofs_workgroup *grp = (void *) - ((unsigned long)batch[i] & - ~RADIX_TREE_EXCEPTIONAL_ENTRY); + struct erofs_workgroup *grp = batch[i]; first_index = grp->index + 1; /* try to shrink each valid workgroup */ - if (!erofs_try_to_release_workgroup(sbi, grp, cleanup)) + if (!erofs_try_to_release_workgroup(sbi, grp)) continue; ++freed; - if (unlikely(!--nr_shrink)) + if (!--nr_shrink) break; } - erofs_workstn_unlock(sbi); + xa_unlock(&sbi->workstn_tree); if (i && nr_shrink) goto repeat; return freed; } -#endif - /* protected by 'erofs_sb_list_lock' */ static unsigned int shrinker_run_no; @@ -249,7 +211,7 @@ static unsigned int shrinker_run_no; static DEFINE_SPINLOCK(erofs_sb_list_lock); static LIST_HEAD(erofs_sb_list); -void erofs_register_super(struct super_block *sb) +void erofs_shrinker_register(struct super_block *sb) { struct erofs_sb_info *sbi = EROFS_SB(sb); @@ -260,21 +222,28 @@ void erofs_register_super(struct super_block *sb) spin_unlock(&erofs_sb_list_lock); } -void erofs_unregister_super(struct super_block *sb) +void erofs_shrinker_unregister(struct super_block *sb) { + struct erofs_sb_info *const sbi = EROFS_SB(sb); + + mutex_lock(&sbi->umount_mutex); + /* clean up all remaining workgroups in memory */ + erofs_shrink_workstation(sbi, ~0UL); + spin_lock(&erofs_sb_list_lock); - list_del(&EROFS_SB(sb)->list); + list_del(&sbi->list); spin_unlock(&erofs_sb_list_lock); + mutex_unlock(&sbi->umount_mutex); } -unsigned long erofs_shrink_count(struct shrinker *shrink, - struct shrink_control *sc) +static unsigned long erofs_shrink_count(struct shrinker *shrink, + struct shrink_control *sc) { return atomic_long_read(&erofs_global_shrink_cnt); } -unsigned long erofs_shrink_scan(struct shrinker *shrink, - struct shrink_control *sc) +static unsigned long erofs_shrink_scan(struct shrinker *shrink, + struct shrink_control *sc) { struct erofs_sb_info *sbi; struct list_head *p; @@ -284,9 +253,9 @@ unsigned long erofs_shrink_scan(struct shrinker *shrink, unsigned long freed = 0; spin_lock(&erofs_sb_list_lock); - do + do { run_no = ++shrinker_run_no; - while (run_no == 0); + } while (run_no == 0); /* Iterate over all mounted superblocks and try to shrink them */ p = erofs_sb_list.next; @@ -308,9 +277,7 @@ unsigned long erofs_shrink_scan(struct shrinker *shrink, spin_unlock(&erofs_sb_list_lock); sbi->shrinker_run_no = run_no; -#ifdef CONFIG_EROFS_FS_ZIP - freed += erofs_shrink_workstation(sbi, nr - freed, false); -#endif + freed += erofs_shrink_workstation(sbi, nr - freed); spin_lock(&erofs_sb_list_lock); /* Get the next list element before we move this one */ @@ -330,3 +297,19 @@ unsigned long erofs_shrink_scan(struct shrinker *shrink, return freed; } +static struct shrinker erofs_shrinker_info = { + .scan_objects = erofs_shrink_scan, + .count_objects = erofs_shrink_count, + .seeks = DEFAULT_SEEKS, +}; + +int __init erofs_init_shrinker(void) +{ + return register_shrinker(&erofs_shrinker_info); +} + +void erofs_exit_shrinker(void) +{ + unregister_shrinker(&erofs_shrinker_info); +} +#endif /* !CONFIG_EROFS_FS_ZIP */ diff --git a/drivers/staging/erofs/xattr.c b/drivers/staging/erofs/xattr.c index d48687ca2199..2b9bb3a7a5f2 100644 --- a/drivers/staging/erofs/xattr.c +++ b/drivers/staging/erofs/xattr.c @@ -1,14 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * linux/drivers/staging/erofs/xattr.c - * * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ #include #include "xattr.h" @@ -19,13 +12,13 @@ struct xattr_iter { void *kaddr; erofs_blk_t blkaddr; - unsigned ofs; + unsigned int ofs; }; static inline void xattr_iter_end(struct xattr_iter *it, bool atomic) { /* the only user of kunmap() is 'init_inode_xattrs' */ - if (unlikely(!atomic)) + if (!atomic) kunmap(it->page); else kunmap_atomic(it->kaddr); @@ -44,23 +37,30 @@ static inline void xattr_iter_end_final(struct xattr_iter *it) static int init_inode_xattrs(struct inode *inode) { - struct erofs_vnode *const vi = EROFS_V(inode); + struct erofs_inode *const vi = EROFS_I(inode); struct xattr_iter it; - unsigned i; + unsigned int i; struct erofs_xattr_ibody_header *ih; + struct super_block *sb; struct erofs_sb_info *sbi; bool atomic_map; int ret = 0; /* the most case is that xattrs of this inode are initialized. */ - if (test_bit(EROFS_V_EA_INITED_BIT, &vi->flags)) + if (test_bit(EROFS_I_EA_INITED_BIT, &vi->flags)) { + /* + * paired with smp_mb() at the end of the function to ensure + * fields will only be observed after the bit is set. + */ + smp_mb(); return 0; + } - if (wait_on_bit_lock(&vi->flags, EROFS_V_BL_XATTR_BIT, TASK_KILLABLE)) + if (wait_on_bit_lock(&vi->flags, EROFS_I_BL_XATTR_BIT, TASK_KILLABLE)) return -ERESTARTSYS; /* someone has initialized xattrs for us? */ - if (test_bit(EROFS_V_EA_INITED_BIT, &vi->flags)) + if (test_bit(EROFS_I_EA_INITED_BIT, &vi->flags)) goto out_unlock; /* @@ -72,25 +72,29 @@ static int init_inode_xattrs(struct inode *inode) * undefined right now (maybe use later with some new sb feature). */ if (vi->xattr_isize == sizeof(struct erofs_xattr_ibody_header)) { - errln("xattr_isize %d of nid %llu is not supported yet", - vi->xattr_isize, vi->nid); - ret = -ENOTSUPP; + erofs_err(inode->i_sb, + "xattr_isize %d of nid %llu is not supported yet", + vi->xattr_isize, vi->nid); + ret = -EOPNOTSUPP; goto out_unlock; } else if (vi->xattr_isize < sizeof(struct erofs_xattr_ibody_header)) { - if (unlikely(vi->xattr_isize)) { + if (vi->xattr_isize) { + erofs_err(inode->i_sb, + "bogus xattr ibody @ nid %llu", vi->nid); DBG_BUGON(1); - ret = -EIO; + ret = -EFSCORRUPTED; goto out_unlock; /* xattr ondisk layout error */ } ret = -ENOATTR; goto out_unlock; } - sbi = EROFS_I_SB(inode); + sb = inode->i_sb; + sbi = EROFS_SB(sb); it.blkaddr = erofs_blknr(iloc(sbi, vi->nid) + vi->inode_isize); it.ofs = erofs_blkoff(iloc(sbi, vi->nid) + vi->inode_isize); - it.page = erofs_get_inline_page(inode, it.blkaddr); + it.page = erofs_get_meta_page(sb, it.blkaddr); if (IS_ERR(it.page)) { ret = PTR_ERR(it.page); goto out_unlock; @@ -115,13 +119,12 @@ static int init_inode_xattrs(struct inode *inode) it.ofs += sizeof(struct erofs_xattr_ibody_header); for (i = 0; i < vi->xattr_shared_count; ++i) { - if (unlikely(it.ofs >= EROFS_BLKSIZ)) { + if (it.ofs >= EROFS_BLKSIZ) { /* cannot be unaligned */ - BUG_ON(it.ofs != EROFS_BLKSIZ); + DBG_BUGON(it.ofs != EROFS_BLKSIZ); xattr_iter_end(&it, atomic_map); - it.page = erofs_get_meta_page(inode->i_sb, - ++it.blkaddr, S_ISDIR(inode->i_mode)); + it.page = erofs_get_meta_page(sb, ++it.blkaddr); if (IS_ERR(it.page)) { kfree(vi->xattr_shared_xattrs); vi->xattr_shared_xattrs = NULL; @@ -139,18 +142,29 @@ static int init_inode_xattrs(struct inode *inode) } xattr_iter_end(&it, atomic_map); - set_bit(EROFS_V_EA_INITED_BIT, &vi->flags); + /* paired with smp_mb() at the beginning of the function. */ + smp_mb(); + set_bit(EROFS_I_EA_INITED_BIT, &vi->flags); out_unlock: - clear_and_wake_up_bit(EROFS_V_BL_XATTR_BIT, &vi->flags); + clear_and_wake_up_bit(EROFS_I_BL_XATTR_BIT, &vi->flags); return ret; } +/* + * the general idea for these return values is + * if 0 is returned, go on processing the current xattr; + * 1 (> 0) is returned, skip this round to process the next xattr; + * -err (< 0) is returned, an error (maybe ENOXATTR) occurred + * and need to be handled + */ struct xattr_iter_handlers { - int (*entry)(struct xattr_iter *, struct erofs_xattr_entry *); - int (*name)(struct xattr_iter *, unsigned, char *, unsigned); - int (*alloc_buffer)(struct xattr_iter *, unsigned); - void (*value)(struct xattr_iter *, unsigned, char *, unsigned); + int (*entry)(struct xattr_iter *_it, struct erofs_xattr_entry *entry); + int (*name)(struct xattr_iter *_it, unsigned int processed, char *buf, + unsigned int len); + int (*alloc_buffer)(struct xattr_iter *_it, unsigned int value_sz); + void (*value)(struct xattr_iter *_it, unsigned int processed, char *buf, + unsigned int len); }; static inline int xattr_iter_fixup(struct xattr_iter *it) @@ -161,7 +175,8 @@ static inline int xattr_iter_fixup(struct xattr_iter *it) xattr_iter_end(it, true); it->blkaddr += erofs_blknr(it->ofs); - it->page = erofs_get_meta_page(it->sb, it->blkaddr, false); + + it->page = erofs_get_meta_page(it->sb, it->blkaddr); if (IS_ERR(it->page)) { int err = PTR_ERR(it->page); @@ -175,15 +190,15 @@ static inline int xattr_iter_fixup(struct xattr_iter *it) } static int inline_xattr_iter_begin(struct xattr_iter *it, - struct inode *inode) + struct inode *inode) { - struct erofs_vnode *const vi = EROFS_V(inode); + struct erofs_inode *const vi = EROFS_I(inode); struct erofs_sb_info *const sbi = EROFS_SB(inode->i_sb); - unsigned xattr_header_sz, inline_xattr_ofs; + unsigned int xattr_header_sz, inline_xattr_ofs; xattr_header_sz = inlinexattr_header_size(inode); - if (unlikely(xattr_header_sz >= vi->xattr_isize)) { - BUG_ON(xattr_header_sz > vi->xattr_isize); + if (xattr_header_sz >= vi->xattr_isize) { + DBG_BUGON(xattr_header_sz > vi->xattr_isize); return -ENOATTR; } @@ -192,7 +207,7 @@ static int inline_xattr_iter_begin(struct xattr_iter *it, it->blkaddr = erofs_blknr(iloc(sbi, vi->nid) + inline_xattr_ofs); it->ofs = erofs_blkoff(iloc(sbi, vi->nid) + inline_xattr_ofs); - it->page = erofs_get_inline_page(inode, it->blkaddr); + it->page = erofs_get_meta_page(inode->i_sb, it->blkaddr); if (IS_ERR(it->page)) return PTR_ERR(it->page); @@ -200,11 +215,16 @@ static int inline_xattr_iter_begin(struct xattr_iter *it, return vi->xattr_isize - xattr_header_sz; } +/* + * Regardless of success or failure, `xattr_foreach' will end up with + * `ofs' pointing to the next xattr item rather than an arbitrary position. + */ static int xattr_foreach(struct xattr_iter *it, - const struct xattr_iter_handlers *op, unsigned int *tlimit) + const struct xattr_iter_handlers *op, + unsigned int *tlimit) { struct erofs_xattr_entry entry; - unsigned value_sz, processed, slice; + unsigned int value_sz, processed, slice; int err; /* 0. fixup blkaddr, ofs, ipage */ @@ -218,10 +238,14 @@ static int xattr_foreach(struct xattr_iter *it, * therefore entry should be in the page */ entry = *(struct erofs_xattr_entry *)(it->kaddr + it->ofs); - if (tlimit != NULL) { - unsigned entry_sz = EROFS_XATTR_ENTRY_SIZE(&entry); + if (tlimit) { + unsigned int entry_sz = erofs_xattr_entry_size(&entry); - BUG_ON(*tlimit < entry_sz); + /* xattr on-disk corruption: xattr entry beyond xattr_isize */ + if (*tlimit < entry_sz) { + DBG_BUGON(1); + return -EFSCORRUPTED; + } *tlimit -= entry_sz; } @@ -240,7 +264,7 @@ static int xattr_foreach(struct xattr_iter *it, while (processed < entry.e_name_len) { if (it->ofs >= EROFS_BLKSIZ) { - BUG_ON(it->ofs > EROFS_BLKSIZ); + DBG_BUGON(it->ofs > EROFS_BLKSIZ); err = xattr_iter_fixup(it); if (err) @@ -248,8 +272,8 @@ static int xattr_foreach(struct xattr_iter *it, it->ofs = 0; } - slice = min_t(unsigned, PAGE_SIZE - it->ofs, - entry.e_name_len - processed); + slice = min_t(unsigned int, PAGE_SIZE - it->ofs, + entry.e_name_len - processed); /* handle name */ err = op->name(it, processed, it->kaddr + it->ofs, slice); @@ -265,7 +289,7 @@ static int xattr_foreach(struct xattr_iter *it, /* 3. handle xattr value */ processed = 0; - if (op->alloc_buffer != NULL) { + if (op->alloc_buffer) { err = op->alloc_buffer(it, value_sz); if (err) { it->ofs += value_sz; @@ -275,7 +299,7 @@ static int xattr_foreach(struct xattr_iter *it, while (processed < value_sz) { if (it->ofs >= EROFS_BLKSIZ) { - BUG_ON(it->ofs > EROFS_BLKSIZ); + DBG_BUGON(it->ofs > EROFS_BLKSIZ); err = xattr_iter_fixup(it); if (err) @@ -283,17 +307,17 @@ static int xattr_foreach(struct xattr_iter *it, it->ofs = 0; } - slice = min_t(unsigned, PAGE_SIZE - it->ofs, - value_sz - processed); + slice = min_t(unsigned int, PAGE_SIZE - it->ofs, + value_sz - processed); op->value(it, processed, it->kaddr + it->ofs, slice); it->ofs += slice; processed += slice; } out: - /* we assume that ofs is aligned with 4 bytes */ + /* xattrs should be 4-byte aligned (on-disk constraint) */ it->ofs = EROFS_XATTR_ALIGN(it->ofs); - return err; + return err < 0 ? err : 0; } struct getxattr_iter { @@ -305,7 +329,7 @@ struct getxattr_iter { }; static int xattr_entrymatch(struct xattr_iter *_it, - struct erofs_xattr_entry *entry) + struct erofs_xattr_entry *entry) { struct getxattr_iter *it = container_of(_it, struct getxattr_iter, it); @@ -314,7 +338,7 @@ static int xattr_entrymatch(struct xattr_iter *_it, } static int xattr_namematch(struct xattr_iter *_it, - unsigned processed, char *buf, unsigned len) + unsigned int processed, char *buf, unsigned int len) { struct getxattr_iter *it = container_of(_it, struct getxattr_iter, it); @@ -322,17 +346,18 @@ static int xattr_namematch(struct xattr_iter *_it, } static int xattr_checkbuffer(struct xattr_iter *_it, - unsigned value_sz) + unsigned int value_sz) { struct getxattr_iter *it = container_of(_it, struct getxattr_iter, it); int err = it->buffer_size < value_sz ? -ERANGE : 0; it->buffer_size = value_sz; - return it->buffer == NULL ? 1 : err; + return !it->buffer ? 1 : err; } static void xattr_copyvalue(struct xattr_iter *_it, - unsigned processed, char *buf, unsigned len) + unsigned int processed, + char *buf, unsigned int len) { struct getxattr_iter *it = container_of(_it, struct getxattr_iter, it); @@ -349,7 +374,7 @@ static const struct xattr_iter_handlers find_xattr_handlers = { static int inline_getxattr(struct inode *inode, struct getxattr_iter *it) { int ret; - unsigned remaining; + unsigned int remaining; ret = inline_xattr_iter_begin(&it->it, inode); if (ret < 0) @@ -358,22 +383,20 @@ static int inline_getxattr(struct inode *inode, struct getxattr_iter *it) remaining = ret; while (remaining) { ret = xattr_foreach(&it->it, &find_xattr_handlers, &remaining); - if (ret >= 0) - break; - - if (ret != -ENOATTR) /* -ENOMEM, -EIO, etc. */ + if (ret != -ENOATTR) break; } xattr_iter_end_final(&it->it); - return ret < 0 ? ret : it->buffer_size; + return ret ? ret : it->buffer_size; } static int shared_getxattr(struct inode *inode, struct getxattr_iter *it) { - struct erofs_vnode *const vi = EROFS_V(inode); - struct erofs_sb_info *const sbi = EROFS_SB(inode->i_sb); - unsigned i; + struct erofs_inode *const vi = EROFS_I(inode); + struct super_block *const sb = inode->i_sb; + struct erofs_sb_info *const sbi = EROFS_SB(sb); + unsigned int i; int ret = -ENOATTR; for (i = 0; i < vi->xattr_shared_count; ++i) { @@ -386,8 +409,7 @@ static int shared_getxattr(struct inode *inode, struct getxattr_iter *it) if (i) xattr_iter_end(&it->it, true); - it->it.page = erofs_get_meta_page(inode->i_sb, - blkaddr, false); + it->it.page = erofs_get_meta_page(sb, blkaddr); if (IS_ERR(it->it.page)) return PTR_ERR(it->it.page); @@ -396,16 +418,13 @@ static int shared_getxattr(struct inode *inode, struct getxattr_iter *it) } ret = xattr_foreach(&it->it, &find_xattr_handlers, NULL); - if (ret >= 0) - break; - - if (ret != -ENOATTR) /* -ENOMEM, -EIO, etc. */ + if (ret != -ENOATTR) break; } if (vi->xattr_shared_count) xattr_iter_end_final(&it->it); - return ret < 0 ? ret : it->buffer_size; + return ret ? ret : it->buffer_size; } static bool erofs_xattr_user_list(struct dentry *dentry) @@ -419,13 +438,13 @@ static bool erofs_xattr_trusted_list(struct dentry *dentry) } int erofs_getxattr(struct inode *inode, int index, - const char *name, - void *buffer, size_t buffer_size) + const char *name, + void *buffer, size_t buffer_size) { int ret; struct getxattr_iter it; - if (unlikely(name == NULL)) + if (!name) return -EINVAL; ret = init_inode_xattrs(inode); @@ -450,8 +469,8 @@ int erofs_getxattr(struct inode *inode, int index, } static int erofs_xattr_generic_get(const struct xattr_handler *handler, - struct dentry *unused, struct inode *inode, - const char *name, void *buffer, size_t size) + struct dentry *unused, struct inode *inode, + const char *name, void *buffer, size_t size) { struct erofs_sb_info *const sbi = EROFS_I_SB(inode); @@ -461,8 +480,6 @@ static int erofs_xattr_generic_get(const struct xattr_handler *handler, return -EOPNOTSUPP; break; case EROFS_XATTR_INDEX_TRUSTED: - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; break; case EROFS_XATTR_INDEX_SECURITY: break; @@ -517,24 +534,23 @@ struct listxattr_iter { }; static int xattr_entrylist(struct xattr_iter *_it, - struct erofs_xattr_entry *entry) + struct erofs_xattr_entry *entry) { struct listxattr_iter *it = container_of(_it, struct listxattr_iter, it); - unsigned prefix_len; + unsigned int prefix_len; const char *prefix; const struct xattr_handler *h = erofs_xattr_handler(entry->e_name_index); - if (h == NULL || (h->list != NULL && !h->list(it->dentry))) + if (!h || (h->list && !h->list(it->dentry))) return 1; - /* Note that at least one of 'prefix' and 'name' should be non-NULL */ - prefix = h->prefix != NULL ? h->prefix : h->name; + prefix = xattr_prefix(h); prefix_len = strlen(prefix); - if (it->buffer == NULL) { + if (!it->buffer) { it->buffer_ofs += prefix_len + entry->e_name_len + 1; return 1; } @@ -549,7 +565,7 @@ static int xattr_entrylist(struct xattr_iter *_it, } static int xattr_namelist(struct xattr_iter *_it, - unsigned processed, char *buf, unsigned len) + unsigned int processed, char *buf, unsigned int len) { struct listxattr_iter *it = container_of(_it, struct listxattr_iter, it); @@ -560,7 +576,7 @@ static int xattr_namelist(struct xattr_iter *_it, } static int xattr_skipvalue(struct xattr_iter *_it, - unsigned value_sz) + unsigned int value_sz) { struct listxattr_iter *it = container_of(_it, struct listxattr_iter, it); @@ -579,7 +595,7 @@ static const struct xattr_iter_handlers list_xattr_handlers = { static int inline_listxattr(struct listxattr_iter *it) { int ret; - unsigned remaining; + unsigned int remaining; ret = inline_xattr_iter_begin(&it->it, d_inode(it->dentry)); if (ret < 0) @@ -588,19 +604,20 @@ static int inline_listxattr(struct listxattr_iter *it) remaining = ret; while (remaining) { ret = xattr_foreach(&it->it, &list_xattr_handlers, &remaining); - if (ret < 0) + if (ret) break; } xattr_iter_end_final(&it->it); - return ret < 0 ? ret : it->buffer_ofs; + return ret ? ret : it->buffer_ofs; } static int shared_listxattr(struct listxattr_iter *it) { struct inode *const inode = d_inode(it->dentry); - struct erofs_vnode *const vi = EROFS_V(inode); - struct erofs_sb_info *const sbi = EROFS_I_SB(inode); - unsigned i; + struct erofs_inode *const vi = EROFS_I(inode); + struct super_block *const sb = inode->i_sb; + struct erofs_sb_info *const sbi = EROFS_SB(sb); + unsigned int i; int ret = 0; for (i = 0; i < vi->xattr_shared_count; ++i) { @@ -612,8 +629,7 @@ static int shared_listxattr(struct listxattr_iter *it) if (i) xattr_iter_end(&it->it, true); - it->it.page = erofs_get_meta_page(inode->i_sb, - blkaddr, false); + it->it.page = erofs_get_meta_page(sb, blkaddr); if (IS_ERR(it->it.page)) return PTR_ERR(it->it.page); @@ -622,17 +638,17 @@ static int shared_listxattr(struct listxattr_iter *it) } ret = xattr_foreach(&it->it, &list_xattr_handlers, NULL); - if (ret < 0) + if (ret) break; } if (vi->xattr_shared_count) xattr_iter_end_final(&it->it); - return ret < 0 ? ret : it->buffer_ofs; + return ret ? ret : it->buffer_ofs; } ssize_t erofs_listxattr(struct dentry *dentry, - char *buffer, size_t buffer_size) + char *buffer, size_t buffer_size) { int ret; struct listxattr_iter it; @@ -656,3 +672,39 @@ ssize_t erofs_listxattr(struct dentry *dentry, return shared_listxattr(&it); } +#ifdef CONFIG_EROFS_FS_POSIX_ACL +struct posix_acl *erofs_get_acl(struct inode *inode, int type) +{ + struct posix_acl *acl; + int prefix, rc; + char *value = NULL; + + switch (type) { + case ACL_TYPE_ACCESS: + prefix = EROFS_XATTR_INDEX_POSIX_ACL_ACCESS; + break; + case ACL_TYPE_DEFAULT: + prefix = EROFS_XATTR_INDEX_POSIX_ACL_DEFAULT; + break; + default: + return ERR_PTR(-EINVAL); + } + + rc = erofs_getxattr(inode, prefix, "", NULL, 0); + if (rc > 0) { + value = kmalloc(rc, GFP_KERNEL); + if (!value) + return ERR_PTR(-ENOMEM); + rc = erofs_getxattr(inode, prefix, "", value, rc); + } + + if (rc == -ENOATTR) + acl = NULL; + else if (rc < 0) + acl = ERR_PTR(rc); + else + acl = posix_acl_from_xattr(&init_user_ns, value, rc); + kfree(value); + return acl; +} +#endif diff --git a/drivers/staging/erofs/xattr.h b/drivers/staging/erofs/xattr.h index 0c7379282fc5..366dcb400525 100644 --- a/drivers/staging/erofs/xattr.h +++ b/drivers/staging/erofs/xattr.h @@ -1,14 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * linux/drivers/staging/erofs/xattr.h - * +/* SPDX-License-Identifier: GPL-2.0-only */ +/* * Copyright (C) 2017-2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ #ifndef __EROFS_XATTR_H #define __EROFS_XATTR_H @@ -20,14 +13,14 @@ /* Attribute not found */ #define ENOATTR ENODATA -static inline unsigned inlinexattr_header_size(struct inode *inode) +static inline unsigned int inlinexattr_header_size(struct inode *inode) { - return sizeof(struct erofs_xattr_ibody_header) - + sizeof(u32) * EROFS_V(inode)->xattr_shared_count; + return sizeof(struct erofs_xattr_ibody_header) + + sizeof(u32) * EROFS_I(inode)->xattr_shared_count; } -static inline erofs_blk_t -xattrblock_addr(struct erofs_sb_info *sbi, unsigned xattr_id) +static inline erofs_blk_t xattrblock_addr(struct erofs_sb_info *sbi, + unsigned int xattr_id) { #ifdef CONFIG_EROFS_FS_XATTR return sbi->xattr_blkaddr + @@ -37,56 +30,59 @@ xattrblock_addr(struct erofs_sb_info *sbi, unsigned xattr_id) #endif } -static inline unsigned -xattrblock_offset(struct erofs_sb_info *sbi, unsigned xattr_id) +static inline unsigned int xattrblock_offset(struct erofs_sb_info *sbi, + unsigned int xattr_id) { return (xattr_id * sizeof(__u32)) % EROFS_BLKSIZ; } +#ifdef CONFIG_EROFS_FS_XATTR extern const struct xattr_handler erofs_xattr_user_handler; extern const struct xattr_handler erofs_xattr_trusted_handler; #ifdef CONFIG_EROFS_FS_SECURITY extern const struct xattr_handler erofs_xattr_security_handler; #endif -static inline const struct xattr_handler *erofs_xattr_handler(unsigned index) +static inline const struct xattr_handler *erofs_xattr_handler(unsigned int idx) { -static const struct xattr_handler *xattr_handler_map[] = { - [EROFS_XATTR_INDEX_USER] = &erofs_xattr_user_handler, + static const struct xattr_handler *xattr_handler_map[] = { + [EROFS_XATTR_INDEX_USER] = &erofs_xattr_user_handler, #ifdef CONFIG_EROFS_FS_POSIX_ACL - [EROFS_XATTR_INDEX_POSIX_ACL_ACCESS] = &posix_acl_access_xattr_handler, - [EROFS_XATTR_INDEX_POSIX_ACL_DEFAULT] = - &posix_acl_default_xattr_handler, + [EROFS_XATTR_INDEX_POSIX_ACL_ACCESS] = + &posix_acl_access_xattr_handler, + [EROFS_XATTR_INDEX_POSIX_ACL_DEFAULT] = + &posix_acl_default_xattr_handler, #endif - [EROFS_XATTR_INDEX_TRUSTED] = &erofs_xattr_trusted_handler, + [EROFS_XATTR_INDEX_TRUSTED] = &erofs_xattr_trusted_handler, #ifdef CONFIG_EROFS_FS_SECURITY - [EROFS_XATTR_INDEX_SECURITY] = &erofs_xattr_security_handler, + [EROFS_XATTR_INDEX_SECURITY] = &erofs_xattr_security_handler, #endif -}; - return index && index < ARRAY_SIZE(xattr_handler_map) ? - xattr_handler_map[index] : NULL; + }; + + return idx && idx < ARRAY_SIZE(xattr_handler_map) ? + xattr_handler_map[idx] : NULL; } -#ifdef CONFIG_EROFS_FS_XATTR - -extern const struct inode_operations erofs_generic_xattr_iops; -extern const struct inode_operations erofs_dir_xattr_iops; +extern const struct xattr_handler *erofs_xattr_handlers[]; int erofs_getxattr(struct inode *, int, const char *, void *, size_t); ssize_t erofs_listxattr(struct dentry *, char *, size_t); #else -static int __maybe_unused erofs_getxattr(struct inode *inode, int index, - const char *name, - void *buffer, size_t buffer_size) +static inline int erofs_getxattr(struct inode *inode, int index, + const char *name, void *buffer, + size_t buffer_size) { - return -ENOTSUPP; + return -EOPNOTSUPP; } -static ssize_t __maybe_unused erofs_listxattr(struct dentry *dentry, - char *buffer, size_t buffer_size) -{ - return -ENOTSUPP; -} +#define erofs_listxattr (NULL) +#define erofs_xattr_handlers (NULL) +#endif /* !CONFIG_EROFS_FS_XATTR */ + +#ifdef CONFIG_EROFS_FS_POSIX_ACL +struct posix_acl *erofs_get_acl(struct inode *inode, int type); +#else +#define erofs_get_acl (NULL) #endif #endif diff --git a/drivers/staging/erofs/zdata.c b/drivers/staging/erofs/zdata.c new file mode 100644 index 000000000000..37c3e28b1e91 --- /dev/null +++ b/drivers/staging/erofs/zdata.c @@ -0,0 +1,1370 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2018 HUAWEI, Inc. + * https://www.huawei.com/ + */ +#include "zdata.h" +#include "compress.h" +#include + +#include + +/* + * a compressed_pages[] placeholder in order to avoid + * being filled with file pages for in-place decompression. + */ +#define PAGE_UNALLOCATED ((void *)0x5F0E4B1D) + +/* how to allocate cached pages for a pcluster */ +enum z_erofs_cache_alloctype { + DONTALLOC, /* don't allocate any cached pages */ + DELAYEDALLOC, /* delayed allocation (at the time of submitting io) */ +}; + +/* + * tagged pointer with 1-bit tag for all compressed pages + * tag 0 - the page is just found with an extra page reference + */ +typedef tagptr1_t compressed_page_t; + +#define tag_compressed_page_justfound(page) \ + tagptr_fold(compressed_page_t, page, 1) + +static struct workqueue_struct *z_erofs_workqueue __read_mostly; +static struct kmem_cache *pcluster_cachep __read_mostly; + +void z_erofs_exit_zip_subsystem(void) +{ + destroy_workqueue(z_erofs_workqueue); + kmem_cache_destroy(pcluster_cachep); +} + +static inline int z_erofs_init_workqueue(void) +{ + const unsigned int onlinecpus = num_possible_cpus(); + + /* + * no need to spawn too many threads, limiting threads could minimum + * scheduling overhead, perhaps per-CPU threads should be better? + */ + z_erofs_workqueue = alloc_workqueue("erofs_unzipd", + WQ_UNBOUND | WQ_HIGHPRI, + onlinecpus + onlinecpus / 4); + return z_erofs_workqueue ? 0 : -ENOMEM; +} + +static void z_erofs_pcluster_init_once(void *ptr) +{ + struct z_erofs_pcluster *pcl = ptr; + struct z_erofs_collection *cl = z_erofs_primarycollection(pcl); + unsigned int i; + + mutex_init(&cl->lock); + cl->nr_pages = 0; + cl->vcnt = 0; + for (i = 0; i < Z_EROFS_CLUSTER_MAX_PAGES; ++i) + pcl->compressed_pages[i] = NULL; +} + +static void z_erofs_pcluster_init_always(struct z_erofs_pcluster *pcl) +{ + struct z_erofs_collection *cl = z_erofs_primarycollection(pcl); + + atomic_set(&pcl->obj.refcount, 1); + + DBG_BUGON(cl->nr_pages); + DBG_BUGON(cl->vcnt); +} + +int __init z_erofs_init_zip_subsystem(void) +{ + pcluster_cachep = kmem_cache_create("erofs_compress", + Z_EROFS_WORKGROUP_SIZE, 0, + SLAB_RECLAIM_ACCOUNT, + z_erofs_pcluster_init_once); + if (pcluster_cachep) { + if (!z_erofs_init_workqueue()) + return 0; + + kmem_cache_destroy(pcluster_cachep); + } + return -ENOMEM; +} + +enum z_erofs_collectmode { + COLLECT_SECONDARY, + COLLECT_PRIMARY, + /* + * The current collection was the tail of an exist chain, in addition + * that the previous processed chained collections are all decided to + * be hooked up to it. + * A new chain will be created for the remaining collections which are + * not processed yet, therefore different from COLLECT_PRIMARY_FOLLOWED, + * the next collection cannot reuse the whole page safely in + * the following scenario: + * ________________________________________________________________ + * | tail (partial) page | head (partial) page | + * | (belongs to the next cl) | (belongs to the current cl) | + * |_______PRIMARY_FOLLOWED_______|________PRIMARY_HOOKED___________| + */ + COLLECT_PRIMARY_HOOKED, + COLLECT_PRIMARY_FOLLOWED_NOINPLACE, + /* + * The current collection has been linked with the owned chain, and + * could also be linked with the remaining collections, which means + * if the processing page is the tail page of the collection, thus + * the current collection can safely use the whole page (since + * the previous collection is under control) for in-place I/O, as + * illustrated below: + * ________________________________________________________________ + * | tail (partial) page | head (partial) page | + * | (of the current cl) | (of the previous collection) | + * | PRIMARY_FOLLOWED or | | + * |_____PRIMARY_HOOKED___|____________PRIMARY_FOLLOWED____________| + * + * [ (*) the above page can be used as inplace I/O. ] + */ + COLLECT_PRIMARY_FOLLOWED, +}; + +struct z_erofs_collector { + struct z_erofs_pagevec_ctor vector; + + struct z_erofs_pcluster *pcl, *tailpcl; + struct z_erofs_collection *cl; + struct page **compressedpages; + z_erofs_next_pcluster_t owned_head; + + enum z_erofs_collectmode mode; +}; + +struct z_erofs_decompress_frontend { + struct inode *const inode; + + struct z_erofs_collector clt; + struct erofs_map_blocks map; + + bool readahead; + /* used for applying cache strategy on the fly */ + bool backmost; + erofs_off_t headoffset; +}; + +#define COLLECTOR_INIT() { \ + .owned_head = Z_EROFS_PCLUSTER_TAIL, \ + .mode = COLLECT_PRIMARY_FOLLOWED } + +#define DECOMPRESS_FRONTEND_INIT(__i) { \ + .inode = __i, .clt = COLLECTOR_INIT(), \ + .backmost = true, } + +static struct page *z_pagemap_global[Z_EROFS_VMAP_GLOBAL_PAGES]; +static DEFINE_MUTEX(z_pagemap_global_lock); + +static void preload_compressed_pages(struct z_erofs_collector *clt, + struct address_space *mc, + enum z_erofs_cache_alloctype type) +{ + const struct z_erofs_pcluster *pcl = clt->pcl; + const unsigned int clusterpages = BIT(pcl->clusterbits); + struct page **pages = clt->compressedpages; + pgoff_t index = pcl->obj.index + (pages - pcl->compressed_pages); + bool standalone = true; + + if (clt->mode < COLLECT_PRIMARY_FOLLOWED) + return; + + for (; pages < pcl->compressed_pages + clusterpages; ++pages) { + struct page *page; + compressed_page_t t; + + /* the compressed page was loaded before */ + if (READ_ONCE(*pages)) + continue; + + page = find_get_page(mc, index); + + if (page) { + t = tag_compressed_page_justfound(page); + } else if (type == DELAYEDALLOC) { + t = tagptr_init(compressed_page_t, PAGE_UNALLOCATED); + } else { /* DONTALLOC */ + if (standalone) + clt->compressedpages = pages; + standalone = false; + continue; + } + + if (!cmpxchg_relaxed(pages, NULL, tagptr_cast_ptr(t))) + continue; + + if (page) + put_page(page); + } + + if (standalone) /* downgrade to PRIMARY_FOLLOWED_NOINPLACE */ + clt->mode = COLLECT_PRIMARY_FOLLOWED_NOINPLACE; +} + +/* called by erofs_shrinker to get rid of all compressed_pages */ +int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, + struct erofs_workgroup *grp) +{ + struct z_erofs_pcluster *const pcl = + container_of(grp, struct z_erofs_pcluster, obj); + struct address_space *const mapping = MNGD_MAPPING(sbi); + const unsigned int clusterpages = BIT(pcl->clusterbits); + int i; + + /* + * refcount of workgroup is now freezed as 1, + * therefore no need to worry about available decompression users. + */ + for (i = 0; i < clusterpages; ++i) { + struct page *page = pcl->compressed_pages[i]; + + if (!page) + continue; + + /* block other users from reclaiming or migrating the page */ + if (!trylock_page(page)) + return -EBUSY; + + if (page->mapping != mapping) + continue; + + /* barrier is implied in the following 'unlock_page' */ + WRITE_ONCE(pcl->compressed_pages[i], NULL); + set_page_private(page, 0); + ClearPagePrivate(page); + + unlock_page(page); + put_page(page); + } + return 0; +} + +int erofs_try_to_free_cached_page(struct address_space *mapping, + struct page *page) +{ + struct z_erofs_pcluster *const pcl = (void *)page_private(page); + const unsigned int clusterpages = BIT(pcl->clusterbits); + int ret = 0; /* 0 - busy */ + + if (erofs_workgroup_try_to_freeze(&pcl->obj, 1)) { + unsigned int i; + + for (i = 0; i < clusterpages; ++i) { + if (pcl->compressed_pages[i] == page) { + WRITE_ONCE(pcl->compressed_pages[i], NULL); + ret = 1; + break; + } + } + erofs_workgroup_unfreeze(&pcl->obj, 1); + + if (ret) { + ClearPagePrivate(page); + put_page(page); + } + } + return ret; +} + +/* page_type must be Z_EROFS_PAGE_TYPE_EXCLUSIVE */ +static inline bool z_erofs_try_inplace_io(struct z_erofs_collector *clt, + struct page *page) +{ + struct z_erofs_pcluster *const pcl = clt->pcl; + const unsigned int clusterpages = BIT(pcl->clusterbits); + + while (clt->compressedpages < pcl->compressed_pages + clusterpages) { + if (!cmpxchg(clt->compressedpages++, NULL, page)) + return true; + } + return false; +} + +/* callers must be with collection lock held */ +static int z_erofs_attach_page(struct z_erofs_collector *clt, + struct page *page, + enum z_erofs_page_type type) +{ + int ret; + bool occupied; + + /* give priority for inplaceio */ + if (clt->mode >= COLLECT_PRIMARY && + type == Z_EROFS_PAGE_TYPE_EXCLUSIVE && + z_erofs_try_inplace_io(clt, page)) + return 0; + + ret = z_erofs_pagevec_enqueue(&clt->vector, + page, type, &occupied); + clt->cl->vcnt += (unsigned int)ret; + + return ret ? 0 : -EAGAIN; +} + +static enum z_erofs_collectmode +try_to_claim_pcluster(struct z_erofs_pcluster *pcl, + z_erofs_next_pcluster_t *owned_head) +{ + /* let's claim these following types of pclusters */ +retry: + if (pcl->next == Z_EROFS_PCLUSTER_NIL) { + /* type 1, nil pcluster */ + if (cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_NIL, + *owned_head) != Z_EROFS_PCLUSTER_NIL) + goto retry; + + *owned_head = &pcl->next; + /* lucky, I am the followee :) */ + return COLLECT_PRIMARY_FOLLOWED; + } else if (pcl->next == Z_EROFS_PCLUSTER_TAIL) { + /* + * type 2, link to the end of a existing open chain, + * be careful that its submission itself is governed + * by the original owned chain. + */ + if (cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_TAIL, + *owned_head) != Z_EROFS_PCLUSTER_TAIL) + goto retry; + *owned_head = Z_EROFS_PCLUSTER_TAIL; + return COLLECT_PRIMARY_HOOKED; + } + return COLLECT_PRIMARY; /* :( better luck next time */ +} + +static int z_erofs_lookup_collection(struct z_erofs_collector *clt, + struct inode *inode, + struct erofs_map_blocks *map) +{ + struct erofs_workgroup *grp; + struct z_erofs_pcluster *pcl; + struct z_erofs_collection *cl; + unsigned int length; + + grp = erofs_find_workgroup(inode->i_sb, map->m_pa >> PAGE_SHIFT); + if (!grp) + return -ENOENT; + + pcl = container_of(grp, struct z_erofs_pcluster, obj); + if (clt->owned_head == &pcl->next || pcl == clt->tailpcl) { + DBG_BUGON(1); + erofs_workgroup_put(grp); + return -EFSCORRUPTED; + } + + cl = z_erofs_primarycollection(pcl); + if (cl->pageofs != (map->m_la & ~PAGE_MASK)) { + DBG_BUGON(1); + erofs_workgroup_put(grp); + return -EFSCORRUPTED; + } + + length = READ_ONCE(pcl->length); + if (length & Z_EROFS_PCLUSTER_FULL_LENGTH) { + if ((map->m_llen << Z_EROFS_PCLUSTER_LENGTH_BIT) > length) { + DBG_BUGON(1); + erofs_workgroup_put(grp); + return -EFSCORRUPTED; + } + } else { + unsigned int llen = map->m_llen << Z_EROFS_PCLUSTER_LENGTH_BIT; + + if (map->m_flags & EROFS_MAP_FULL_MAPPED) + llen |= Z_EROFS_PCLUSTER_FULL_LENGTH; + + while (llen > length && + length != cmpxchg_relaxed(&pcl->length, length, llen)) { + cpu_relax(); + length = READ_ONCE(pcl->length); + } + } + mutex_lock(&cl->lock); + /* used to check tail merging loop due to corrupted images */ + if (clt->owned_head == Z_EROFS_PCLUSTER_TAIL) + clt->tailpcl = pcl; + clt->mode = try_to_claim_pcluster(pcl, &clt->owned_head); + /* clean tailpcl if the current owned_head is Z_EROFS_PCLUSTER_TAIL */ + if (clt->owned_head == Z_EROFS_PCLUSTER_TAIL) + clt->tailpcl = NULL; + clt->pcl = pcl; + clt->cl = cl; + return 0; +} + +static int z_erofs_register_collection(struct z_erofs_collector *clt, + struct inode *inode, + struct erofs_map_blocks *map) +{ + struct z_erofs_pcluster *pcl; + struct z_erofs_collection *cl; + int err; + + /* no available workgroup, let's allocate one */ + pcl = kmem_cache_alloc(pcluster_cachep, GFP_NOFS); + if (!pcl) + return -ENOMEM; + + z_erofs_pcluster_init_always(pcl); + pcl->obj.index = map->m_pa >> PAGE_SHIFT; + + pcl->length = (map->m_llen << Z_EROFS_PCLUSTER_LENGTH_BIT) | + (map->m_flags & EROFS_MAP_FULL_MAPPED ? + Z_EROFS_PCLUSTER_FULL_LENGTH : 0); + + if (map->m_flags & EROFS_MAP_ZIPPED) + pcl->algorithmformat = Z_EROFS_COMPRESSION_LZ4; + else + pcl->algorithmformat = Z_EROFS_COMPRESSION_SHIFTED; + + pcl->clusterbits = EROFS_I(inode)->z_physical_clusterbits[0]; + pcl->clusterbits -= PAGE_SHIFT; + + /* new pclusters should be claimed as type 1, primary and followed */ + pcl->next = clt->owned_head; + clt->mode = COLLECT_PRIMARY_FOLLOWED; + + cl = z_erofs_primarycollection(pcl); + cl->pageofs = map->m_la & ~PAGE_MASK; + + /* + * lock all primary followed works before visible to others + * and mutex_trylock *never* fails for a new pcluster. + */ + mutex_trylock(&cl->lock); + + err = erofs_register_workgroup(inode->i_sb, &pcl->obj); + if (err) { + mutex_unlock(&cl->lock); + kmem_cache_free(pcluster_cachep, pcl); + return -EAGAIN; + } + /* used to check tail merging loop due to corrupted images */ + if (clt->owned_head == Z_EROFS_PCLUSTER_TAIL) + clt->tailpcl = pcl; + clt->owned_head = &pcl->next; + clt->pcl = pcl; + clt->cl = cl; + return 0; +} + +static int z_erofs_collector_begin(struct z_erofs_collector *clt, + struct inode *inode, + struct erofs_map_blocks *map) +{ + int ret; + + DBG_BUGON(clt->cl); + + /* must be Z_EROFS_PCLUSTER_TAIL or pointed to previous collection */ + DBG_BUGON(clt->owned_head == Z_EROFS_PCLUSTER_NIL); + DBG_BUGON(clt->owned_head == Z_EROFS_PCLUSTER_TAIL_CLOSED); + + if (!PAGE_ALIGNED(map->m_pa)) { + DBG_BUGON(1); + return -EINVAL; + } + +repeat: + ret = z_erofs_lookup_collection(clt, inode, map); + if (ret == -ENOENT) { + ret = z_erofs_register_collection(clt, inode, map); + + /* someone registered at the same time, give another try */ + if (ret == -EAGAIN) { + cond_resched(); + goto repeat; + } + } + + if (ret) + return ret; + + z_erofs_pagevec_ctor_init(&clt->vector, Z_EROFS_NR_INLINE_PAGEVECS, + clt->cl->pagevec, clt->cl->vcnt); + + clt->compressedpages = clt->pcl->compressed_pages; + if (clt->mode <= COLLECT_PRIMARY) /* cannot do in-place I/O */ + clt->compressedpages += Z_EROFS_CLUSTER_MAX_PAGES; + return 0; +} + +/* + * keep in mind that no referenced pclusters will be freed + * only after a RCU grace period. + */ +static void z_erofs_rcu_callback(struct rcu_head *head) +{ + struct z_erofs_collection *const cl = + container_of(head, struct z_erofs_collection, rcu); + + kmem_cache_free(pcluster_cachep, + container_of(cl, struct z_erofs_pcluster, + primary_collection)); +} + +void erofs_workgroup_free_rcu(struct erofs_workgroup *grp) +{ + struct z_erofs_pcluster *const pcl = + container_of(grp, struct z_erofs_pcluster, obj); + struct z_erofs_collection *const cl = z_erofs_primarycollection(pcl); + + call_rcu(&cl->rcu, z_erofs_rcu_callback); +} + +static void z_erofs_collection_put(struct z_erofs_collection *cl) +{ + struct z_erofs_pcluster *const pcl = + container_of(cl, struct z_erofs_pcluster, primary_collection); + + erofs_workgroup_put(&pcl->obj); +} + +static bool z_erofs_collector_end(struct z_erofs_collector *clt) +{ + struct z_erofs_collection *cl = clt->cl; + + if (!cl) + return false; + + z_erofs_pagevec_ctor_exit(&clt->vector, false); + mutex_unlock(&cl->lock); + + /* + * if all pending pages are added, don't hold its reference + * any longer if the pcluster isn't hosted by ourselves. + */ + if (clt->mode < COLLECT_PRIMARY_FOLLOWED_NOINPLACE) + z_erofs_collection_put(cl); + + clt->cl = NULL; + return true; +} + +static bool should_alloc_managed_pages(struct z_erofs_decompress_frontend *fe, + unsigned int cachestrategy, + erofs_off_t la) +{ + if (cachestrategy <= EROFS_ZIP_CACHE_DISABLED) + return false; + + if (fe->backmost) + return true; + + return cachestrategy >= EROFS_ZIP_CACHE_READAROUND && + la < fe->headoffset; +} + +static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, + struct page *page) +{ + struct inode *const inode = fe->inode; + struct erofs_sb_info *const sbi = EROFS_I_SB(inode); + struct erofs_map_blocks *const map = &fe->map; + struct z_erofs_collector *const clt = &fe->clt; + const loff_t offset = page_offset(page); + bool tight = true; + + enum z_erofs_cache_alloctype cache_strategy; + enum z_erofs_page_type page_type; + unsigned int cur, end, spiltted, index; + int err = 0; + + /* register locked file pages as online pages in pack */ + z_erofs_onlinepage_init(page); + + spiltted = 0; + end = PAGE_SIZE; +repeat: + cur = end - 1; + + /* lucky, within the range of the current map_blocks */ + if (offset + cur >= map->m_la && + offset + cur < map->m_la + map->m_llen) { + /* didn't get a valid collection previously (very rare) */ + if (!clt->cl) + goto restart_now; + goto hitted; + } + + /* go ahead the next map_blocks */ + erofs_dbg("%s: [out-of-range] pos %llu", __func__, offset + cur); + + if (z_erofs_collector_end(clt)) + fe->backmost = false; + + map->m_la = offset + cur; + map->m_llen = 0; + err = z_erofs_map_blocks_iter(inode, map, 0); + if (err) + goto err_out; + +restart_now: + if (!(map->m_flags & EROFS_MAP_MAPPED)) + goto hitted; + + err = z_erofs_collector_begin(clt, inode, map); + if (err) + goto err_out; + + /* preload all compressed pages (maybe downgrade role if necessary) */ + if (should_alloc_managed_pages(fe, sbi->cache_strategy, map->m_la)) + cache_strategy = DELAYEDALLOC; + else + cache_strategy = DONTALLOC; + + preload_compressed_pages(clt, MNGD_MAPPING(sbi), cache_strategy); + +hitted: + /* + * Ensure the current partial page belongs to this submit chain rather + * than other concurrent submit chains or the noio(bypass) chain since + * those chains are handled asynchronously thus the page cannot be used + * for inplace I/O or pagevec (should be processed in strict order.) + */ + tight &= (clt->mode >= COLLECT_PRIMARY_HOOKED && + clt->mode != COLLECT_PRIMARY_FOLLOWED_NOINPLACE); + + cur = end - min_t(unsigned int, offset + end - map->m_la, end); + if (!(map->m_flags & EROFS_MAP_MAPPED)) { + zero_user_segment(page, cur, end); + goto next_part; + } + + /* let's derive page type */ + page_type = cur ? Z_EROFS_VLE_PAGE_TYPE_HEAD : + (!spiltted ? Z_EROFS_PAGE_TYPE_EXCLUSIVE : + (tight ? Z_EROFS_PAGE_TYPE_EXCLUSIVE : + Z_EROFS_VLE_PAGE_TYPE_TAIL_SHARED)); + + if (cur) + tight &= (clt->mode >= COLLECT_PRIMARY_FOLLOWED); + +retry: + err = z_erofs_attach_page(clt, page, page_type); + /* should allocate an additional staging page for pagevec */ + if (err == -EAGAIN) { + struct page *const newpage = + alloc_page(GFP_NOFS | __GFP_NOFAIL); + + newpage->mapping = Z_EROFS_MAPPING_STAGING; + err = z_erofs_attach_page(clt, newpage, + Z_EROFS_PAGE_TYPE_EXCLUSIVE); + if (!err) + goto retry; + } + + if (err) + goto err_out; + + index = page->index - (map->m_la >> PAGE_SHIFT); + + z_erofs_onlinepage_fixup(page, index, true); + + /* bump up the number of spiltted parts of a page */ + ++spiltted; + /* also update nr_pages */ + clt->cl->nr_pages = max_t(pgoff_t, clt->cl->nr_pages, index + 1); +next_part: + /* can be used for verification */ + map->m_llen = offset + cur - map->m_la; + + end = cur; + if (end > 0) + goto repeat; + +out: + z_erofs_onlinepage_endio(page); + + erofs_dbg("%s, finish page: %pK spiltted: %u map->m_llen %llu", + __func__, page, spiltted, map->m_llen); + return err; + + /* if some error occurred while processing this page */ +err_out: + SetPageError(page); + goto out; +} + +static void z_erofs_decompress_kickoff(struct z_erofs_decompressqueue *io, + bool sync, int bios) +{ + /* wake up the caller thread for sync decompression */ + if (sync) { + unsigned long flags; + + spin_lock_irqsave(&io->u.wait.lock, flags); + if (!atomic_add_return(bios, &io->pending_bios)) + wake_up_locked(&io->u.wait); + spin_unlock_irqrestore(&io->u.wait.lock, flags); + return; + } + + if (!atomic_add_return(bios, &io->pending_bios)) + queue_work(z_erofs_workqueue, &io->u.work); +} + +static void z_erofs_decompressqueue_endio(struct bio *bio) +{ + tagptr1_t t = tagptr_init(tagptr1_t, bio->bi_private); + struct z_erofs_decompressqueue *q = tagptr_unfold_ptr(t); + blk_status_t err = bio->bi_status; + struct bio_vec *bvec; + unsigned int i; + + bio_for_each_segment_all(bvec, bio, i) { + struct page *page = bvec->bv_page; + + DBG_BUGON(PageUptodate(page)); + DBG_BUGON(!page->mapping); + + if (err) + SetPageError(page); + + if (erofs_page_is_managed(EROFS_SB(q->sb), page)) { + if (!err) + SetPageUptodate(page); + unlock_page(page); + } + } + z_erofs_decompress_kickoff(q, tagptr_unfold_tags(t), -1); + bio_put(bio); +} + +static int z_erofs_decompress_pcluster(struct super_block *sb, + struct z_erofs_pcluster *pcl, + struct list_head *pagepool) +{ + struct erofs_sb_info *const sbi = EROFS_SB(sb); + const unsigned int clusterpages = BIT(pcl->clusterbits); + struct z_erofs_pagevec_ctor ctor; + unsigned int i, outputsize, llen, nr_pages; + struct page *pages_onstack[Z_EROFS_VMAP_ONSTACK_PAGES]; + struct page **pages, **compressed_pages, *page; + + enum z_erofs_page_type page_type; + bool overlapped, partial; + struct z_erofs_collection *cl; + int err; + + might_sleep(); + cl = z_erofs_primarycollection(pcl); + DBG_BUGON(!READ_ONCE(cl->nr_pages)); + + mutex_lock(&cl->lock); + nr_pages = cl->nr_pages; + + if (nr_pages <= Z_EROFS_VMAP_ONSTACK_PAGES) { + pages = pages_onstack; + } else if (nr_pages <= Z_EROFS_VMAP_GLOBAL_PAGES && + mutex_trylock(&z_pagemap_global_lock)) { + pages = z_pagemap_global; + } else { + gfp_t gfp_flags = GFP_KERNEL; + + if (nr_pages > Z_EROFS_VMAP_GLOBAL_PAGES) + gfp_flags |= __GFP_NOFAIL; + + pages = kvmalloc_array(nr_pages, sizeof(struct page *), + gfp_flags); + + /* fallback to global pagemap for the lowmem scenario */ + if (!pages) { + mutex_lock(&z_pagemap_global_lock); + pages = z_pagemap_global; + } + } + + for (i = 0; i < nr_pages; ++i) + pages[i] = NULL; + + err = 0; + z_erofs_pagevec_ctor_init(&ctor, Z_EROFS_NR_INLINE_PAGEVECS, + cl->pagevec, 0); + + for (i = 0; i < cl->vcnt; ++i) { + unsigned int pagenr; + + page = z_erofs_pagevec_dequeue(&ctor, &page_type); + + /* all pages in pagevec ought to be valid */ + DBG_BUGON(!page); + DBG_BUGON(!page->mapping); + + if (z_erofs_put_stagingpage(pagepool, page)) + continue; + + if (page_type == Z_EROFS_VLE_PAGE_TYPE_HEAD) + pagenr = 0; + else + pagenr = z_erofs_onlinepage_index(page); + + DBG_BUGON(pagenr >= nr_pages); + + /* + * currently EROFS doesn't support multiref(dedup), + * so here erroring out one multiref page. + */ + if (pages[pagenr]) { + DBG_BUGON(1); + SetPageError(pages[pagenr]); + z_erofs_onlinepage_endio(pages[pagenr]); + err = -EFSCORRUPTED; + } + pages[pagenr] = page; + } + z_erofs_pagevec_ctor_exit(&ctor, true); + + overlapped = false; + compressed_pages = pcl->compressed_pages; + + for (i = 0; i < clusterpages; ++i) { + unsigned int pagenr; + + page = compressed_pages[i]; + + /* all compressed pages ought to be valid */ + DBG_BUGON(!page); + DBG_BUGON(!page->mapping); + + if (!z_erofs_page_is_staging(page)) { + if (erofs_page_is_managed(sbi, page)) { + if (!PageUptodate(page)) + err = -EIO; + continue; + } + + /* + * only if non-head page can be selected + * for inplace decompression + */ + pagenr = z_erofs_onlinepage_index(page); + + DBG_BUGON(pagenr >= nr_pages); + if (pages[pagenr]) { + DBG_BUGON(1); + SetPageError(pages[pagenr]); + z_erofs_onlinepage_endio(pages[pagenr]); + err = -EFSCORRUPTED; + } + pages[pagenr] = page; + + overlapped = true; + } + + /* PG_error needs checking for inplaced and staging pages */ + if (PageError(page)) { + DBG_BUGON(PageUptodate(page)); + err = -EIO; + } + } + + if (err) + goto out; + + llen = pcl->length >> Z_EROFS_PCLUSTER_LENGTH_BIT; + if (nr_pages << PAGE_SHIFT >= cl->pageofs + llen) { + outputsize = llen; + partial = !(pcl->length & Z_EROFS_PCLUSTER_FULL_LENGTH); + } else { + outputsize = (nr_pages << PAGE_SHIFT) - cl->pageofs; + partial = true; + } + + err = z_erofs_decompress(&(struct z_erofs_decompress_req) { + .sb = sb, + .in = compressed_pages, + .out = pages, + .pageofs_out = cl->pageofs, + .inputsize = PAGE_SIZE, + .outputsize = outputsize, + .alg = pcl->algorithmformat, + .inplace_io = overlapped, + .partial_decoding = partial + }, pagepool); + +out: + /* must handle all compressed pages before endding pages */ + for (i = 0; i < clusterpages; ++i) { + page = compressed_pages[i]; + + if (erofs_page_is_managed(sbi, page)) + continue; + + /* recycle all individual staging pages */ + (void)z_erofs_put_stagingpage(pagepool, page); + + WRITE_ONCE(compressed_pages[i], NULL); + } + + for (i = 0; i < nr_pages; ++i) { + page = pages[i]; + if (!page) + continue; + + DBG_BUGON(!page->mapping); + + /* recycle all individual staging pages */ + if (z_erofs_put_stagingpage(pagepool, page)) + continue; + + if (err < 0) + SetPageError(page); + + z_erofs_onlinepage_endio(page); + } + + if (pages == z_pagemap_global) + mutex_unlock(&z_pagemap_global_lock); + else if (pages != pages_onstack) + kvfree(pages); + + cl->nr_pages = 0; + cl->vcnt = 0; + + /* all cl locks MUST be taken before the following line */ + WRITE_ONCE(pcl->next, Z_EROFS_PCLUSTER_NIL); + + /* all cl locks SHOULD be released right now */ + mutex_unlock(&cl->lock); + + z_erofs_collection_put(cl); + return err; +} + +static void z_erofs_decompress_queue(const struct z_erofs_decompressqueue *io, + struct list_head *pagepool) +{ + z_erofs_next_pcluster_t owned = io->head; + + while (owned != Z_EROFS_PCLUSTER_TAIL_CLOSED) { + struct z_erofs_pcluster *pcl; + + /* no possible that 'owned' equals Z_EROFS_WORK_TPTR_TAIL */ + DBG_BUGON(owned == Z_EROFS_PCLUSTER_TAIL); + + /* no possible that 'owned' equals NULL */ + DBG_BUGON(owned == Z_EROFS_PCLUSTER_NIL); + + pcl = container_of(owned, struct z_erofs_pcluster, next); + owned = READ_ONCE(pcl->next); + + z_erofs_decompress_pcluster(io->sb, pcl, pagepool); + } +} + +static void z_erofs_decompressqueue_work(struct work_struct *work) +{ + struct z_erofs_decompressqueue *bgq = + container_of(work, struct z_erofs_decompressqueue, u.work); + LIST_HEAD(pagepool); + + DBG_BUGON(bgq->head == Z_EROFS_PCLUSTER_TAIL_CLOSED); + z_erofs_decompress_queue(bgq, &pagepool); + + put_pages_list(&pagepool); + kvfree(bgq); +} + +static struct page *pickup_page_for_submission(struct z_erofs_pcluster *pcl, + unsigned int nr, + struct list_head *pagepool, + struct address_space *mc, + gfp_t gfp) +{ + const pgoff_t index = pcl->obj.index; + bool tocache = false; + + struct address_space *mapping; + struct page *oldpage, *page; + + compressed_page_t t; + int justfound; + +repeat: + page = READ_ONCE(pcl->compressed_pages[nr]); + oldpage = page; + + if (!page) + goto out_allocpage; + + /* + * the cached page has not been allocated and + * an placeholder is out there, prepare it now. + */ + if (page == PAGE_UNALLOCATED) { + tocache = true; + goto out_allocpage; + } + + /* process the target tagged pointer */ + t = tagptr_init(compressed_page_t, page); + justfound = tagptr_unfold_tags(t); + page = tagptr_unfold_ptr(t); + + mapping = READ_ONCE(page->mapping); + + /* + * unmanaged (file) pages are all locked solidly, + * therefore it is impossible for `mapping' to be NULL. + */ + if (mapping && mapping != mc) + /* ought to be unmanaged pages */ + goto out; + + lock_page(page); + + /* only true if page reclaim goes wrong, should never happen */ + DBG_BUGON(justfound && PagePrivate(page)); + + /* the page is still in manage cache */ + if (page->mapping == mc) { + WRITE_ONCE(pcl->compressed_pages[nr], page); + + ClearPageError(page); + if (!PagePrivate(page)) { + /* + * impossible to be !PagePrivate(page) for + * the current restriction as well if + * the page is already in compressed_pages[]. + */ + DBG_BUGON(!justfound); + + justfound = 0; + set_page_private(page, (unsigned long)pcl); + SetPagePrivate(page); + } + + /* no need to submit io if it is already up-to-date */ + if (PageUptodate(page)) { + unlock_page(page); + page = NULL; + } + goto out; + } + + /* + * the managed page has been truncated, it's unsafe to + * reuse this one, let's allocate a new cache-managed page. + */ + DBG_BUGON(page->mapping); + DBG_BUGON(!justfound); + + tocache = true; + unlock_page(page); + put_page(page); +out_allocpage: + page = erofs_allocpage(pagepool, gfp | __GFP_NOFAIL); + if (!tocache || add_to_page_cache_lru(page, mc, index + nr, gfp)) { + /* non-LRU / non-movable temporary page is needed */ + page->mapping = Z_EROFS_MAPPING_STAGING; + tocache = false; + } + + if (oldpage != cmpxchg(&pcl->compressed_pages[nr], oldpage, page)) { + if (tocache) { + /* since it added to managed cache successfully */ + unlock_page(page); + put_page(page); + } else { + list_add(&page->lru, pagepool); + } + cond_resched(); + goto repeat; + } + + if (tocache) { + set_page_private(page, (unsigned long)pcl); + SetPagePrivate(page); + } +out: /* the only exit (for tracing and debugging) */ + return page; +} + +static struct z_erofs_decompressqueue * +jobqueue_init(struct super_block *sb, + struct z_erofs_decompressqueue *fgq, bool *fg) +{ + struct z_erofs_decompressqueue *q; + + if (fg && !*fg) { + q = kvzalloc(sizeof(*q), GFP_KERNEL | __GFP_NOWARN); + if (!q) { + *fg = true; + goto fg_out; + } + INIT_WORK(&q->u.work, z_erofs_decompressqueue_work); + } else { +fg_out: + q = fgq; + init_waitqueue_head(&fgq->u.wait); + atomic_set(&fgq->pending_bios, 0); + } + q->sb = sb; + q->head = Z_EROFS_PCLUSTER_TAIL_CLOSED; + return q; +} + +/* define decompression jobqueue types */ +enum { + JQ_BYPASS, + JQ_SUBMIT, + NR_JOBQUEUES, +}; + +static void *jobqueueset_init(struct super_block *sb, + struct z_erofs_decompressqueue *q[], + struct z_erofs_decompressqueue *fgq, bool *fg) +{ + /* + * if managed cache is enabled, bypass jobqueue is needed, + * no need to read from device for all pclusters in this queue. + */ + q[JQ_BYPASS] = jobqueue_init(sb, fgq + JQ_BYPASS, NULL); + q[JQ_SUBMIT] = jobqueue_init(sb, fgq + JQ_SUBMIT, fg); + + return tagptr_cast_ptr(tagptr_fold(tagptr1_t, q[JQ_SUBMIT], *fg)); +} + +static void move_to_bypass_jobqueue(struct z_erofs_pcluster *pcl, + z_erofs_next_pcluster_t qtail[], + z_erofs_next_pcluster_t owned_head) +{ + z_erofs_next_pcluster_t *const submit_qtail = qtail[JQ_SUBMIT]; + z_erofs_next_pcluster_t *const bypass_qtail = qtail[JQ_BYPASS]; + + DBG_BUGON(owned_head == Z_EROFS_PCLUSTER_TAIL_CLOSED); + if (owned_head == Z_EROFS_PCLUSTER_TAIL) + owned_head = Z_EROFS_PCLUSTER_TAIL_CLOSED; + + WRITE_ONCE(pcl->next, Z_EROFS_PCLUSTER_TAIL_CLOSED); + + WRITE_ONCE(*submit_qtail, owned_head); + WRITE_ONCE(*bypass_qtail, &pcl->next); + + qtail[JQ_BYPASS] = &pcl->next; +} + +static void z_erofs_submit_queue(struct super_block *sb, + struct z_erofs_decompress_frontend *f, + struct list_head *pagepool, + struct z_erofs_decompressqueue *fgq, + bool *force_fg) +{ + struct erofs_sb_info *const sbi = EROFS_SB(sb); + z_erofs_next_pcluster_t qtail[NR_JOBQUEUES]; + struct z_erofs_decompressqueue *q[NR_JOBQUEUES]; + void *bi_private; + z_erofs_next_pcluster_t owned_head = f->clt.owned_head; + /* since bio will be NULL, no need to initialize last_index */ + pgoff_t last_index; + unsigned int nr_bios = 0; + struct bio *bio = NULL; + + bi_private = jobqueueset_init(sb, q, fgq, force_fg); + qtail[JQ_BYPASS] = &q[JQ_BYPASS]->head; + qtail[JQ_SUBMIT] = &q[JQ_SUBMIT]->head; + + /* by default, all need io submission */ + q[JQ_SUBMIT]->head = owned_head; + + do { + struct z_erofs_pcluster *pcl; + pgoff_t cur, end; + unsigned int i = 0; + bool bypass = true; + + /* no possible 'owned_head' equals the following */ + DBG_BUGON(owned_head == Z_EROFS_PCLUSTER_TAIL_CLOSED); + DBG_BUGON(owned_head == Z_EROFS_PCLUSTER_NIL); + + pcl = container_of(owned_head, struct z_erofs_pcluster, next); + + cur = pcl->obj.index; + end = cur + BIT(pcl->clusterbits); + + /* close the main owned chain at first */ + owned_head = cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_TAIL, + Z_EROFS_PCLUSTER_TAIL_CLOSED); + + do { + struct page *page; + + page = pickup_page_for_submission(pcl, i++, pagepool, + MNGD_MAPPING(sbi), + GFP_NOFS); + if (!page) + continue; + + if (bio && cur != last_index + 1) { +submit_bio_retry: + submit_bio(bio); + bio = NULL; + } + + if (!bio) { + bio = bio_alloc(GFP_NOIO, BIO_MAX_PAGES); + + bio->bi_end_io = z_erofs_decompressqueue_endio; + bio_set_dev(bio, sb->s_bdev); + bio->bi_iter.bi_sector = (sector_t)cur << + LOG_SECTORS_PER_BLOCK; + bio->bi_private = bi_private; + bio->bi_opf = REQ_OP_READ; + if (f->readahead) + bio->bi_opf |= REQ_RAHEAD; + ++nr_bios; + } + + if (bio_add_page(bio, page, PAGE_SIZE, 0) < PAGE_SIZE) + goto submit_bio_retry; + + last_index = cur; + bypass = false; + } while (++cur < end); + + if (!bypass) + qtail[JQ_SUBMIT] = &pcl->next; + else + move_to_bypass_jobqueue(pcl, qtail, owned_head); + } while (owned_head != Z_EROFS_PCLUSTER_TAIL); + + if (bio) + submit_bio(bio); + + /* + * although background is preferred, no one is pending for submission. + * don't issue workqueue for decompression but drop it directly instead. + */ + if (!*force_fg && !nr_bios) { + kvfree(q[JQ_SUBMIT]); + return; + } + z_erofs_decompress_kickoff(q[JQ_SUBMIT], *force_fg, nr_bios); +} + +static void z_erofs_runqueue(struct super_block *sb, + struct z_erofs_decompress_frontend *f, + struct list_head *pagepool, bool force_fg) +{ + struct z_erofs_decompressqueue io[NR_JOBQUEUES]; + + if (f->clt.owned_head == Z_EROFS_PCLUSTER_TAIL) + return; + z_erofs_submit_queue(sb, f, pagepool, io, &force_fg); + + /* handle bypass queue (no i/o pclusters) immediately */ + z_erofs_decompress_queue(&io[JQ_BYPASS], pagepool); + + if (!force_fg) + return; + + /* wait until all bios are completed */ + io_wait_event(io[JQ_SUBMIT].u.wait, + !atomic_read(&io[JQ_SUBMIT].pending_bios)); + + /* handle synchronous decompress queue in the caller context */ + z_erofs_decompress_queue(&io[JQ_SUBMIT], pagepool); +} + +static int z_erofs_readpage(struct file *file, struct page *page) +{ + struct inode *const inode = page->mapping->host; + struct z_erofs_decompress_frontend f = DECOMPRESS_FRONTEND_INIT(inode); + int err; + LIST_HEAD(pagepool); + + trace_erofs_readpage(page, false); + + f.headoffset = (erofs_off_t)page->index << PAGE_SHIFT; + + err = z_erofs_do_read_page(&f, page); + (void)z_erofs_collector_end(&f.clt); + + /* if some compressed cluster ready, need submit them anyway */ + z_erofs_runqueue(inode->i_sb, &f, &pagepool, true); + + if (err) + erofs_err(inode->i_sb, "failed to read, err [%d]", err); + + if (f.map.mpage) + put_page(f.map.mpage); + + /* clean up the remaining free pages */ + put_pages_list(&pagepool); + return err; +} + +static int z_erofs_readpages(struct file *filp, struct address_space *mapping, + struct list_head *pages, unsigned int nr_pages) +{ + struct inode *const inode = mapping->host; + struct erofs_sb_info *const sbi = EROFS_I_SB(inode); + + bool sync = (nr_pages <= sbi->max_sync_decompress_pages); + struct z_erofs_decompress_frontend f = DECOMPRESS_FRONTEND_INIT(inode); + gfp_t gfp = mapping_gfp_constraint(mapping, GFP_KERNEL); + struct page *head = NULL; + LIST_HEAD(pagepool); + + trace_erofs_readpages(mapping->host, lru_to_page(pages), + nr_pages, false); + + f.headoffset = (erofs_off_t)lru_to_page(pages)->index << PAGE_SHIFT; + + for (; nr_pages; --nr_pages) { + struct page *page = lru_to_page(pages); + + prefetchw(&page->flags); + list_del(&page->lru); + + /* + * A pure asynchronous readahead is indicated if + * a PG_readahead marked page is hitted at first. + * Let's also do asynchronous decompression for this case. + */ + sync &= !(PageReadahead(page) && !head); + + if (add_to_page_cache_lru(page, mapping, page->index, gfp)) { + list_add(&page->lru, &pagepool); + continue; + } + + set_page_private(page, (unsigned long)head); + head = page; + } + + while (head) { + struct page *page = head; + int err; + + /* traversal in reverse order */ + head = (void *)page_private(page); + + err = z_erofs_do_read_page(&f, page); + if (err) + erofs_err(inode->i_sb, + "readahead error at page %lu @ nid %llu", + page->index, EROFS_I(inode)->nid); + put_page(page); + } + + (void)z_erofs_collector_end(&f.clt); + + z_erofs_runqueue(inode->i_sb, &f, &pagepool, sync); + + if (f.map.mpage) + put_page(f.map.mpage); + + /* clean up the remaining free pages */ + put_pages_list(&pagepool); + return 0; +} + +const struct address_space_operations z_erofs_aops = { + .readpage = z_erofs_readpage, + .readpages = z_erofs_readpages, +}; diff --git a/drivers/staging/erofs/zdata.h b/drivers/staging/erofs/zdata.h new file mode 100644 index 000000000000..68da309d5ad7 --- /dev/null +++ b/drivers/staging/erofs/zdata.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2018 HUAWEI, Inc. + * https://www.huawei.com/ + */ +#ifndef __EROFS_FS_ZDATA_H +#define __EROFS_FS_ZDATA_H + +#include "internal.h" +#include "zpvec.h" + +#define Z_EROFS_NR_INLINE_PAGEVECS 3 + +/* + * Structure fields follow one of the following exclusion rules. + * + * I: Modifiable by initialization/destruction paths and read-only + * for everyone else; + * + * L: Field should be protected by pageset lock; + * + * A: Field should be accessed / updated in atomic for parallelized code. + */ +struct z_erofs_collection { + struct mutex lock; + + /* I: page offset of start position of decompression */ + unsigned short pageofs; + + /* L: maximum relative page index in pagevec[] */ + unsigned short nr_pages; + + /* L: total number of pages in pagevec[] */ + unsigned int vcnt; + + union { + /* L: inline a certain number of pagevecs for bootstrap */ + erofs_vtptr_t pagevec[Z_EROFS_NR_INLINE_PAGEVECS]; + + /* I: can be used to free the pcluster by RCU. */ + struct rcu_head rcu; + }; +}; + +#define Z_EROFS_PCLUSTER_FULL_LENGTH 0x00000001 +#define Z_EROFS_PCLUSTER_LENGTH_BIT 1 + +/* + * let's leave a type here in case of introducing + * another tagged pointer later. + */ +typedef void *z_erofs_next_pcluster_t; + +struct z_erofs_pcluster { + struct erofs_workgroup obj; + struct z_erofs_collection primary_collection; + + /* A: point to next chained pcluster or TAILs */ + z_erofs_next_pcluster_t next; + + /* A: compressed pages (including multi-usage pages) */ + struct page *compressed_pages[Z_EROFS_CLUSTER_MAX_PAGES]; + + /* A: lower limit of decompressed length and if full length or not */ + unsigned int length; + + /* I: compression algorithm format */ + unsigned char algorithmformat; + /* I: bit shift of physical cluster size */ + unsigned char clusterbits; +}; + +#define z_erofs_primarycollection(pcluster) (&(pcluster)->primary_collection) + +/* let's avoid the valid 32-bit kernel addresses */ + +/* the chained workgroup has't submitted io (still open) */ +#define Z_EROFS_PCLUSTER_TAIL ((void *)0x5F0ECAFE) +/* the chained workgroup has already submitted io */ +#define Z_EROFS_PCLUSTER_TAIL_CLOSED ((void *)0x5F0EDEAD) + +#define Z_EROFS_PCLUSTER_NIL (NULL) + +#define Z_EROFS_WORKGROUP_SIZE sizeof(struct z_erofs_pcluster) + +struct z_erofs_decompressqueue { + struct super_block *sb; + atomic_t pending_bios; + z_erofs_next_pcluster_t head; + + union { + wait_queue_head_t wait; + struct work_struct work; + } u; +}; + +#define MNGD_MAPPING(sbi) ((sbi)->managed_cache->i_mapping) +static inline bool erofs_page_is_managed(const struct erofs_sb_info *sbi, + struct page *page) +{ + return page->mapping == MNGD_MAPPING(sbi); +} + +#define Z_EROFS_ONLINEPAGE_COUNT_BITS 2 +#define Z_EROFS_ONLINEPAGE_COUNT_MASK ((1 << Z_EROFS_ONLINEPAGE_COUNT_BITS) - 1) +#define Z_EROFS_ONLINEPAGE_INDEX_SHIFT (Z_EROFS_ONLINEPAGE_COUNT_BITS) + +/* + * waiters (aka. ongoing_packs): # to unlock the page + * sub-index: 0 - for partial page, >= 1 full page sub-index + */ +typedef atomic_t z_erofs_onlinepage_t; + +/* type punning */ +union z_erofs_onlinepage_converter { + z_erofs_onlinepage_t *o; + unsigned long *v; +}; + +static inline unsigned int z_erofs_onlinepage_index(struct page *page) +{ + union z_erofs_onlinepage_converter u; + + DBG_BUGON(!PagePrivate(page)); + u.v = &page_private(page); + + return atomic_read(u.o) >> Z_EROFS_ONLINEPAGE_INDEX_SHIFT; +} + +static inline void z_erofs_onlinepage_init(struct page *page) +{ + union { + z_erofs_onlinepage_t o; + unsigned long v; + /* keep from being unlocked in advance */ + } u = { .o = ATOMIC_INIT(1) }; + + set_page_private(page, u.v); + smp_wmb(); + SetPagePrivate(page); +} + +static inline void z_erofs_onlinepage_fixup(struct page *page, + uintptr_t index, bool down) +{ + union z_erofs_onlinepage_converter u = { .v = &page_private(page) }; + int orig, orig_index, val; + +repeat: + orig = atomic_read(u.o); + orig_index = orig >> Z_EROFS_ONLINEPAGE_INDEX_SHIFT; + if (orig_index) { + if (!index) + return; + + DBG_BUGON(orig_index != index); + } + + val = (index << Z_EROFS_ONLINEPAGE_INDEX_SHIFT) | + ((orig & Z_EROFS_ONLINEPAGE_COUNT_MASK) + (unsigned int)down); + if (atomic_cmpxchg(u.o, orig, val) != orig) + goto repeat; +} + +static inline void z_erofs_onlinepage_endio(struct page *page) +{ + union z_erofs_onlinepage_converter u; + unsigned int v; + + DBG_BUGON(!PagePrivate(page)); + u.v = &page_private(page); + + v = atomic_dec_return(u.o); + if (!(v & Z_EROFS_ONLINEPAGE_COUNT_MASK)) { + ClearPagePrivate(page); + if (!PageError(page)) + SetPageUptodate(page); + unlock_page(page); + } + erofs_dbg("%s, page %p value %x", __func__, page, atomic_read(u.o)); +} + +#define Z_EROFS_VMAP_ONSTACK_PAGES \ + min_t(unsigned int, THREAD_SIZE / 8 / sizeof(struct page *), 96U) +#define Z_EROFS_VMAP_GLOBAL_PAGES 2048 + +#endif + diff --git a/drivers/staging/erofs/zmap.c b/drivers/staging/erofs/zmap.c new file mode 100644 index 000000000000..a13f69cf4026 --- /dev/null +++ b/drivers/staging/erofs/zmap.c @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2018-2019 HUAWEI, Inc. + * https://www.huawei.com/ + */ +#include "internal.h" +#include +#include + +int z_erofs_fill_inode(struct inode *inode) +{ + struct erofs_inode *const vi = EROFS_I(inode); + + if (vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY) { + vi->z_advise = 0; + vi->z_algorithmtype[0] = 0; + vi->z_algorithmtype[1] = 0; + vi->z_logical_clusterbits = LOG_BLOCK_SIZE; + vi->z_physical_clusterbits[0] = vi->z_logical_clusterbits; + vi->z_physical_clusterbits[1] = vi->z_logical_clusterbits; + set_bit(EROFS_I_Z_INITED_BIT, &vi->flags); + } + + inode->i_mapping->a_ops = &z_erofs_aops; + return 0; +} + +static int z_erofs_fill_inode_lazy(struct inode *inode) +{ + struct erofs_inode *const vi = EROFS_I(inode); + struct super_block *const sb = inode->i_sb; + int err; + erofs_off_t pos; + struct page *page; + void *kaddr; + struct z_erofs_map_header *h; + + if (test_bit(EROFS_I_Z_INITED_BIT, &vi->flags)) { + /* + * paired with smp_mb() at the end of the function to ensure + * fields will only be observed after the bit is set. + */ + smp_mb(); + return 0; + } + + if (wait_on_bit_lock(&vi->flags, EROFS_I_BL_Z_BIT, TASK_KILLABLE)) + return -ERESTARTSYS; + + err = 0; + if (test_bit(EROFS_I_Z_INITED_BIT, &vi->flags)) + goto out_unlock; + + DBG_BUGON(vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY); + + pos = ALIGN(iloc(EROFS_SB(sb), vi->nid) + vi->inode_isize + + vi->xattr_isize, 8); + page = erofs_get_meta_page(sb, erofs_blknr(pos)); + if (IS_ERR(page)) { + err = PTR_ERR(page); + goto out_unlock; + } + + kaddr = kmap_atomic(page); + + h = kaddr + erofs_blkoff(pos); + vi->z_advise = le16_to_cpu(h->h_advise); + vi->z_algorithmtype[0] = h->h_algorithmtype & 15; + vi->z_algorithmtype[1] = h->h_algorithmtype >> 4; + + if (vi->z_algorithmtype[0] >= Z_EROFS_COMPRESSION_MAX) { + erofs_err(sb, "unknown compression format %u for nid %llu, please upgrade kernel", + vi->z_algorithmtype[0], vi->nid); + err = -EOPNOTSUPP; + goto unmap_done; + } + + vi->z_logical_clusterbits = LOG_BLOCK_SIZE + (h->h_clusterbits & 7); + vi->z_physical_clusterbits[0] = vi->z_logical_clusterbits + + ((h->h_clusterbits >> 3) & 3); + + if (vi->z_physical_clusterbits[0] != LOG_BLOCK_SIZE) { + erofs_err(sb, "unsupported physical clusterbits %u for nid %llu, please upgrade kernel", + vi->z_physical_clusterbits[0], vi->nid); + err = -EOPNOTSUPP; + goto unmap_done; + } + + vi->z_physical_clusterbits[1] = vi->z_logical_clusterbits + + ((h->h_clusterbits >> 5) & 7); + /* paired with smp_mb() at the beginning of the function */ + smp_mb(); + set_bit(EROFS_I_Z_INITED_BIT, &vi->flags); +unmap_done: + kunmap_atomic(kaddr); + unlock_page(page); + put_page(page); +out_unlock: + clear_and_wake_up_bit(EROFS_I_BL_Z_BIT, &vi->flags); + return err; +} + +struct z_erofs_maprecorder { + struct inode *inode; + struct erofs_map_blocks *map; + void *kaddr; + + unsigned long lcn; + /* compression extent information gathered */ + u8 type; + u16 clusterofs; + u16 delta[2]; + erofs_blk_t pblk; +}; + +static int z_erofs_reload_indexes(struct z_erofs_maprecorder *m, + erofs_blk_t eblk) +{ + struct super_block *const sb = m->inode->i_sb; + struct erofs_map_blocks *const map = m->map; + struct page *mpage = map->mpage; + + if (mpage) { + if (mpage->index == eblk) { + if (!m->kaddr) + m->kaddr = kmap_atomic(mpage); + return 0; + } + + if (m->kaddr) { + kunmap_atomic(m->kaddr); + m->kaddr = NULL; + } + put_page(mpage); + } + + mpage = erofs_get_meta_page(sb, eblk); + if (IS_ERR(mpage)) { + map->mpage = NULL; + return PTR_ERR(mpage); + } + m->kaddr = kmap_atomic(mpage); + unlock_page(mpage); + map->mpage = mpage; + return 0; +} + +static int legacy_load_cluster_from_disk(struct z_erofs_maprecorder *m, + unsigned long lcn) +{ + struct inode *const inode = m->inode; + struct erofs_inode *const vi = EROFS_I(inode); + const erofs_off_t ibase = iloc(EROFS_I_SB(inode), vi->nid); + const erofs_off_t pos = + Z_EROFS_VLE_LEGACY_INDEX_ALIGN(ibase + vi->inode_isize + + vi->xattr_isize) + + lcn * sizeof(struct z_erofs_vle_decompressed_index); + struct z_erofs_vle_decompressed_index *di; + unsigned int advise, type; + int err; + + err = z_erofs_reload_indexes(m, erofs_blknr(pos)); + if (err) + return err; + + m->lcn = lcn; + di = m->kaddr + erofs_blkoff(pos); + + advise = le16_to_cpu(di->di_advise); + type = (advise >> Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT) & + ((1 << Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) - 1); + switch (type) { + case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: + m->clusterofs = 1 << vi->z_logical_clusterbits; + m->delta[0] = le16_to_cpu(di->di_u.delta[0]); + m->delta[1] = le16_to_cpu(di->di_u.delta[1]); + break; + case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: + case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: + m->clusterofs = le16_to_cpu(di->di_clusterofs); + m->pblk = le32_to_cpu(di->di_u.blkaddr); + break; + default: + DBG_BUGON(1); + return -EOPNOTSUPP; + } + m->type = type; + return 0; +} + +static unsigned int decode_compactedbits(unsigned int lobits, + unsigned int lomask, + u8 *in, unsigned int pos, u8 *type) +{ + const unsigned int v = get_unaligned_le32(in + pos / 8) >> (pos & 7); + const unsigned int lo = v & lomask; + + *type = (v >> lobits) & 3; + return lo; +} + +static int unpack_compacted_index(struct z_erofs_maprecorder *m, + unsigned int amortizedshift, + unsigned int eofs) +{ + struct erofs_inode *const vi = EROFS_I(m->inode); + const unsigned int lclusterbits = vi->z_logical_clusterbits; + const unsigned int lomask = (1 << lclusterbits) - 1; + unsigned int vcnt, base, lo, encodebits, nblk; + int i; + u8 *in, type; + + if (1 << amortizedshift == 4) + vcnt = 2; + else if (1 << amortizedshift == 2 && lclusterbits == 12) + vcnt = 16; + else + return -EOPNOTSUPP; + + encodebits = ((vcnt << amortizedshift) - sizeof(__le32)) * 8 / vcnt; + base = round_down(eofs, vcnt << amortizedshift); + in = m->kaddr + base; + + i = (eofs - base) >> amortizedshift; + + lo = decode_compactedbits(lclusterbits, lomask, + in, encodebits * i, &type); + m->type = type; + if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) { + m->clusterofs = 1 << lclusterbits; + if (i + 1 != vcnt) { + m->delta[0] = lo; + return 0; + } + /* + * since the last lcluster in the pack is special, + * of which lo saves delta[1] rather than delta[0]. + * Hence, get delta[0] by the previous lcluster indirectly. + */ + lo = decode_compactedbits(lclusterbits, lomask, + in, encodebits * (i - 1), &type); + if (type != Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) + lo = 0; + m->delta[0] = lo + 1; + return 0; + } + m->clusterofs = lo; + m->delta[0] = 0; + /* figout out blkaddr (pblk) for HEAD lclusters */ + nblk = 1; + while (i > 0) { + --i; + lo = decode_compactedbits(lclusterbits, lomask, + in, encodebits * i, &type); + if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) + i -= lo; + + if (i >= 0) + ++nblk; + } + in += (vcnt << amortizedshift) - sizeof(__le32); + m->pblk = le32_to_cpu(*(__le32 *)in) + nblk; + return 0; +} + +static int compacted_load_cluster_from_disk(struct z_erofs_maprecorder *m, + unsigned long lcn) +{ + struct inode *const inode = m->inode; + struct erofs_inode *const vi = EROFS_I(inode); + const unsigned int lclusterbits = vi->z_logical_clusterbits; + const erofs_off_t ebase = ALIGN(iloc(EROFS_I_SB(inode), vi->nid) + + vi->inode_isize + vi->xattr_isize, 8) + + sizeof(struct z_erofs_map_header); + const unsigned int totalidx = DIV_ROUND_UP(inode->i_size, EROFS_BLKSIZ); + unsigned int compacted_4b_initial, compacted_2b; + unsigned int amortizedshift; + erofs_off_t pos; + int err; + + if (lclusterbits != 12) + return -EOPNOTSUPP; + + if (lcn >= totalidx) + return -EINVAL; + + m->lcn = lcn; + /* used to align to 32-byte (compacted_2b) alignment */ + compacted_4b_initial = (32 - ebase % 32) / 4; + if (compacted_4b_initial == 32 / 4) + compacted_4b_initial = 0; + + if (vi->z_advise & Z_EROFS_ADVISE_COMPACTED_2B) + compacted_2b = rounddown(totalidx - compacted_4b_initial, 16); + else + compacted_2b = 0; + + pos = ebase; + if (lcn < compacted_4b_initial) { + amortizedshift = 2; + goto out; + } + pos += compacted_4b_initial * 4; + lcn -= compacted_4b_initial; + + if (lcn < compacted_2b) { + amortizedshift = 1; + goto out; + } + pos += compacted_2b * 2; + lcn -= compacted_2b; + amortizedshift = 2; +out: + pos += lcn * (1 << amortizedshift); + err = z_erofs_reload_indexes(m, erofs_blknr(pos)); + if (err) + return err; + return unpack_compacted_index(m, amortizedshift, erofs_blkoff(pos)); +} + +static int z_erofs_load_cluster_from_disk(struct z_erofs_maprecorder *m, + unsigned int lcn) +{ + const unsigned int datamode = EROFS_I(m->inode)->datalayout; + + if (datamode == EROFS_INODE_FLAT_COMPRESSION_LEGACY) + return legacy_load_cluster_from_disk(m, lcn); + + if (datamode == EROFS_INODE_FLAT_COMPRESSION) + return compacted_load_cluster_from_disk(m, lcn); + + return -EINVAL; +} + +static int z_erofs_extent_lookback(struct z_erofs_maprecorder *m, + unsigned int lookback_distance) +{ + struct erofs_inode *const vi = EROFS_I(m->inode); + struct erofs_map_blocks *const map = m->map; + const unsigned int lclusterbits = vi->z_logical_clusterbits; + unsigned long lcn = m->lcn; + int err; + + if (lcn < lookback_distance) { + erofs_err(m->inode->i_sb, + "bogus lookback distance @ nid %llu", vi->nid); + DBG_BUGON(1); + return -EFSCORRUPTED; + } + + /* load extent head logical cluster if needed */ + lcn -= lookback_distance; + err = z_erofs_load_cluster_from_disk(m, lcn); + if (err) + return err; + + switch (m->type) { + case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: + if (!m->delta[0]) { + erofs_err(m->inode->i_sb, + "invalid lookback distance 0 @ nid %llu", + vi->nid); + DBG_BUGON(1); + return -EFSCORRUPTED; + } + return z_erofs_extent_lookback(m, m->delta[0]); + case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: + map->m_flags &= ~EROFS_MAP_ZIPPED; + /* fallthrough */ + case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: + map->m_la = (lcn << lclusterbits) | m->clusterofs; + break; + default: + erofs_err(m->inode->i_sb, + "unknown type %u @ lcn %lu of nid %llu", + m->type, lcn, vi->nid); + DBG_BUGON(1); + return -EOPNOTSUPP; + } + return 0; +} + +int z_erofs_map_blocks_iter(struct inode *inode, + struct erofs_map_blocks *map, + int flags) +{ + struct erofs_inode *const vi = EROFS_I(inode); + struct z_erofs_maprecorder m = { + .inode = inode, + .map = map, + }; + int err = 0; + unsigned int lclusterbits, endoff; + unsigned long long ofs, end; + + trace_z_erofs_map_blocks_iter_enter(inode, map, flags); + + /* when trying to read beyond EOF, leave it unmapped */ + if (map->m_la >= inode->i_size) { + map->m_llen = map->m_la + 1 - inode->i_size; + map->m_la = inode->i_size; + map->m_flags = 0; + goto out; + } + + err = z_erofs_fill_inode_lazy(inode); + if (err) + goto out; + + lclusterbits = vi->z_logical_clusterbits; + ofs = map->m_la; + m.lcn = ofs >> lclusterbits; + endoff = ofs & ((1 << lclusterbits) - 1); + + err = z_erofs_load_cluster_from_disk(&m, m.lcn); + if (err) + goto unmap_out; + + map->m_flags = EROFS_MAP_ZIPPED; /* by default, compressed */ + end = (m.lcn + 1ULL) << lclusterbits; + + switch (m.type) { + case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: + if (endoff >= m.clusterofs) + map->m_flags &= ~EROFS_MAP_ZIPPED; + /* fallthrough */ + case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: + if (endoff >= m.clusterofs) { + map->m_la = (m.lcn << lclusterbits) | m.clusterofs; + break; + } + /* m.lcn should be >= 1 if endoff < m.clusterofs */ + if (!m.lcn) { + erofs_err(inode->i_sb, + "invalid logical cluster 0 at nid %llu", + vi->nid); + err = -EFSCORRUPTED; + goto unmap_out; + } + end = (m.lcn << lclusterbits) | m.clusterofs; + map->m_flags |= EROFS_MAP_FULL_MAPPED; + m.delta[0] = 1; + /* fallthrough */ + case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: + /* get the correspoinding first chunk */ + err = z_erofs_extent_lookback(&m, m.delta[0]); + if (err) + goto unmap_out; + break; + default: + erofs_err(inode->i_sb, + "unknown type %u @ offset %llu of nid %llu", + m.type, ofs, vi->nid); + err = -EOPNOTSUPP; + goto unmap_out; + } + + map->m_llen = end - map->m_la; + map->m_plen = 1 << lclusterbits; + map->m_pa = blknr_to_addr(m.pblk); + map->m_flags |= EROFS_MAP_MAPPED; + +unmap_out: + if (m.kaddr) + kunmap_atomic(m.kaddr); + +out: + erofs_dbg("%s, m_la %llu m_pa %llu m_llen %llu m_plen %llu m_flags 0%o", + __func__, map->m_la, map->m_pa, + map->m_llen, map->m_plen, map->m_flags); + + trace_z_erofs_map_blocks_iter_exit(inode, map, flags, err); + + /* aggressively BUG_ON iff CONFIG_EROFS_FS_DEBUG is on */ + DBG_BUGON(err < 0 && err != -ENOMEM); + return err; +} diff --git a/drivers/staging/erofs/unzip_pagevec.h b/drivers/staging/erofs/zpvec.h similarity index 67% rename from drivers/staging/erofs/unzip_pagevec.h rename to drivers/staging/erofs/zpvec.h index 23856ba2742d..bfc12ecbbe83 100644 --- a/drivers/staging/erofs/unzip_pagevec.h +++ b/drivers/staging/erofs/zpvec.h @@ -1,21 +1,14 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * linux/drivers/staging/erofs/unzip_pagevec.h - * +/* SPDX-License-Identifier: GPL-2.0-only */ +/* * Copyright (C) 2018 HUAWEI, Inc. - * http://www.huawei.com/ - * Created by Gao Xiang - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of the Linux - * distribution for more details. + * https://www.huawei.com/ */ -#ifndef __EROFS_UNZIP_PAGEVEC_H -#define __EROFS_UNZIP_PAGEVEC_H +#ifndef __EROFS_FS_ZPVEC_H +#define __EROFS_FS_ZPVEC_H -#include +#include "tagptr.h" -/* page type in pagevec for unzip subsystem */ +/* page type in pagevec for decompress subsystem */ enum z_erofs_page_type { /* including Z_EROFS_VLE_PAGE_TAIL_EXCLUSIVE */ Z_EROFS_PAGE_TYPE_EXCLUSIVE, @@ -43,7 +36,7 @@ struct z_erofs_pagevec_ctor { static inline void z_erofs_pagevec_ctor_exit(struct z_erofs_pagevec_ctor *ctor, bool atomic) { - if (ctor->curr == NULL) + if (!ctor->curr) return; if (atomic) @@ -54,25 +47,22 @@ static inline void z_erofs_pagevec_ctor_exit(struct z_erofs_pagevec_ctor *ctor, static inline struct page * z_erofs_pagevec_ctor_next_page(struct z_erofs_pagevec_ctor *ctor, - unsigned nr) + unsigned int nr) { - unsigned index; + unsigned int index; /* keep away from occupied pages */ - if (ctor->next != NULL) + if (ctor->next) return ctor->next; for (index = 0; index < nr; ++index) { const erofs_vtptr_t t = ctor->pages[index]; - const unsigned tags = tagptr_unfold_tags(t); + const unsigned int tags = tagptr_unfold_tags(t); if (tags == Z_EROFS_PAGE_TYPE_EXCLUSIVE) return tagptr_unfold_ptr(t); } - - if (unlikely(nr >= ctor->nr)) - BUG(); - + DBG_BUGON(nr >= ctor->nr); return NULL; } @@ -94,8 +84,9 @@ z_erofs_pagevec_ctor_pagedown(struct z_erofs_pagevec_ctor *ctor, } static inline void z_erofs_pagevec_ctor_init(struct z_erofs_pagevec_ctor *ctor, - unsigned nr, - erofs_vtptr_t *pages, unsigned i) + unsigned int nr, + erofs_vtptr_t *pages, + unsigned int i) { ctor->nr = nr; ctor->curr = ctor->next = NULL; @@ -109,23 +100,21 @@ static inline void z_erofs_pagevec_ctor_init(struct z_erofs_pagevec_ctor *ctor, z_erofs_pagevec_ctor_pagedown(ctor, false); } } - ctor->next = z_erofs_pagevec_ctor_next_page(ctor, i); ctor->index = i; } -static inline bool -z_erofs_pagevec_ctor_enqueue(struct z_erofs_pagevec_ctor *ctor, - struct page *page, - enum z_erofs_page_type type, - bool *occupied) +static inline bool z_erofs_pagevec_enqueue(struct z_erofs_pagevec_ctor *ctor, + struct page *page, + enum z_erofs_page_type type, + bool *occupied) { *occupied = false; - if (unlikely(ctor->next == NULL && type)) + if (!ctor->next && type) if (ctor->index + 1 == ctor->nr) return false; - if (unlikely(ctor->index >= ctor->nr)) + if (ctor->index >= ctor->nr) z_erofs_pagevec_ctor_pagedown(ctor, false); /* exclusive page type must be 0 */ @@ -137,19 +126,17 @@ z_erofs_pagevec_ctor_enqueue(struct z_erofs_pagevec_ctor *ctor, ctor->next = page; *occupied = true; } - - ctor->pages[ctor->index++] = - tagptr_fold(erofs_vtptr_t, page, type); + ctor->pages[ctor->index++] = tagptr_fold(erofs_vtptr_t, page, type); return true; } static inline struct page * -z_erofs_pagevec_ctor_dequeue(struct z_erofs_pagevec_ctor *ctor, - enum z_erofs_page_type *type) +z_erofs_pagevec_dequeue(struct z_erofs_pagevec_ctor *ctor, + enum z_erofs_page_type *type) { erofs_vtptr_t t; - if (unlikely(ctor->index >= ctor->nr)) { + if (ctor->index >= ctor->nr) { DBG_BUGON(!ctor->next); z_erofs_pagevec_ctor_pagedown(ctor, true); } @@ -162,11 +149,7 @@ z_erofs_pagevec_ctor_dequeue(struct z_erofs_pagevec_ctor *ctor, if (*type == (uintptr_t)ctor->next) ctor->next = tagptr_unfold_ptr(t); - ctor->pages[ctor->index++] = - tagptr_fold(erofs_vtptr_t, NULL, 0); - + ctor->pages[ctor->index++] = tagptr_fold(erofs_vtptr_t, NULL, 0); return tagptr_unfold_ptr(t); } - #endif - diff --git a/drivers/staging/erofs/include/trace/events/erofs.h b/include/trace/events/erofs.h similarity index 85% rename from drivers/staging/erofs/include/trace/events/erofs.h rename to include/trace/events/erofs.h index 5aead93a762f..27f5caa6299a 100644 --- a/drivers/staging/erofs/include/trace/events/erofs.h +++ b/include/trace/events/erofs.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ #undef TRACE_SYSTEM #define TRACE_SYSTEM erofs @@ -6,6 +6,9 @@ #define _TRACE_EROFS_H #include +#include + +struct erofs_map_blocks; #define show_dev(dev) MAJOR(dev), MINOR(dev) #define show_dev_nid(entry) show_dev(entry->dev), entry->nid @@ -38,7 +41,7 @@ TRACE_EVENT(erofs_lookup, TP_fast_assign( __entry->dev = dir->i_sb->s_dev; - __entry->nid = EROFS_V(dir)->nid; + __entry->nid = EROFS_I(dir)->nid; __entry->name = dentry->d_name.name; __entry->flags = flags; ), @@ -63,7 +66,7 @@ TRACE_EVENT(erofs_fill_inode, TP_fast_assign( __entry->dev = inode->i_sb->s_dev; - __entry->nid = EROFS_V(inode)->nid; + __entry->nid = EROFS_I(inode)->nid; __entry->blkaddr = erofs_blknr(iloc(EROFS_I_SB(inode), __entry->nid)); __entry->ofs = erofs_blkoff(iloc(EROFS_I_SB(inode), __entry->nid)); __entry->isdir = isdir; @@ -92,7 +95,7 @@ TRACE_EVENT(erofs_readpage, TP_fast_assign( __entry->dev = page->mapping->host->i_sb->s_dev; - __entry->nid = EROFS_V(page->mapping->host)->nid; + __entry->nid = EROFS_I(page->mapping->host)->nid; __entry->dir = S_ISDIR(page->mapping->host->i_mode); __entry->index = page->index; __entry->uptodate = PageUptodate(page); @@ -125,7 +128,7 @@ TRACE_EVENT(erofs_readpages, TP_fast_assign( __entry->dev = inode->i_sb->s_dev; - __entry->nid = EROFS_V(inode)->nid; + __entry->nid = EROFS_I(inode)->nid; __entry->start = page->index; __entry->nrpage = nrpage; __entry->raw = raw; @@ -154,7 +157,7 @@ DECLARE_EVENT_CLASS(erofs__map_blocks_enter, TP_fast_assign( __entry->dev = inode->i_sb->s_dev; - __entry->nid = EROFS_V(inode)->nid; + __entry->nid = EROFS_I(inode)->nid; __entry->la = map->m_la; __entry->llen = map->m_llen; __entry->flags = flags; @@ -162,7 +165,8 @@ DECLARE_EVENT_CLASS(erofs__map_blocks_enter, TP_printk("dev = (%d,%d), nid = %llu, la %llu llen %llu flags %s", show_dev_nid(__entry), - __entry->la, __entry->llen, show_map_flags(__entry->flags)) + __entry->la, __entry->llen, + __entry->flags ? show_map_flags(__entry->flags) : "NULL") ); DEFINE_EVENT(erofs__map_blocks_enter, erofs_map_blocks_flatmode_enter, @@ -172,6 +176,13 @@ DEFINE_EVENT(erofs__map_blocks_enter, erofs_map_blocks_flatmode_enter, TP_ARGS(inode, map, flags) ); +DEFINE_EVENT(erofs__map_blocks_enter, z_erofs_map_blocks_iter_enter, + TP_PROTO(struct inode *inode, struct erofs_map_blocks *map, + unsigned int flags), + + TP_ARGS(inode, map, flags) +); + DECLARE_EVENT_CLASS(erofs__map_blocks_exit, TP_PROTO(struct inode *inode, struct erofs_map_blocks *map, unsigned int flags, int ret), @@ -192,7 +203,7 @@ DECLARE_EVENT_CLASS(erofs__map_blocks_exit, TP_fast_assign( __entry->dev = inode->i_sb->s_dev; - __entry->nid = EROFS_V(inode)->nid; + __entry->nid = EROFS_I(inode)->nid; __entry->flags = flags; __entry->la = map->m_la; __entry->pa = map->m_pa; @@ -204,7 +215,8 @@ DECLARE_EVENT_CLASS(erofs__map_blocks_exit, TP_printk("dev = (%d,%d), nid = %llu, flags %s " "la %llu pa %llu llen %llu plen %llu mflags %s ret %d", - show_dev_nid(__entry), show_map_flags(__entry->flags), + show_dev_nid(__entry), + __entry->flags ? show_map_flags(__entry->flags) : "NULL", __entry->la, __entry->pa, __entry->llen, __entry->plen, show_mflags(__entry->mflags), __entry->ret) ); @@ -216,6 +228,13 @@ DEFINE_EVENT(erofs__map_blocks_exit, erofs_map_blocks_flatmode_exit, TP_ARGS(inode, map, flags, ret) ); +DEFINE_EVENT(erofs__map_blocks_exit, z_erofs_map_blocks_iter_exit, + TP_PROTO(struct inode *inode, struct erofs_map_blocks *map, + unsigned int flags, int ret), + + TP_ARGS(inode, map, flags, ret) +); + TRACE_EVENT(erofs_destroy_inode, TP_PROTO(struct inode *inode), @@ -228,7 +247,7 @@ TRACE_EVENT(erofs_destroy_inode, TP_fast_assign( __entry->dev = inode->i_sb->s_dev; - __entry->nid = EROFS_V(inode)->nid; + __entry->nid = EROFS_I(inode)->nid; ), TP_printk("dev = (%d,%d), nid = %llu", show_dev_nid(__entry)) From e6ac4b0ae8bd6f7042e15a2496c1274149dd1e05 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Mon, 30 Aug 2021 11:44:53 +0800 Subject: [PATCH 05/74] erofs: move from drivers/staging/ to fs/ Since 5.4, erofs has been moved into fs/. Signed-off-by: Gao Xiang --- drivers/staging/Kconfig | 2 -- drivers/staging/Makefile | 1 - fs/Kconfig | 1 + fs/Makefile | 1 + {drivers/staging => fs}/erofs/Kconfig | 0 {drivers/staging => fs}/erofs/Makefile | 0 {drivers/staging => fs}/erofs/TODO | 0 {drivers/staging => fs}/erofs/compress.h | 0 {drivers/staging => fs}/erofs/data.c | 0 {drivers/staging => fs}/erofs/decompressor.c | 0 {drivers/staging => fs}/erofs/dir.c | 0 {drivers/staging => fs}/erofs/erofs_fs.h | 0 {drivers/staging => fs}/erofs/inode.c | 0 {drivers/staging => fs}/erofs/internal.h | 0 {drivers/staging => fs}/erofs/namei.c | 0 {drivers/staging => fs}/erofs/super.c | 0 {drivers/staging => fs}/erofs/tagptr.h | 0 {drivers/staging => fs}/erofs/utils.c | 0 {drivers/staging => fs}/erofs/xattr.c | 0 {drivers/staging => fs}/erofs/xattr.h | 0 {drivers/staging => fs}/erofs/zdata.c | 0 {drivers/staging => fs}/erofs/zdata.h | 0 {drivers/staging => fs}/erofs/zmap.c | 0 {drivers/staging => fs}/erofs/zpvec.h | 0 24 files changed, 2 insertions(+), 3 deletions(-) rename {drivers/staging => fs}/erofs/Kconfig (100%) rename {drivers/staging => fs}/erofs/Makefile (100%) rename {drivers/staging => fs}/erofs/TODO (100%) rename {drivers/staging => fs}/erofs/compress.h (100%) rename {drivers/staging => fs}/erofs/data.c (100%) rename {drivers/staging => fs}/erofs/decompressor.c (100%) rename {drivers/staging => fs}/erofs/dir.c (100%) rename {drivers/staging => fs}/erofs/erofs_fs.h (100%) rename {drivers/staging => fs}/erofs/inode.c (100%) rename {drivers/staging => fs}/erofs/internal.h (100%) rename {drivers/staging => fs}/erofs/namei.c (100%) rename {drivers/staging => fs}/erofs/super.c (100%) rename {drivers/staging => fs}/erofs/tagptr.h (100%) rename {drivers/staging => fs}/erofs/utils.c (100%) rename {drivers/staging => fs}/erofs/xattr.c (100%) rename {drivers/staging => fs}/erofs/xattr.h (100%) rename {drivers/staging => fs}/erofs/zdata.c (100%) rename {drivers/staging => fs}/erofs/zdata.h (100%) rename {drivers/staging => fs}/erofs/zmap.c (100%) rename {drivers/staging => fs}/erofs/zpvec.h (100%) diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 58e8140c1f57..2705c72515c5 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -122,6 +122,4 @@ source "drivers/staging/gasket/Kconfig" source "drivers/staging/axis-fifo/Kconfig" -source "drivers/staging/erofs/Kconfig" - endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 6f3065569fa0..cac453fcd774 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -51,4 +51,3 @@ obj-$(CONFIG_SOC_MT7621) += mt7621-eth/ obj-$(CONFIG_SOC_MT7621) += mt7621-dts/ obj-$(CONFIG_STAGING_GASKET_FRAMEWORK) += gasket/ obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ -obj-$(CONFIG_EROFS_FS) += erofs/ diff --git a/fs/Kconfig b/fs/Kconfig index ac474a61be37..d9e20290da75 100644 --- a/fs/Kconfig +++ b/fs/Kconfig @@ -255,6 +255,7 @@ source "fs/pstore/Kconfig" source "fs/sysv/Kconfig" source "fs/ufs/Kconfig" source "fs/exofs/Kconfig" +source "fs/erofs/Kconfig" endif # MISC_FILESYSTEMS diff --git a/fs/Makefile b/fs/Makefile index 293733f61594..0f6bad3ac103 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -128,3 +128,4 @@ obj-y += exofs/ # Multiple modules obj-$(CONFIG_CEPH_FS) += ceph/ obj-$(CONFIG_PSTORE) += pstore/ obj-$(CONFIG_EFIVAR_FS) += efivarfs/ +obj-$(CONFIG_EROFS_FS) += erofs/ diff --git a/drivers/staging/erofs/Kconfig b/fs/erofs/Kconfig similarity index 100% rename from drivers/staging/erofs/Kconfig rename to fs/erofs/Kconfig diff --git a/drivers/staging/erofs/Makefile b/fs/erofs/Makefile similarity index 100% rename from drivers/staging/erofs/Makefile rename to fs/erofs/Makefile diff --git a/drivers/staging/erofs/TODO b/fs/erofs/TODO similarity index 100% rename from drivers/staging/erofs/TODO rename to fs/erofs/TODO diff --git a/drivers/staging/erofs/compress.h b/fs/erofs/compress.h similarity index 100% rename from drivers/staging/erofs/compress.h rename to fs/erofs/compress.h diff --git a/drivers/staging/erofs/data.c b/fs/erofs/data.c similarity index 100% rename from drivers/staging/erofs/data.c rename to fs/erofs/data.c diff --git a/drivers/staging/erofs/decompressor.c b/fs/erofs/decompressor.c similarity index 100% rename from drivers/staging/erofs/decompressor.c rename to fs/erofs/decompressor.c diff --git a/drivers/staging/erofs/dir.c b/fs/erofs/dir.c similarity index 100% rename from drivers/staging/erofs/dir.c rename to fs/erofs/dir.c diff --git a/drivers/staging/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h similarity index 100% rename from drivers/staging/erofs/erofs_fs.h rename to fs/erofs/erofs_fs.h diff --git a/drivers/staging/erofs/inode.c b/fs/erofs/inode.c similarity index 100% rename from drivers/staging/erofs/inode.c rename to fs/erofs/inode.c diff --git a/drivers/staging/erofs/internal.h b/fs/erofs/internal.h similarity index 100% rename from drivers/staging/erofs/internal.h rename to fs/erofs/internal.h diff --git a/drivers/staging/erofs/namei.c b/fs/erofs/namei.c similarity index 100% rename from drivers/staging/erofs/namei.c rename to fs/erofs/namei.c diff --git a/drivers/staging/erofs/super.c b/fs/erofs/super.c similarity index 100% rename from drivers/staging/erofs/super.c rename to fs/erofs/super.c diff --git a/drivers/staging/erofs/tagptr.h b/fs/erofs/tagptr.h similarity index 100% rename from drivers/staging/erofs/tagptr.h rename to fs/erofs/tagptr.h diff --git a/drivers/staging/erofs/utils.c b/fs/erofs/utils.c similarity index 100% rename from drivers/staging/erofs/utils.c rename to fs/erofs/utils.c diff --git a/drivers/staging/erofs/xattr.c b/fs/erofs/xattr.c similarity index 100% rename from drivers/staging/erofs/xattr.c rename to fs/erofs/xattr.c diff --git a/drivers/staging/erofs/xattr.h b/fs/erofs/xattr.h similarity index 100% rename from drivers/staging/erofs/xattr.h rename to fs/erofs/xattr.h diff --git a/drivers/staging/erofs/zdata.c b/fs/erofs/zdata.c similarity index 100% rename from drivers/staging/erofs/zdata.c rename to fs/erofs/zdata.c diff --git a/drivers/staging/erofs/zdata.h b/fs/erofs/zdata.h similarity index 100% rename from drivers/staging/erofs/zdata.h rename to fs/erofs/zdata.h diff --git a/drivers/staging/erofs/zmap.c b/fs/erofs/zmap.c similarity index 100% rename from drivers/staging/erofs/zmap.c rename to fs/erofs/zmap.c diff --git a/drivers/staging/erofs/zpvec.h b/fs/erofs/zpvec.h similarity index 100% rename from drivers/staging/erofs/zpvec.h rename to fs/erofs/zpvec.h From d4cd715771c3f919dc9089bbcca12d82774b2f97 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Mon, 25 Oct 2021 15:43:11 +0800 Subject: [PATCH 06/74] erofs: don't trigger WARN() when decompression fails [ Upstream commit a0961f351d82d43ab0b845304caa235dfe249ae9 ] syzbot reported a WARNING [1] due to corrupted compressed data. As Dmitry said, "If this is not a kernel bug, then the code should not use WARN. WARN if for kernel bugs and is recognized as such by all testing systems and humans." [1] https://lore.kernel.org/r/000000000000b3586105cf0ff45e@google.com Link: https://lore.kernel.org/r/20211025074311.130395-1-hsiangkao@linux.alibaba.com Cc: Dmitry Vyukov Reviewed-by: Chao Yu Reported-by: syzbot+d8aaffc3719597e8cfb4@syzkaller.appspotmail.com Signed-off-by: Gao Xiang Signed-off-by: Sasha Levin --- fs/erofs/decompressor.c | 1 - 1 file changed, 1 deletion(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 7822ab4a8262..1893910f489a 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -169,7 +169,6 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) erofs_err(rq->sb, "failed to decompress %d in[%u, %u] out[%u]", ret, inlen, inputmargin, rq->outputsize); - WARN_ON(1); print_hex_dump(KERN_DEBUG, "[ in]: ", DUMP_PREFIX_OFFSET, 16, 1, src + inputmargin, inlen, true); print_hex_dump(KERN_DEBUG, "[out]: ", DUMP_PREFIX_OFFSET, From b0429df102fbfdf220a929aa73caafe3e449f14d Mon Sep 17 00:00:00 2001 From: Yue Hu Date: Tue, 16 Nov 2021 09:08:18 +0800 Subject: [PATCH 07/74] erofs: remove the occupied parameter from z_erofs_pagevec_enqueue() commit 7dea3de7d384f4c8156e8bd93112ba6db1eb276c upstream. No any behavior to variable occupied in z_erofs_attach_page() which is only caller to z_erofs_pagevec_enqueue(). Link: https://lore.kernel.org/r/20210419102623.2015-1-zbestahu@gmail.com Signed-off-by: Yue Hu Reviewed-by: Gao Xiang Signed-off-by: Gao Xiang Signed-off-by: Gao Xiang Signed-off-by: Greg Kroah-Hartman --- fs/erofs/zdata.c | 4 +--- fs/erofs/zpvec.h | 5 +---- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 37c3e28b1e91..6dcb069b16da 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -291,7 +291,6 @@ static int z_erofs_attach_page(struct z_erofs_collector *clt, enum z_erofs_page_type type) { int ret; - bool occupied; /* give priority for inplaceio */ if (clt->mode >= COLLECT_PRIMARY && @@ -299,8 +298,7 @@ static int z_erofs_attach_page(struct z_erofs_collector *clt, z_erofs_try_inplace_io(clt, page)) return 0; - ret = z_erofs_pagevec_enqueue(&clt->vector, - page, type, &occupied); + ret = z_erofs_pagevec_enqueue(&clt->vector, page, type); clt->cl->vcnt += (unsigned int)ret; return ret ? 0 : -EAGAIN; diff --git a/fs/erofs/zpvec.h b/fs/erofs/zpvec.h index bfc12ecbbe83..dfd7fe0503bb 100644 --- a/fs/erofs/zpvec.h +++ b/fs/erofs/zpvec.h @@ -106,10 +106,8 @@ static inline void z_erofs_pagevec_ctor_init(struct z_erofs_pagevec_ctor *ctor, static inline bool z_erofs_pagevec_enqueue(struct z_erofs_pagevec_ctor *ctor, struct page *page, - enum z_erofs_page_type type, - bool *occupied) + enum z_erofs_page_type type) { - *occupied = false; if (!ctor->next && type) if (ctor->index + 1 == ctor->nr) return false; @@ -124,7 +122,6 @@ static inline bool z_erofs_pagevec_enqueue(struct z_erofs_pagevec_ctor *ctor, /* should remind that collector->next never equal to 1, 2 */ if (type == (uintptr_t)ctor->next) { ctor->next = page; - *occupied = true; } ctor->pages[ctor->index++] = tagptr_fold(erofs_vtptr_t, page, type); return true; From e0bca84ae60e9676ed0741815b03b0b0eb0af0e1 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Tue, 16 Nov 2021 09:08:19 +0800 Subject: [PATCH 08/74] erofs: fix unsafe pagevec reuse of hooked pclusters commit 86432a6dca9bed79111990851df5756d3eb5f57c upstream. There are pclusters in runtime marked with Z_EROFS_PCLUSTER_TAIL before actual I/O submission. Thus, the decompression chain can be extended if the following pcluster chain hooks such tail pcluster. As the related comment mentioned, if some page is made of a hooked pcluster and another followed pcluster, it can be reused for in-place I/O (since I/O should be submitted anyway): _______________________________________________________________ | tail (partial) page | head (partial) page | |_____PRIMARY_HOOKED___|____________PRIMARY_FOLLOWED____________| However, it's by no means safe to reuse as pagevec since if such PRIMARY_HOOKED pclusters finally move into bypass chain without I/O submission. It's somewhat hard to reproduce with LZ4 and I just found it (general protection fault) by ro_fsstressing a LZMA image for long time. I'm going to actively clean up related code together with multi-page folio adaption in the next few months. Let's address it directly for easier backporting for now. Call trace for reference: z_erofs_decompress_pcluster+0x10a/0x8a0 [erofs] z_erofs_decompress_queue.isra.36+0x3c/0x60 [erofs] z_erofs_runqueue+0x5f3/0x840 [erofs] z_erofs_readahead+0x1e8/0x320 [erofs] read_pages+0x91/0x270 page_cache_ra_unbounded+0x18b/0x240 filemap_get_pages+0x10a/0x5f0 filemap_read+0xa9/0x330 new_sync_read+0x11b/0x1a0 vfs_read+0xf1/0x190 Link: https://lore.kernel.org/r/20211103182006.4040-1-xiang@kernel.org Fixes: 3883a79abd02 ("staging: erofs: introduce VLE decompression support") Cc: # 4.19+ Reviewed-by: Chao Yu Signed-off-by: Gao Xiang Signed-off-by: Greg Kroah-Hartman --- fs/erofs/zdata.c | 13 +++++++------ fs/erofs/zpvec.h | 13 ++++++++++--- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 6dcb069b16da..e0659382857d 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -287,8 +287,8 @@ static inline bool z_erofs_try_inplace_io(struct z_erofs_collector *clt, /* callers must be with collection lock held */ static int z_erofs_attach_page(struct z_erofs_collector *clt, - struct page *page, - enum z_erofs_page_type type) + struct page *page, enum z_erofs_page_type type, + bool pvec_safereuse) { int ret; @@ -298,9 +298,9 @@ static int z_erofs_attach_page(struct z_erofs_collector *clt, z_erofs_try_inplace_io(clt, page)) return 0; - ret = z_erofs_pagevec_enqueue(&clt->vector, page, type); + ret = z_erofs_pagevec_enqueue(&clt->vector, page, type, + pvec_safereuse); clt->cl->vcnt += (unsigned int)ret; - return ret ? 0 : -EAGAIN; } @@ -642,7 +642,8 @@ static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, tight &= (clt->mode >= COLLECT_PRIMARY_FOLLOWED); retry: - err = z_erofs_attach_page(clt, page, page_type); + err = z_erofs_attach_page(clt, page, page_type, + clt->mode >= COLLECT_PRIMARY_FOLLOWED); /* should allocate an additional staging page for pagevec */ if (err == -EAGAIN) { struct page *const newpage = @@ -650,7 +651,7 @@ static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, newpage->mapping = Z_EROFS_MAPPING_STAGING; err = z_erofs_attach_page(clt, newpage, - Z_EROFS_PAGE_TYPE_EXCLUSIVE); + Z_EROFS_PAGE_TYPE_EXCLUSIVE, true); if (!err) goto retry; } diff --git a/fs/erofs/zpvec.h b/fs/erofs/zpvec.h index dfd7fe0503bb..b05464f4a808 100644 --- a/fs/erofs/zpvec.h +++ b/fs/erofs/zpvec.h @@ -106,11 +106,18 @@ static inline void z_erofs_pagevec_ctor_init(struct z_erofs_pagevec_ctor *ctor, static inline bool z_erofs_pagevec_enqueue(struct z_erofs_pagevec_ctor *ctor, struct page *page, - enum z_erofs_page_type type) + enum z_erofs_page_type type, + bool pvec_safereuse) { - if (!ctor->next && type) - if (ctor->index + 1 == ctor->nr) + if (!ctor->next) { + /* some pages cannot be reused as pvec safely without I/O */ + if (type == Z_EROFS_PAGE_TYPE_EXCLUSIVE && !pvec_safereuse) + type = Z_EROFS_VLE_PAGE_TYPE_TAIL_SHARED; + + if (type != Z_EROFS_PAGE_TYPE_EXCLUSIVE && + ctor->index + 1 == ctor->nr) return false; + } if (ctor->index >= ctor->nr) z_erofs_pagevec_ctor_pagedown(ctor, false); From 814be7844d0f95b9f0643d5e190013747edb728f Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 30 Oct 2020 14:28:39 +0200 Subject: [PATCH 09/74] erofs: remove a void EROFS_VERSION macro set in Makefile Since commit 4f761fa253b4 ("erofs: rename errln/infoln/debugln to erofs_{err, info, dbg}") the defined macro EROFS_VERSION has no affect, therefore removing it from the Makefile is a non-functional change. Link: https://lore.kernel.org/r/20201030122839.25431-1-vladimir@tuxera.com Reviewed-by: Gao Xiang Reviewed-by: Chao Yu Signed-off-by: Vladimir Zapolskiy Signed-off-by: Gao Xiang --- fs/erofs/Makefile | 5 ----- 1 file changed, 5 deletions(-) diff --git a/fs/erofs/Makefile b/fs/erofs/Makefile index 46f2aa4ba46c..af159539fc1b 100644 --- a/fs/erofs/Makefile +++ b/fs/erofs/Makefile @@ -1,11 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -EROFS_VERSION = "1.0" - -ccflags-y += -DEROFS_VERSION=\"$(EROFS_VERSION)\" - obj-$(CONFIG_EROFS_FS) += erofs.o erofs-objs := super.o inode.o data.o namei.o dir.o utils.o erofs-$(CONFIG_EROFS_FS_XATTR) += xattr.o erofs-$(CONFIG_EROFS_FS_ZIP) += decompressor.o zmap.o zdata.o - From 77e2119ba87a9924780bcaee4365c98da10f17d8 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Tue, 8 Dec 2020 17:58:32 +0800 Subject: [PATCH 10/74] erofs: get rid of magical Z_EROFS_MAPPING_STAGING Previously, we played around with magical page->mapping for short-lived temporary pages since we need to identify different types of pages in the same pcluster but both invalidated and short-lived temporary pages can have page->mapping == NULL. It was considered as safe because that temporary pages are all non-LRU / non-movable pages. This patch tends to use specific page->private to identify short-lived pages instead so it won't rely on page->mapping anymore. Details are described in "compress.h" as well. Link: https://lore.kernel.org/r/20201208095834.3133565-1-hsiangkao@redhat.com Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/compress.h | 57 +++++++++++++++++++++++++++++------------ fs/erofs/decompressor.c | 2 +- fs/erofs/zdata.c | 44 +++++++++++++++++++------------ fs/erofs/zdata.h | 1 + 4 files changed, 70 insertions(+), 34 deletions(-) diff --git a/fs/erofs/compress.h b/fs/erofs/compress.h index e9b1aa0afe0e..07cb63d098d9 100644 --- a/fs/erofs/compress.h +++ b/fs/erofs/compress.h @@ -25,30 +25,55 @@ struct z_erofs_decompress_req { bool inplace_io, partial_decoding; }; +/* some special page->private (unsigned long, see below) */ +#define Z_EROFS_SHORTLIVED_PAGE (-1UL << 2) + /* - * - 0x5A110C8D ('sallocated', Z_EROFS_MAPPING_STAGING) - - * used to mark temporary allocated pages from other - * file/cached pages and NULL mapping pages. + * For all pages in a pcluster, page->private should be one of + * Type Last 2bits page->private + * short-lived page 00 Z_EROFS_SHORTLIVED_PAGE + * cached/managed page 00 pointer to z_erofs_pcluster + * online page (file-backed, 01/10/11 sub-index << 2 | count + * some pages can be used for inplace I/O) + * + * page->mapping should be one of + * Type page->mapping + * short-lived page NULL + * cached/managed page non-NULL or NULL (invalidated/truncated page) + * online page non-NULL + * + * For all managed pages, PG_private should be set with 1 extra refcount, + * which is used for page reclaim / migration. */ -#define Z_EROFS_MAPPING_STAGING ((void *)0x5A110C8D) -/* check if a page is marked as staging */ -static inline bool z_erofs_page_is_staging(struct page *page) +/* + * short-lived pages are pages directly from buddy system with specific + * page->private (no need to set PagePrivate since these are non-LRU / + * non-movable pages and bypass reclaim / migration code). + */ +static inline bool z_erofs_is_shortlived_page(struct page *page) { - return page->mapping == Z_EROFS_MAPPING_STAGING; -} - -static inline bool z_erofs_put_stagingpage(struct list_head *pagepool, - struct page *page) -{ - if (!z_erofs_page_is_staging(page)) + if (page->private != Z_EROFS_SHORTLIVED_PAGE) return false; - /* staging pages should not be used by others at the same time */ - if (page_ref_count(page) > 1) + DBG_BUGON(page->mapping); + return true; +} + +static inline bool z_erofs_put_shortlivedpage(struct list_head *pagepool, + struct page *page) +{ + if (!z_erofs_is_shortlived_page(page)) + return false; + + /* short-lived pages should not be used by others at the same time */ + if (page_ref_count(page) > 1) { put_page(page); - else + } else { + /* follow the pcluster rule above. */ + set_page_private(page, 0); list_add(&page->lru, pagepool); + } return true; } diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 1893910f489a..d2853876e91d 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -75,7 +75,7 @@ static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, victim = erofs_allocpage(pagepool, GFP_KERNEL); if (!victim) return -ENOMEM; - victim->mapping = Z_EROFS_MAPPING_STAGING; + set_page_private(victim, Z_EROFS_SHORTLIVED_PAGE); } rq->out[i] = victim; } diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index e0659382857d..0cf4c6d2bf5b 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -235,9 +235,9 @@ int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, /* barrier is implied in the following 'unlock_page' */ WRITE_ONCE(pcl->compressed_pages[i], NULL); + set_page_private(page, 0); ClearPagePrivate(page); - unlock_page(page); put_page(page); } @@ -264,6 +264,7 @@ int erofs_try_to_free_cached_page(struct address_space *mapping, erofs_workgroup_unfreeze(&pcl->obj, 1); if (ret) { + set_page_private(page, 0); ClearPagePrivate(page); put_page(page); } @@ -644,12 +645,12 @@ static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, retry: err = z_erofs_attach_page(clt, page, page_type, clt->mode >= COLLECT_PRIMARY_FOLLOWED); - /* should allocate an additional staging page for pagevec */ + /* should allocate an additional short-lived page for pagevec */ if (err == -EAGAIN) { struct page *const newpage = alloc_page(GFP_NOFS | __GFP_NOFAIL); - newpage->mapping = Z_EROFS_MAPPING_STAGING; + set_page_private(newpage, Z_EROFS_SHORTLIVED_PAGE); err = z_erofs_attach_page(clt, newpage, Z_EROFS_PAGE_TYPE_EXCLUSIVE, true); if (!err) @@ -706,6 +707,11 @@ static void z_erofs_decompress_kickoff(struct z_erofs_decompressqueue *io, queue_work(z_erofs_workqueue, &io->u.work); } +static bool z_erofs_page_is_invalidated(struct page *page) +{ + return !page->mapping && !z_erofs_is_shortlived_page(page); +} + static void z_erofs_decompressqueue_endio(struct bio *bio) { tagptr1_t t = tagptr_init(tagptr1_t, bio->bi_private); @@ -718,7 +724,7 @@ static void z_erofs_decompressqueue_endio(struct bio *bio) struct page *page = bvec->bv_page; DBG_BUGON(PageUptodate(page)); - DBG_BUGON(!page->mapping); + DBG_BUGON(z_erofs_page_is_invalidated(page)); if (err) SetPageError(page); @@ -791,9 +797,9 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, /* all pages in pagevec ought to be valid */ DBG_BUGON(!page); - DBG_BUGON(!page->mapping); + DBG_BUGON(z_erofs_page_is_invalidated(page)); - if (z_erofs_put_stagingpage(pagepool, page)) + if (z_erofs_put_shortlivedpage(pagepool, page)) continue; if (page_type == Z_EROFS_VLE_PAGE_TYPE_HEAD) @@ -827,9 +833,9 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, /* all compressed pages ought to be valid */ DBG_BUGON(!page); - DBG_BUGON(!page->mapping); + DBG_BUGON(z_erofs_page_is_invalidated(page)); - if (!z_erofs_page_is_staging(page)) { + if (!z_erofs_is_shortlived_page(page)) { if (erofs_page_is_managed(sbi, page)) { if (!PageUptodate(page)) err = -EIO; @@ -854,7 +860,7 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, overlapped = true; } - /* PG_error needs checking for inplaced and staging pages */ + /* PG_error needs checking for all non-managed pages */ if (PageError(page)) { DBG_BUGON(PageUptodate(page)); err = -EIO; @@ -893,8 +899,8 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, if (erofs_page_is_managed(sbi, page)) continue; - /* recycle all individual staging pages */ - (void)z_erofs_put_stagingpage(pagepool, page); + /* recycle all individual short-lived pages */ + (void)z_erofs_put_shortlivedpage(pagepool, page); WRITE_ONCE(compressed_pages[i], NULL); } @@ -904,10 +910,10 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, if (!page) continue; - DBG_BUGON(!page->mapping); + DBG_BUGON(z_erofs_page_is_invalidated(page)); - /* recycle all individual staging pages */ - if (z_erofs_put_stagingpage(pagepool, page)) + /* recycle all individual short-lived pages */ + if (z_erofs_put_shortlivedpage(pagepool, page)) continue; if (err < 0) @@ -1007,13 +1013,17 @@ static struct page *pickup_page_for_submission(struct z_erofs_pcluster *pcl, mapping = READ_ONCE(page->mapping); /* - * unmanaged (file) pages are all locked solidly, + * file-backed online pages in plcuster are all locked steady, * therefore it is impossible for `mapping' to be NULL. */ if (mapping && mapping != mc) /* ought to be unmanaged pages */ goto out; + /* directly return for shortlived page as well */ + if (z_erofs_is_shortlived_page(page)) + goto out; + lock_page(page); /* only true if page reclaim goes wrong, should never happen */ @@ -1058,8 +1068,8 @@ static struct page *pickup_page_for_submission(struct z_erofs_pcluster *pcl, out_allocpage: page = erofs_allocpage(pagepool, gfp | __GFP_NOFAIL); if (!tocache || add_to_page_cache_lru(page, mc, index + nr, gfp)) { - /* non-LRU / non-movable temporary page is needed */ - page->mapping = Z_EROFS_MAPPING_STAGING; + /* turn into temporary page if fails */ + set_page_private(page, Z_EROFS_SHORTLIVED_PAGE); tocache = false; } diff --git a/fs/erofs/zdata.h b/fs/erofs/zdata.h index 68da309d5ad7..658bda5efcda 100644 --- a/fs/erofs/zdata.h +++ b/fs/erofs/zdata.h @@ -172,6 +172,7 @@ static inline void z_erofs_onlinepage_endio(struct page *page) v = atomic_dec_return(u.o); if (!(v & Z_EROFS_ONLINEPAGE_COUNT_MASK)) { + set_page_private(page, 0); ClearPagePrivate(page); if (!PageError(page)) SetPageUptodate(page); From d25241a02c9683c2cee9275c4ccf3ac81db2944b Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Tue, 8 Dec 2020 17:58:33 +0800 Subject: [PATCH 11/74] erofs: insert to managed cache after adding to pcl Previously, it could be some concern to call add_to_page_cache_lru() with page->mapping == Z_EROFS_MAPPING_STAGING (!= NULL). In contrast, page->private is used instead now, so partially revert commit 5ddcee1f3a1c ("erofs: get rid of __stagingpage_alloc helper") with some adaption for simplicity. Link: https://lore.kernel.org/r/20201208095834.3133565-2-hsiangkao@redhat.com Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/zdata.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 0cf4c6d2bf5b..3cfd10481bda 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -1067,28 +1067,20 @@ static struct page *pickup_page_for_submission(struct z_erofs_pcluster *pcl, put_page(page); out_allocpage: page = erofs_allocpage(pagepool, gfp | __GFP_NOFAIL); - if (!tocache || add_to_page_cache_lru(page, mc, index + nr, gfp)) { - /* turn into temporary page if fails */ - set_page_private(page, Z_EROFS_SHORTLIVED_PAGE); - tocache = false; - } - if (oldpage != cmpxchg(&pcl->compressed_pages[nr], oldpage, page)) { - if (tocache) { - /* since it added to managed cache successfully */ - unlock_page(page); - put_page(page); - } else { - list_add(&page->lru, pagepool); - } + list_add(&page->lru, pagepool); cond_resched(); goto repeat; } - if (tocache) { - set_page_private(page, (unsigned long)pcl); - SetPagePrivate(page); + if (!tocache || add_to_page_cache_lru(page, mc, index + nr, gfp)) { + /* turn into temporary page if fails (1 ref) */ + set_page_private(page, Z_EROFS_SHORTLIVED_PAGE); + goto out; } + set_page_private(page, (unsigned long)pcl); + SetPagePrivate(page); + out: /* the only exit (for tracing and debugging) */ return page; } From 6fdf3375a10262f74a9bb66812a724eddae65528 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Tue, 8 Dec 2020 17:58:34 +0800 Subject: [PATCH 12/74] erofs: simplify try_to_claim_pcluster() simplify try_to_claim_pcluster() by directly using cmpxchg() here (the retry loop caused more overhead.) Also, move the chain loop detection in and rename it to z_erofs_try_to_claim_pcluster(). Link: https://lore.kernel.org/r/20201208095834.3133565-3-hsiangkao@redhat.com Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/zdata.c | 53 +++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 3cfd10481bda..f5372cd96ea9 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -305,34 +305,33 @@ static int z_erofs_attach_page(struct z_erofs_collector *clt, return ret ? 0 : -EAGAIN; } -static enum z_erofs_collectmode -try_to_claim_pcluster(struct z_erofs_pcluster *pcl, - z_erofs_next_pcluster_t *owned_head) +static void z_erofs_try_to_claim_pcluster(struct z_erofs_collector *clt) { - /* let's claim these following types of pclusters */ -retry: - if (pcl->next == Z_EROFS_PCLUSTER_NIL) { - /* type 1, nil pcluster */ - if (cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_NIL, - *owned_head) != Z_EROFS_PCLUSTER_NIL) - goto retry; + struct z_erofs_pcluster *pcl = clt->pcl; + z_erofs_next_pcluster_t *owned_head = &clt->owned_head; + /* type 1, nil pcluster (this pcluster doesn't belong to any chain.) */ + if (cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_NIL, + *owned_head) == Z_EROFS_PCLUSTER_NIL) { *owned_head = &pcl->next; - /* lucky, I am the followee :) */ - return COLLECT_PRIMARY_FOLLOWED; - } else if (pcl->next == Z_EROFS_PCLUSTER_TAIL) { - /* - * type 2, link to the end of a existing open chain, - * be careful that its submission itself is governed - * by the original owned chain. - */ - if (cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_TAIL, - *owned_head) != Z_EROFS_PCLUSTER_TAIL) - goto retry; - *owned_head = Z_EROFS_PCLUSTER_TAIL; - return COLLECT_PRIMARY_HOOKED; + /* so we can attach this pcluster to our submission chain. */ + clt->mode = COLLECT_PRIMARY_FOLLOWED; + return; } - return COLLECT_PRIMARY; /* :( better luck next time */ + + /* + * type 2, link to the end of an existing open chain, be careful + * that its submission is controlled by the original attached chain. + */ + if (cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_TAIL, + *owned_head) == Z_EROFS_PCLUSTER_TAIL) { + *owned_head = Z_EROFS_PCLUSTER_TAIL; + clt->mode = COLLECT_PRIMARY_HOOKED; + clt->tailpcl = NULL; + return; + } + /* type 3, it belongs to a chain, but it isn't the end of the chain */ + clt->mode = COLLECT_PRIMARY; } static int z_erofs_lookup_collection(struct z_erofs_collector *clt, @@ -385,10 +384,8 @@ static int z_erofs_lookup_collection(struct z_erofs_collector *clt, /* used to check tail merging loop due to corrupted images */ if (clt->owned_head == Z_EROFS_PCLUSTER_TAIL) clt->tailpcl = pcl; - clt->mode = try_to_claim_pcluster(pcl, &clt->owned_head); - /* clean tailpcl if the current owned_head is Z_EROFS_PCLUSTER_TAIL */ - if (clt->owned_head == Z_EROFS_PCLUSTER_TAIL) - clt->tailpcl = NULL; + clt->pcl = pcl; + z_erofs_try_to_claim_pcluster(clt); clt->pcl = pcl; clt->cl = cl; return 0; From 33e7e223d8bf0c1fbf93545396be6c5ddb0a83e9 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 9 Dec 2020 20:37:17 +0800 Subject: [PATCH 13/74] erofs: force inplace I/O under low memory scenario Try to forcely switch to inplace I/O under low memory scenario in order to avoid direct memory reclaim due to cached page allocation. Link: https://lore.kernel.org/r/20201209123717.12430-1-hsiangkao@aol.com Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/compress.h | 3 +++ fs/erofs/zdata.c | 48 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 43 insertions(+), 8 deletions(-) diff --git a/fs/erofs/compress.h b/fs/erofs/compress.h index 07cb63d098d9..3701c72bacb2 100644 --- a/fs/erofs/compress.h +++ b/fs/erofs/compress.h @@ -27,11 +27,13 @@ struct z_erofs_decompress_req { /* some special page->private (unsigned long, see below) */ #define Z_EROFS_SHORTLIVED_PAGE (-1UL << 2) +#define Z_EROFS_PREALLOCATED_PAGE (-2UL << 2) /* * For all pages in a pcluster, page->private should be one of * Type Last 2bits page->private * short-lived page 00 Z_EROFS_SHORTLIVED_PAGE + * preallocated page (tryalloc) 00 Z_EROFS_PREALLOCATED_PAGE * cached/managed page 00 pointer to z_erofs_pcluster * online page (file-backed, 01/10/11 sub-index << 2 | count * some pages can be used for inplace I/O) @@ -39,6 +41,7 @@ struct z_erofs_decompress_req { * page->mapping should be one of * Type page->mapping * short-lived page NULL + * preallocated page NULL * cached/managed page non-NULL or NULL (invalidated/truncated page) * online page non-NULL * diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index f5372cd96ea9..d4cf12dbc683 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -19,6 +19,11 @@ enum z_erofs_cache_alloctype { DONTALLOC, /* don't allocate any cached pages */ DELAYEDALLOC, /* delayed allocation (at the time of submitting io) */ + /* + * try to use cached I/O if page allocation succeeds or fallback + * to in-place I/O instead to avoid any direct reclaim. + */ + TRYALLOC, }; /* @@ -163,13 +168,16 @@ static DEFINE_MUTEX(z_pagemap_global_lock); static void preload_compressed_pages(struct z_erofs_collector *clt, struct address_space *mc, - enum z_erofs_cache_alloctype type) + enum z_erofs_cache_alloctype type, + struct list_head *pagepool) { const struct z_erofs_pcluster *pcl = clt->pcl; const unsigned int clusterpages = BIT(pcl->clusterbits); struct page **pages = clt->compressedpages; pgoff_t index = pcl->obj.index + (pages - pcl->compressed_pages); bool standalone = true; + gfp_t gfp = (mapping_gfp_mask(mc) & ~__GFP_DIRECT_RECLAIM) | + __GFP_NOMEMALLOC | __GFP_NORETRY | __GFP_NOWARN; if (clt->mode < COLLECT_PRIMARY_FOLLOWED) return; @@ -177,6 +185,7 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, for (; pages < pcl->compressed_pages + clusterpages; ++pages) { struct page *page; compressed_page_t t; + struct page *newpage = NULL; /* the compressed page was loaded before */ if (READ_ONCE(*pages)) @@ -188,7 +197,15 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, t = tag_compressed_page_justfound(page); } else if (type == DELAYEDALLOC) { t = tagptr_init(compressed_page_t, PAGE_UNALLOCATED); + } else if (type == TRYALLOC) { + newpage = erofs_allocpage(pagepool, gfp); + if (!newpage) + goto dontalloc; + + set_page_private(newpage, Z_EROFS_PREALLOCATED_PAGE); + t = tag_compressed_page_justfound(newpage); } else { /* DONTALLOC */ +dontalloc: if (standalone) clt->compressedpages = pages; standalone = false; @@ -198,8 +215,12 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, if (!cmpxchg_relaxed(pages, NULL, tagptr_cast_ptr(t))) continue; - if (page) + if (page) { put_page(page); + } else if (newpage) { + set_page_private(newpage, 0); + list_add(&newpage->lru, pagepool); + } } if (standalone) /* downgrade to PRIMARY_FOLLOWED_NOINPLACE */ @@ -555,7 +576,7 @@ static bool should_alloc_managed_pages(struct z_erofs_decompress_frontend *fe, } static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, - struct page *page) + struct page *page, struct list_head *pagepool) { struct inode *const inode = fe->inode; struct erofs_sb_info *const sbi = EROFS_I_SB(inode); @@ -608,11 +629,12 @@ static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, /* preload all compressed pages (maybe downgrade role if necessary) */ if (should_alloc_managed_pages(fe, sbi->cache_strategy, map->m_la)) - cache_strategy = DELAYEDALLOC; + cache_strategy = TRYALLOC; else cache_strategy = DONTALLOC; - preload_compressed_pages(clt, MNGD_MAPPING(sbi), cache_strategy); + preload_compressed_pages(clt, MNGD_MAPPING(sbi), + cache_strategy, pagepool); hitted: /* @@ -1007,6 +1029,16 @@ static struct page *pickup_page_for_submission(struct z_erofs_pcluster *pcl, justfound = tagptr_unfold_tags(t); page = tagptr_unfold_ptr(t); + /* + * preallocated cached pages, which is used to avoid direct reclaim + * otherwise, it will go inplace I/O path instead. + */ + if (page->private == Z_EROFS_PREALLOCATED_PAGE) { + WRITE_ONCE(pcl->compressed_pages[nr], page); + set_page_private(page, 0); + tocache = true; + goto out_tocache; + } mapping = READ_ONCE(page->mapping); /* @@ -1069,7 +1101,7 @@ static struct page *pickup_page_for_submission(struct z_erofs_pcluster *pcl, cond_resched(); goto repeat; } - +out_tocache: if (!tocache || add_to_page_cache_lru(page, mc, index + nr, gfp)) { /* turn into temporary page if fails (1 ref) */ set_page_private(page, Z_EROFS_SHORTLIVED_PAGE); @@ -1279,7 +1311,7 @@ static int z_erofs_readpage(struct file *file, struct page *page) f.headoffset = (erofs_off_t)page->index << PAGE_SHIFT; - err = z_erofs_do_read_page(&f, page); + err = z_erofs_do_read_page(&f, page, &pagepool); (void)z_erofs_collector_end(&f.clt); /* if some compressed cluster ready, need submit them anyway */ @@ -1342,7 +1374,7 @@ static int z_erofs_readpages(struct file *filp, struct address_space *mapping, /* traversal in reverse order */ head = (void *)page_private(page); - err = z_erofs_do_read_page(&f, page); + err = z_erofs_do_read_page(&f, page, &pagepool); if (err) erofs_err(inode->i_sb, "readahead error at page %lu @ nid %llu", From 55a37faecea0e46326035416fcfda54a5f9d7ba7 Mon Sep 17 00:00:00 2001 From: Huang Jianan Date: Tue, 16 Mar 2021 11:15:14 +0800 Subject: [PATCH 14/74] erofs: avoid memory allocation failure during rolling decompression Currently, err would be treated as io error. Therefore, it'd be better to ensure memory allocation during rolling decompression to avoid such io error. In the long term, we might consider adding another !Uptodate case for such case. Link: https://lore.kernel.org/r/20210316031515.90954-1-huangjianan@oppo.com Reviewed-by: Gao Xiang Reviewed-by: Chao Yu Signed-off-by: Huang Jianan Signed-off-by: Guo Weichao Signed-off-by: Gao Xiang --- fs/erofs/decompressor.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index d2853876e91d..cebe62a0fb4e 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -72,9 +72,8 @@ static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, victim = availables[--top]; get_page(victim); } else { - victim = erofs_allocpage(pagepool, GFP_KERNEL); - if (!victim) - return -ENOMEM; + victim = erofs_allocpage(pagepool, + GFP_KERNEL | __GFP_NOFAIL); set_page_private(victim, Z_EROFS_SHORTLIVED_PAGE); } rq->out[i] = victim; From 076924e0ba769d5da8903a4d8fb30472c04efab0 Mon Sep 17 00:00:00 2001 From: Huang Jianan Date: Wed, 17 Mar 2021 11:54:47 +0800 Subject: [PATCH 15/74] erofs: use workqueue decompression for atomic contexts only z_erofs_decompressqueue_endio may not be executed in the atomic context, for example, when dm-verity is turned on. In this scenario, data can be decompressed directly to get rid of additional kworker scheduling overhead. Link: https://lore.kernel.org/r/20210317035448.13921-2-huangjianan@oppo.com Reviewed-by: Gao Xiang Reviewed-by: Chao Yu Signed-off-by: Huang Jianan Signed-off-by: Guo Weichao Signed-off-by: Gao Xiang --- fs/erofs/zdata.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index d4cf12dbc683..086e28ec5a51 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -708,6 +708,7 @@ static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, goto out; } +static void z_erofs_decompressqueue_work(struct work_struct *work); static void z_erofs_decompress_kickoff(struct z_erofs_decompressqueue *io, bool sync, int bios) { @@ -722,8 +723,14 @@ static void z_erofs_decompress_kickoff(struct z_erofs_decompressqueue *io, return; } - if (!atomic_add_return(bios, &io->pending_bios)) + if (atomic_add_return(bios, &io->pending_bios)) + return; + /* Use workqueue decompression for atomic contexts only */ + if (in_atomic() || irqs_disabled()) { queue_work(z_erofs_workqueue, &io->u.work); + return; + } + z_erofs_decompressqueue_work(&io->u.work); } static bool z_erofs_page_is_invalidated(struct page *page) From 9b3398c32d3b89705afddb99d71374120f84d747 Mon Sep 17 00:00:00 2001 From: Huang Jianan Date: Wed, 17 Mar 2021 11:54:48 +0800 Subject: [PATCH 16/74] erofs: use sync decompression for atomic contexts only Sync decompression was introduced to get rid of additional kworker scheduling overhead. But there is no such overhead in non-atomic contexts. Therefore, it should be better to turn off sync decompression to avoid the current thread waiting in z_erofs_runqueue. Link: https://lore.kernel.org/r/20210317035448.13921-3-huangjianan@oppo.com Reviewed-by: Gao Xiang Reviewed-by: Chao Yu Signed-off-by: Huang Jianan Signed-off-by: Guo Weichao Signed-off-by: Gao Xiang --- fs/erofs/internal.h | 3 +++ fs/erofs/super.c | 1 + fs/erofs/zdata.c | 8 ++++++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 5ee2368a18d5..eaa2ebcab926 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -54,6 +54,9 @@ struct erofs_sb_info { /* the dedicated workstation for compression */ struct radix_tree_root workstn_tree; + /* strategy of sync decompression (false - auto, true - force on) */ + bool readahead_sync_decompress; + /* threshold for decompression synchronously */ unsigned int max_sync_decompress_pages; diff --git a/fs/erofs/super.c b/fs/erofs/super.c index 13977976c719..18e31aad02f1 100644 --- a/fs/erofs/super.c +++ b/fs/erofs/super.c @@ -239,6 +239,7 @@ static void erofs_default_options(struct erofs_sb_info *sbi) #ifdef CONFIG_EROFS_FS_ZIP sbi->cache_strategy = EROFS_ZIP_CACHE_READAROUND; sbi->max_sync_decompress_pages = 3; + sbi->readahead_sync_decompress = false; #endif #ifdef CONFIG_EROFS_FS_XATTR set_opt(sbi, XATTR_USER); diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 086e28ec5a51..4dd180a1130c 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -712,6 +712,8 @@ static void z_erofs_decompressqueue_work(struct work_struct *work); static void z_erofs_decompress_kickoff(struct z_erofs_decompressqueue *io, bool sync, int bios) { + struct erofs_sb_info *const sbi = EROFS_SB(io->sb); + /* wake up the caller thread for sync decompression */ if (sync) { unsigned long flags; @@ -725,9 +727,10 @@ static void z_erofs_decompress_kickoff(struct z_erofs_decompressqueue *io, if (atomic_add_return(bios, &io->pending_bios)) return; - /* Use workqueue decompression for atomic contexts only */ + /* Use workqueue and sync decompression for atomic contexts only */ if (in_atomic() || irqs_disabled()) { queue_work(z_erofs_workqueue, &io->u.work); + sbi->readahead_sync_decompress = true; return; } z_erofs_decompressqueue_work(&io->u.work); @@ -1341,7 +1344,8 @@ static int z_erofs_readpages(struct file *filp, struct address_space *mapping, struct inode *const inode = mapping->host; struct erofs_sb_info *const sbi = EROFS_I_SB(inode); - bool sync = (nr_pages <= sbi->max_sync_decompress_pages); + bool sync = (sbi->readahead_sync_decompress && + nr_pages <= sbi->max_sync_decompress_pages); struct z_erofs_decompress_frontend f = DECOMPRESS_FRONTEND_INIT(inode); gfp_t gfp = mapping_gfp_constraint(mapping, GFP_KERNEL); struct page *head = NULL; From eb68e9eefb7231c8431ccd1aca6481c4f0360d72 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Mon, 22 Mar 2021 02:32:27 +0800 Subject: [PATCH 17/74] erofs: complete a missing case for inplace I/O Add a missing case which could cause unnecessary page allocation but not directly use inplace I/O instead, which increases runtime extra memory footprint. The detail is, considering an online file-backed page, the right half of the page is chosen to be cached (e.g. the end page of a readahead request) and some of its data doesn't exist in managed cache, so the pcluster will be definitely kept in the submission chain. (IOWs, it cannot be decompressed without I/O, e.g., due to the bypass queue). Currently, DELAYEDALLOC/TRYALLOC cases can be downgraded as NOINPLACE, and stop online pages from inplace I/O. After this patch, unneeded page allocations won't be observed in pickup_page_for_submission() then. Link: https://lore.kernel.org/r/20210321183227.5182-1-hsiangkao@aol.com Signed-off-by: Gao Xiang --- fs/erofs/zdata.c | 44 +++++++++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 4dd180a1130c..216b074e1b19 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -113,6 +113,12 @@ enum z_erofs_collectmode { * |_______PRIMARY_FOLLOWED_______|________PRIMARY_HOOKED___________| */ COLLECT_PRIMARY_HOOKED, + /* + * a weak form of COLLECT_PRIMARY_FOLLOWED, the difference is that it + * could be dispatched into bypass queue later due to uptodated managed + * pages. All related online pages cannot be reused for inplace I/O (or + * pagevec) since it can be directly decoded without I/O submission. + */ COLLECT_PRIMARY_FOLLOWED_NOINPLACE, /* * The current collection has been linked with the owned chain, and @@ -195,21 +201,25 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, if (page) { t = tag_compressed_page_justfound(page); - } else if (type == DELAYEDALLOC) { - t = tagptr_init(compressed_page_t, PAGE_UNALLOCATED); - } else if (type == TRYALLOC) { - newpage = erofs_allocpage(pagepool, gfp); - if (!newpage) - goto dontalloc; - - set_page_private(newpage, Z_EROFS_PREALLOCATED_PAGE); - t = tag_compressed_page_justfound(newpage); - } else { /* DONTALLOC */ -dontalloc: - if (standalone) - clt->compressedpages = pages; + } else { + /* I/O is needed, no possible to decompress directly */ standalone = false; - continue; + switch (type) { + case DELAYEDALLOC: + t = tagptr_init(compressed_page_t, + PAGE_UNALLOCATED); + break; + case TRYALLOC: + newpage = erofs_allocpage(pagepool, gfp); + if (!newpage) + continue; + set_page_private(newpage, + Z_EROFS_PREALLOCATED_PAGE); + t = tag_compressed_page_justfound(newpage); + break; + default: /* DONTALLOC */ + continue; + } } if (!cmpxchg_relaxed(pages, NULL, tagptr_cast_ptr(t))) @@ -223,7 +233,11 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, } } - if (standalone) /* downgrade to PRIMARY_FOLLOWED_NOINPLACE */ + /* + * don't do inplace I/O if all compressed pages are available in + * managed cache since it can be moved to the bypass queue instead. + */ + if (standalone) clt->mode = COLLECT_PRIMARY_FOLLOWED_NOINPLACE; } From b0a1e9660543a54467461a53c708cef93c7f3e18 Mon Sep 17 00:00:00 2001 From: Yue Hu Date: Thu, 25 Mar 2021 15:10:08 +0800 Subject: [PATCH 18/74] erofs: don't use erofs_map_blocks() any more Currently, erofs_map_blocks() will be called only from erofs_{bmap, read_raw_page} which are all for uncompressed files. So, the compression branch in erofs_map_blocks() is pointless. Let's remove it and use erofs_map_blocks_flatmode() directly. Also update related comments. Link: https://lore.kernel.org/r/20210325071008.573-1-zbestahu@gmail.com Reviewed-by: Chao Yu Signed-off-by: Yue Hu Signed-off-by: Gao Xiang --- fs/erofs/data.c | 19 ++----------------- fs/erofs/internal.h | 6 ++---- 2 files changed, 4 insertions(+), 21 deletions(-) diff --git a/fs/erofs/data.c b/fs/erofs/data.c index 4f305b68497e..dc264a819dc2 100644 --- a/fs/erofs/data.c +++ b/fs/erofs/data.c @@ -108,21 +108,6 @@ static int erofs_map_blocks_flatmode(struct inode *inode, return err; } -int erofs_map_blocks(struct inode *inode, - struct erofs_map_blocks *map, int flags) -{ - if (erofs_inode_is_data_compressed(EROFS_I(inode)->datalayout)) { - int err = z_erofs_map_blocks_iter(inode, map, flags); - - if (map->mpage) { - put_page(map->mpage); - map->mpage = NULL; - } - return err; - } - return erofs_map_blocks_flatmode(inode, map, flags); -} - static inline struct bio *erofs_read_raw_page(struct bio *bio, struct address_space *mapping, struct page *page, @@ -158,7 +143,7 @@ static inline struct bio *erofs_read_raw_page(struct bio *bio, erofs_blk_t blknr; unsigned int blkoff; - err = erofs_map_blocks(inode, &map, EROFS_GET_BLOCKS_RAW); + err = erofs_map_blocks_flatmode(inode, &map, EROFS_GET_BLOCKS_RAW); if (err) goto err_out; @@ -336,7 +321,7 @@ static sector_t erofs_bmap(struct address_space *mapping, sector_t block) return 0; } - if (!erofs_map_blocks(inode, &map, EROFS_GET_BLOCKS_RAW)) + if (!erofs_map_blocks_flatmode(inode, &map, EROFS_GET_BLOCKS_RAW)) return erofs_blknr(map.m_pa); return 0; diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index eaa2ebcab926..ef55cfae4cd6 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -284,7 +284,7 @@ extern const struct address_space_operations erofs_raw_access_aops; extern const struct address_space_operations z_erofs_aops; /* - * Logical to physical block mapping, used by erofs_map_blocks() + * Logical to physical block mapping * * Different with other file systems, it is used for 2 access modes: * @@ -331,7 +331,7 @@ struct erofs_map_blocks { struct page *mpage; }; -/* Flags used by erofs_map_blocks() */ +/* Flags used by erofs_map_blocks_flatmode() */ #define EROFS_GET_BLOCKS_RAW 0x0001 /* zmap.c */ @@ -353,8 +353,6 @@ static inline int z_erofs_map_blocks_iter(struct inode *inode, /* data.c */ struct page *erofs_get_meta_page(struct super_block *sb, erofs_blk_t blkaddr); -int erofs_map_blocks(struct inode *, struct erofs_map_blocks *, int); - /* inode.c */ static inline unsigned long erofs_inode_hash(erofs_nid_t nid) { From 3877bc67a9c285a97653a7e297c718d9f4d95722 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Mon, 29 Mar 2021 09:23:05 +0800 Subject: [PATCH 19/74] erofs: introduce erofs_sb_has_xxx() helpers Introduce erofs_sb_has_xxx() to make long checks short, especially for later big pcluster & LZMA features. Link: https://lore.kernel.org/r/20210329012308.28743-2-hsiangkao@aol.com Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/decompressor.c | 3 +-- fs/erofs/internal.h | 9 +++++++++ fs/erofs/super.c | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index cebe62a0fb4e..510b8b3b5271 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -123,8 +123,7 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) support_0padding = false; /* decompression inplace is only safe when 0padding is enabled */ - if (EROFS_SB(rq->sb)->feature_incompat & - EROFS_FEATURE_INCOMPAT_LZ4_0PADDING) { + if (erofs_sb_has_lz4_0padding(EROFS_SB(rq->sb))) { support_0padding = true; while (!src[inputmargin & ~PAGE_MASK]) diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index ef55cfae4cd6..aa1a7ce8c1aa 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -213,6 +213,15 @@ static inline erofs_off_t iloc(struct erofs_sb_info *sbi, erofs_nid_t nid) return blknr_to_addr(sbi->meta_blkaddr) + (nid << sbi->islotbits); } +#define EROFS_FEATURE_FUNCS(name, compat, feature) \ +static inline bool erofs_sb_has_##name(struct erofs_sb_info *sbi) \ +{ \ + return sbi->feature_##compat & EROFS_FEATURE_##feature; \ +} + +EROFS_FEATURE_FUNCS(lz4_0padding, incompat, INCOMPAT_LZ4_0PADDING) +EROFS_FEATURE_FUNCS(sb_chksum, compat, COMPAT_SB_CHKSUM) + /* atomic flag definitions */ #define EROFS_I_EA_INITED_BIT 0 #define EROFS_I_Z_INITED_BIT 1 diff --git a/fs/erofs/super.c b/fs/erofs/super.c index 18e31aad02f1..6cac5d1489b6 100644 --- a/fs/erofs/super.c +++ b/fs/erofs/super.c @@ -152,7 +152,7 @@ static int erofs_read_superblock(struct super_block *sb) } sbi->feature_compat = le32_to_cpu(dsb->feature_compat); - if (sbi->feature_compat & EROFS_FEATURE_COMPAT_SB_CHKSUM) { + if (erofs_sb_has_sb_chksum(sbi)) { ret = erofs_superblock_csum_verify(sb, data); if (ret) goto out; From c4040ba892191f981753fa6759ea6584a372ec1a Mon Sep 17 00:00:00 2001 From: Huang Jianan Date: Mon, 29 Mar 2021 09:23:06 +0800 Subject: [PATCH 20/74] erofs: support adjust lz4 history window size lz4 uses LZ4_DISTANCE_MAX to record history preservation. When using rolling decompression, a block with a higher compression ratio will cause a larger memory allocation (up to 64k). It may cause a large resource burden in extreme cases on devices with small memory and a large number of concurrent IOs. So appropriately reducing this value can improve performance. Decreasing this value will reduce the compression ratio (except when input_size Signed-off-by: Huang Jianan Signed-off-by: Guo Weichao [ Gao Xiang: introduce struct erofs_sb_lz4_info for configurations. ] Signed-off-by: Gao Xiang --- fs/erofs/decompressor.c | 21 +++++++++++++++++---- fs/erofs/erofs_fs.h | 4 +++- fs/erofs/internal.h | 19 +++++++++++++++++++ fs/erofs/super.c | 4 +++- 4 files changed, 42 insertions(+), 6 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 510b8b3b5271..8ee4fa6ecd20 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -27,6 +27,17 @@ struct z_erofs_decompressor { char *name; }; +int z_erofs_load_lz4_config(struct super_block *sb, + struct erofs_super_block *dsb) +{ + u16 distance = le16_to_cpu(dsb->lz4_max_distance); + + EROFS_SB(sb)->lz4.max_distance_pages = distance ? + DIV_ROUND_UP(distance, PAGE_SIZE) + 1 : + LZ4_MAX_DISTANCE_PAGES; + return 0; +} + static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, struct list_head *pagepool) { @@ -35,6 +46,8 @@ static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, struct page *availables[LZ4_MAX_DISTANCE_PAGES] = { NULL }; unsigned long bounced[DIV_ROUND_UP(LZ4_MAX_DISTANCE_PAGES, BITS_PER_LONG)] = { 0 }; + unsigned int lz4_max_distance_pages = + EROFS_SB(rq->sb)->lz4.max_distance_pages; void *kaddr = NULL; unsigned int i, j, top; @@ -43,14 +56,14 @@ static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, struct page *const page = rq->out[i]; struct page *victim; - if (j >= LZ4_MAX_DISTANCE_PAGES) + if (j >= lz4_max_distance_pages) j = 0; /* 'valid' bounced can only be tested after a complete round */ if (test_bit(j, bounced)) { - DBG_BUGON(i < LZ4_MAX_DISTANCE_PAGES); - DBG_BUGON(top >= LZ4_MAX_DISTANCE_PAGES); - availables[top++] = rq->out[i - LZ4_MAX_DISTANCE_PAGES]; + DBG_BUGON(i < lz4_max_distance_pages); + DBG_BUGON(top >= lz4_max_distance_pages); + availables[top++] = rq->out[i - lz4_max_distance_pages]; } if (page) { diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h index 011c3e281f7f..a1b212f6812b 100644 --- a/fs/erofs/erofs_fs.h +++ b/fs/erofs/erofs_fs.h @@ -39,7 +39,9 @@ struct erofs_super_block { __u8 uuid[16]; /* 128-bit uuid for volume */ __u8 volume_name[16]; /* volume name */ __le32 feature_incompat; - __u8 reserved2[44]; + /* customized lz4 sliding window size instead of 64k by default */ + __le16 lz4_max_distance; + __u8 reserved2[42]; }; /* diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index aa1a7ce8c1aa..4c15f0b8261e 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -45,6 +45,12 @@ typedef u64 erofs_off_t; /* data type for filesystem-wide blocks number */ typedef u32 erofs_blk_t; +/* all filesystem-wide lz4 configurations */ +struct erofs_sb_lz4_info { + /* # of pages needed for EROFS lz4 rolling decompression */ + u16 max_distance_pages; +}; + struct erofs_sb_info { #ifdef CONFIG_EROFS_FS_ZIP /* list for all registered superblocks, mainly for shrinker */ @@ -67,6 +73,8 @@ struct erofs_sb_info { /* pseudo inode to manage cached pages */ struct inode *managed_cache; + + struct erofs_sb_lz4_info lz4; #endif /* CONFIG_EROFS_FS_ZIP */ u32 blocks; u32 meta_blkaddr; @@ -424,6 +432,8 @@ int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, struct erofs_workgroup *egrp); int erofs_try_to_free_cached_page(struct address_space *mapping, struct page *page); +int z_erofs_load_lz4_config(struct super_block *sb, + struct erofs_super_block *dsb); #else static inline void erofs_shrinker_register(struct super_block *sb) {} static inline void erofs_shrinker_unregister(struct super_block *sb) {} @@ -431,6 +441,15 @@ static inline int erofs_init_shrinker(void) { return 0; } static inline void erofs_exit_shrinker(void) {} static inline int z_erofs_init_zip_subsystem(void) { return 0; } static inline void z_erofs_exit_zip_subsystem(void) {} +static inline int z_erofs_load_lz4_config(struct super_block *sb, + struct erofs_super_block *dsb) +{ + if (dsb->lz4_max_distance) { + erofs_err(sb, "lz4 algorithm isn't enabled"); + return -EINVAL; + } + return 0; +} #endif /* !CONFIG_EROFS_FS_ZIP */ #define EFSCORRUPTED EUCLEAN /* Filesystem is corrupted */ diff --git a/fs/erofs/super.c b/fs/erofs/super.c index 6cac5d1489b6..599463632bd3 100644 --- a/fs/erofs/super.c +++ b/fs/erofs/super.c @@ -191,7 +191,9 @@ static int erofs_read_superblock(struct super_block *sb) ret = -EFSCORRUPTED; goto out; } - ret = 0; + + /* parse on-disk compression configurations */ + ret = z_erofs_load_lz4_config(sb, dsb); out: kunmap(page); put_page(page); From 4c219cefe47c98e54dd9c83822d02d0a2b6bcfce Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Mon, 29 Mar 2021 09:23:07 +0800 Subject: [PATCH 21/74] erofs: introduce on-disk lz4 fs configurations Introduce z_erofs_lz4_cfgs to store all lz4 configurations. Currently it's only max_distance, but will be used for new features later. Link: https://lore.kernel.org/r/20210329012308.28743-4-hsiangkao@aol.com Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/decompressor.c | 15 +++++++++++++-- fs/erofs/erofs_fs.h | 6 ++++++ fs/erofs/internal.h | 8 +++++--- fs/erofs/super.c | 2 +- 4 files changed, 25 insertions(+), 6 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 8ee4fa6ecd20..4a8a3779f9cd 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -28,9 +28,20 @@ struct z_erofs_decompressor { }; int z_erofs_load_lz4_config(struct super_block *sb, - struct erofs_super_block *dsb) + struct erofs_super_block *dsb, + struct z_erofs_lz4_cfgs *lz4, int size) { - u16 distance = le16_to_cpu(dsb->lz4_max_distance); + u16 distance; + + if (lz4) { + if (size < sizeof(struct z_erofs_lz4_cfgs)) { + erofs_err(sb, "invalid lz4 cfgs, size=%u", size); + return -EINVAL; + } + distance = le16_to_cpu(lz4->max_distance); + } else { + distance = le16_to_cpu(dsb->lz4_max_distance); + } EROFS_SB(sb)->lz4.max_distance_pages = distance ? DIV_ROUND_UP(distance, PAGE_SIZE) + 1 : diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h index a1b212f6812b..383cc5c8f98b 100644 --- a/fs/erofs/erofs_fs.h +++ b/fs/erofs/erofs_fs.h @@ -200,6 +200,12 @@ enum { Z_EROFS_COMPRESSION_MAX }; +/* 14 bytes (+ length field = 16 bytes) */ +struct z_erofs_lz4_cfgs { + __le16 max_distance; + u8 reserved[12]; +} __packed; + /* * bit 0 : COMPACTED_2B indexes (0 - off; 1 - on) * e.g. for 4k logical cluster size, 4B if compacted 2B is off; diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 4c15f0b8261e..5785a0631a1d 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -433,7 +433,8 @@ int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, int erofs_try_to_free_cached_page(struct address_space *mapping, struct page *page); int z_erofs_load_lz4_config(struct super_block *sb, - struct erofs_super_block *dsb); + struct erofs_super_block *dsb, + struct z_erofs_lz4_cfgs *lz4, int len); #else static inline void erofs_shrinker_register(struct super_block *sb) {} static inline void erofs_shrinker_unregister(struct super_block *sb) {} @@ -442,9 +443,10 @@ static inline void erofs_exit_shrinker(void) {} static inline int z_erofs_init_zip_subsystem(void) { return 0; } static inline void z_erofs_exit_zip_subsystem(void) {} static inline int z_erofs_load_lz4_config(struct super_block *sb, - struct erofs_super_block *dsb) + struct erofs_super_block *dsb, + struct z_erofs_lz4_cfgs *lz4, int len) { - if (dsb->lz4_max_distance) { + if (lz4 || dsb->lz4_max_distance) { erofs_err(sb, "lz4 algorithm isn't enabled"); return -EINVAL; } diff --git a/fs/erofs/super.c b/fs/erofs/super.c index 599463632bd3..495a4e2b720d 100644 --- a/fs/erofs/super.c +++ b/fs/erofs/super.c @@ -193,7 +193,7 @@ static int erofs_read_superblock(struct super_block *sb) } /* parse on-disk compression configurations */ - ret = z_erofs_load_lz4_config(sb, dsb); + ret = z_erofs_load_lz4_config(sb, dsb, NULL, 0); out: kunmap(page); put_page(page); From 16c996732f31abd4e5f74c7225c4635203c7df07 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Mon, 29 Mar 2021 18:00:12 +0800 Subject: [PATCH 22/74] erofs: add on-disk compression configurations Add a bitmap for available compression algorithms and a variable-sized on-disk table for compression options in preparation for upcoming big pcluster and LZMA algorithm, which follows the end of super block. To parse the compression options, the bitmap is scanned one by one. For each available algorithm, there is data followed by 2-byte `length' correspondingly (it's enough for most cases, or entire fs blocks should be used.) With such available algorithm bitmap, kernel itself can also refuse to mount such filesystem if any unsupported compression algorithm exists. Note that COMPR_CFGS feature will be enabled with BIG_PCLUSTER. Link: https://lore.kernel.org/r/20210329100012.12980-1-hsiangkao@aol.com Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/decompressor.c | 2 +- fs/erofs/erofs_fs.h | 16 +++-- fs/erofs/internal.h | 5 +- fs/erofs/super.c | 141 +++++++++++++++++++++++++++++++++++++++- 4 files changed, 157 insertions(+), 7 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 4a8a3779f9cd..6e7a74ede63b 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -40,7 +40,7 @@ int z_erofs_load_lz4_config(struct super_block *sb, } distance = le16_to_cpu(lz4->max_distance); } else { - distance = le16_to_cpu(dsb->lz4_max_distance); + distance = le16_to_cpu(dsb->u1.lz4_max_distance); } EROFS_SB(sb)->lz4.max_distance_pages = distance ? diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h index 383cc5c8f98b..39e24fda8b95 100644 --- a/fs/erofs/erofs_fs.h +++ b/fs/erofs/erofs_fs.h @@ -18,15 +18,18 @@ * be incompatible with this kernel version. */ #define EROFS_FEATURE_INCOMPAT_LZ4_0PADDING 0x00000001 +#define EROFS_FEATURE_INCOMPAT_COMPR_CFGS 0x00000002 #define EROFS_ALL_FEATURE_INCOMPAT EROFS_FEATURE_INCOMPAT_LZ4_0PADDING -/* 128-byte erofs on-disk super block */ +#define EROFS_SB_EXTSLOT_SIZE 16 + +/* erofs on-disk super block (currently 128 bytes) */ struct erofs_super_block { __le32 magic; /* file system magic number */ __le32 checksum; /* crc32c(super_block) */ __le32 feature_compat; __u8 blkszbits; /* support block_size == PAGE_SIZE only */ - __u8 reserved; + __u8 sb_extslots; /* superblock size = 128 + sb_extslots * 16 */ __le16 root_nid; /* nid of root directory */ __le64 inos; /* total valid ino # (== f_files - f_favail) */ @@ -39,8 +42,12 @@ struct erofs_super_block { __u8 uuid[16]; /* 128-bit uuid for volume */ __u8 volume_name[16]; /* volume name */ __le32 feature_incompat; - /* customized lz4 sliding window size instead of 64k by default */ - __le16 lz4_max_distance; + union { + /* bitmap for available compression algorithms */ + __le16 available_compr_algs; + /* customized sliding window size instead of 64k by default */ + __le16 lz4_max_distance; + } __packed u1; __u8 reserved2[42]; }; @@ -199,6 +206,7 @@ enum { Z_EROFS_COMPRESSION_LZ4 = 0, Z_EROFS_COMPRESSION_MAX }; +#define Z_EROFS_ALL_COMPR_ALGS (1 << (Z_EROFS_COMPRESSION_MAX - 1)) /* 14 bytes (+ length field = 16 bytes) */ struct z_erofs_lz4_cfgs { diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 5785a0631a1d..1dc54ef5f9ba 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -67,6 +67,7 @@ struct erofs_sb_info { unsigned int max_sync_decompress_pages; unsigned int shrinker_run_no; + u16 available_compr_algs; /* current strategy of how to use managed cache */ unsigned char cache_strategy; @@ -85,6 +86,7 @@ struct erofs_sb_info { /* inode slot unit size in bit shift */ unsigned char islotbits; + u32 sb_size; /* total superblock size */ u32 build_time_nsec; u64 build_time; @@ -228,6 +230,7 @@ static inline bool erofs_sb_has_##name(struct erofs_sb_info *sbi) \ } EROFS_FEATURE_FUNCS(lz4_0padding, incompat, INCOMPAT_LZ4_0PADDING) +EROFS_FEATURE_FUNCS(compr_cfgs, incompat, INCOMPAT_COMPR_CFGS) EROFS_FEATURE_FUNCS(sb_chksum, compat, COMPAT_SB_CHKSUM) /* atomic flag definitions */ @@ -446,7 +449,7 @@ static inline int z_erofs_load_lz4_config(struct super_block *sb, struct erofs_super_block *dsb, struct z_erofs_lz4_cfgs *lz4, int len) { - if (lz4 || dsb->lz4_max_distance) { + if (lz4 || dsb->u1.lz4_max_distance) { erofs_err(sb, "lz4 algorithm isn't enabled"); return -EINVAL; } diff --git a/fs/erofs/super.c b/fs/erofs/super.c index 495a4e2b720d..ba63008b2c28 100644 --- a/fs/erofs/super.c +++ b/fs/erofs/super.c @@ -125,6 +125,136 @@ static bool check_layout_compatibility(struct super_block *sb, return true; } +#ifdef CONFIG_EROFS_FS_ZIP +/* read variable-sized metadata, offset will be aligned by 4-byte */ +static void *erofs_read_metadata(struct super_block *sb, struct page **pagep, + erofs_off_t *offset, int *lengthp) +{ + struct page *page = *pagep; + u8 *buffer, *ptr; + int len, i, cnt; + erofs_blk_t blk; + + *offset = round_up(*offset, 4); + blk = erofs_blknr(*offset); + + if (!page || page->index != blk) { + if (page) { + unlock_page(page); + put_page(page); + } + page = erofs_get_meta_page(sb, blk); + if (IS_ERR(page)) + goto err_nullpage; + } + + ptr = kmap(page); + len = le16_to_cpu(*(__le16 *)&ptr[erofs_blkoff(*offset)]); + if (!len) + len = U16_MAX + 1; + buffer = kmalloc(len, GFP_KERNEL); + if (!buffer) { + buffer = ERR_PTR(-ENOMEM); + goto out; + } + *offset += sizeof(__le16); + *lengthp = len; + + for (i = 0; i < len; i += cnt) { + cnt = min(EROFS_BLKSIZ - (int)erofs_blkoff(*offset), len - i); + blk = erofs_blknr(*offset); + + if (!page || page->index != blk) { + if (page) { + kunmap(page); + unlock_page(page); + put_page(page); + } + page = erofs_get_meta_page(sb, blk); + if (IS_ERR(page)) { + kfree(buffer); + goto err_nullpage; + } + ptr = kmap(page); + } + memcpy(buffer + i, ptr + erofs_blkoff(*offset), cnt); + *offset += cnt; + } +out: + kunmap(page); + *pagep = page; + return buffer; +err_nullpage: + *pagep = NULL; + return page; +} + +static int erofs_load_compr_cfgs(struct super_block *sb, + struct erofs_super_block *dsb) +{ + struct erofs_sb_info *sbi; + struct page *page; + unsigned int algs, alg; + erofs_off_t offset; + int size, ret; + + sbi = EROFS_SB(sb); + sbi->available_compr_algs = le16_to_cpu(dsb->u1.available_compr_algs); + + if (sbi->available_compr_algs & ~Z_EROFS_ALL_COMPR_ALGS) { + erofs_err(sb, "try to load compressed fs with unsupported algorithms %x", + sbi->available_compr_algs & ~Z_EROFS_ALL_COMPR_ALGS); + return -EINVAL; + } + + offset = EROFS_SUPER_OFFSET + sbi->sb_size; + page = NULL; + alg = 0; + ret = 0; + + for (algs = sbi->available_compr_algs; algs; algs >>= 1, ++alg) { + void *data; + + if (!(algs & 1)) + continue; + + data = erofs_read_metadata(sb, &page, &offset, &size); + if (IS_ERR(data)) { + ret = PTR_ERR(data); + goto err; + } + + switch (alg) { + case Z_EROFS_COMPRESSION_LZ4: + ret = z_erofs_load_lz4_config(sb, dsb, data, size); + break; + default: + DBG_BUGON(1); + ret = -EFAULT; + } + kfree(data); + if (ret) + goto err; + } +err: + if (page) { + unlock_page(page); + put_page(page); + } + return ret; +} +#else +static int erofs_load_compr_cfgs(struct super_block *sb, + struct erofs_super_block *dsb) +{ + if (dsb->u1.available_compr_algs) { + erofs_err(sb, "try to load compressed fs when compression is disabled"); + return -EINVAL; + } + return 0; +} +#endif + static int erofs_read_superblock(struct super_block *sb) { struct erofs_sb_info *sbi; @@ -170,6 +300,12 @@ static int erofs_read_superblock(struct super_block *sb) if (!check_layout_compatibility(sb, dsb)) goto out; + sbi->sb_size = 128 + dsb->sb_extslots * EROFS_SB_EXTSLOT_SIZE; + if (sbi->sb_size > EROFS_BLKSIZ) { + erofs_err(sb, "invalid sb_extslots %u (more than a fs block)", + sbi->sb_size); + goto out; + } sbi->blocks = le32_to_cpu(dsb->blocks); sbi->meta_blkaddr = le32_to_cpu(dsb->meta_blkaddr); #ifdef CONFIG_EROFS_FS_XATTR @@ -193,7 +329,10 @@ static int erofs_read_superblock(struct super_block *sb) } /* parse on-disk compression configurations */ - ret = z_erofs_load_lz4_config(sb, dsb, NULL, 0); + if (erofs_sb_has_compr_cfgs(sbi)) + ret = erofs_load_compr_cfgs(sb, dsb); + else + ret = z_erofs_load_lz4_config(sb, dsb, NULL, 0); out: kunmap(page); put_page(page); From c9996699b46105476c14ca1adeb8b2fa096b1abe Mon Sep 17 00:00:00 2001 From: Ruiqi Gong Date: Wed, 31 Mar 2021 05:39:20 -0400 Subject: [PATCH 23/74] erofs: Clean up spelling mistakes found in fs/erofs zmap.c: s/correspoinding/corresponding zdata.c: s/endding/ending Link: https://lore.kernel.org/r/20210331093920.31923-1-gongruiqi1@huawei.com Reported-by: Hulk Robot Signed-off-by: Ruiqi Gong Reviewed-by: Gao Xiang Signed-off-by: Gao Xiang --- fs/erofs/zdata.c | 2 +- fs/erofs/zmap.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 216b074e1b19..477163b69c04 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -935,7 +935,7 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, }, pagepool); out: - /* must handle all compressed pages before endding pages */ + /* must handle all compressed pages before ending pages */ for (i = 0; i < clusterpages; ++i) { page = compressed_pages[i]; diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c index a13f69cf4026..bc3cfb6fb957 100644 --- a/fs/erofs/zmap.c +++ b/fs/erofs/zmap.c @@ -442,7 +442,7 @@ int z_erofs_map_blocks_iter(struct inode *inode, m.delta[0] = 1; /* fallthrough */ case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: - /* get the correspoinding first chunk */ + /* get the corresponding first chunk */ err = z_erofs_extent_lookback(&m, m.delta[0]); if (err) goto unmap_out; From 5eb979af027198bf0ce3838ccfd55d878ed5fae2 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:18 +0800 Subject: [PATCH 24/74] erofs: reserve physical_clusterbits[] Formal big pcluster design is actually more powerful / flexable than the previous thought whose pclustersize was fixed as power-of-2 blocks, which was obviously inefficient and space-wasting. Instead, pclustersize can now be set independently for each pcluster, so various pcluster sizes can also be used together in one file if mkfs wants (for example, according to data type and/or compression ratio). Let's get rid of previous physical_clusterbits[] setting (also notice that corresponding on-disk fields are still 0 for now). Therefore, head1/2 can be used for at most 2 different algorithms in one file and again pclustersize is now independent of these. Link: https://lore.kernel.org/r/20210407043927.10623-2-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/erofs_fs.h | 4 +--- fs/erofs/internal.h | 1 - fs/erofs/zdata.c | 3 +-- fs/erofs/zmap.c | 15 --------------- 4 files changed, 2 insertions(+), 21 deletions(-) diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h index 39e24fda8b95..04010fb6b370 100644 --- a/fs/erofs/erofs_fs.h +++ b/fs/erofs/erofs_fs.h @@ -233,9 +233,7 @@ struct z_erofs_map_header { __u8 h_algorithmtype; /* * bit 0-2 : logical cluster bits - 12, e.g. 0 for 4096; - * bit 3-4 : (physical - logical) cluster bits of head 1: - * For example, if logical clustersize = 4096, 1 for 8192. - * bit 5-7 : (physical - logical) cluster bits of head 2. + * bit 3-7 : reserved. */ __u8 h_clusterbits; }; diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 1dc54ef5f9ba..821d910cd1cc 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -261,7 +261,6 @@ struct erofs_inode { unsigned short z_advise; unsigned char z_algorithmtype[2]; unsigned char z_logical_clusterbits; - unsigned char z_physical_clusterbits[2]; }; #endif /* CONFIG_EROFS_FS_ZIP */ }; diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 477163b69c04..f93a23cfe257 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -451,8 +451,7 @@ static int z_erofs_register_collection(struct z_erofs_collector *clt, else pcl->algorithmformat = Z_EROFS_COMPRESSION_SHIFTED; - pcl->clusterbits = EROFS_I(inode)->z_physical_clusterbits[0]; - pcl->clusterbits -= PAGE_SHIFT; + pcl->clusterbits = 0; /* new pclusters should be claimed as type 1, primary and followed */ pcl->next = clt->owned_head; diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c index bc3cfb6fb957..4f504708c558 100644 --- a/fs/erofs/zmap.c +++ b/fs/erofs/zmap.c @@ -16,11 +16,8 @@ int z_erofs_fill_inode(struct inode *inode) vi->z_algorithmtype[0] = 0; vi->z_algorithmtype[1] = 0; vi->z_logical_clusterbits = LOG_BLOCK_SIZE; - vi->z_physical_clusterbits[0] = vi->z_logical_clusterbits; - vi->z_physical_clusterbits[1] = vi->z_logical_clusterbits; set_bit(EROFS_I_Z_INITED_BIT, &vi->flags); } - inode->i_mapping->a_ops = &z_erofs_aops; return 0; } @@ -76,18 +73,6 @@ static int z_erofs_fill_inode_lazy(struct inode *inode) } vi->z_logical_clusterbits = LOG_BLOCK_SIZE + (h->h_clusterbits & 7); - vi->z_physical_clusterbits[0] = vi->z_logical_clusterbits + - ((h->h_clusterbits >> 3) & 3); - - if (vi->z_physical_clusterbits[0] != LOG_BLOCK_SIZE) { - erofs_err(sb, "unsupported physical clusterbits %u for nid %llu, please upgrade kernel", - vi->z_physical_clusterbits[0], vi->nid); - err = -EOPNOTSUPP; - goto unmap_done; - } - - vi->z_physical_clusterbits[1] = vi->z_logical_clusterbits + - ((h->h_clusterbits >> 5) & 7); /* paired with smp_mb() at the beginning of the function */ smp_mb(); set_bit(EROFS_I_Z_INITED_BIT, &vi->flags); From 092ced045a27369516a938aa862904f4405d8d69 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Sat, 10 Apr 2021 03:06:30 +0800 Subject: [PATCH 25/74] erofs: introduce multipage per-CPU buffers To deal the with the cases which inplace decompression is infeasible for some inplace I/O. Per-CPU buffers was introduced to get rid of page allocation latency and thrash for low-latency decompression algorithms such as lz4. For the big pcluster feature, introduce multipage per-CPU buffers to keep such inplace I/O pclusters temporarily as well but note that per-CPU pages are just consecutive virtually. When a new big pcluster fs is mounted, its max pclustersize will be read and per-CPU buffers can be growed if needed. Shrinking adjustable per-CPU buffers is more complex (because we don't know if such size is still be used), so currently just release them all when unloading. Link: https://lore.kernel.org/r/20210409190630.19569-1-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/Makefile | 2 +- fs/erofs/decompressor.c | 8 ++- fs/erofs/internal.h | 25 ++----- fs/erofs/pcpubuf.c | 148 ++++++++++++++++++++++++++++++++++++++++ fs/erofs/super.c | 2 + fs/erofs/utils.c | 12 ---- 6 files changed, 163 insertions(+), 34 deletions(-) create mode 100644 fs/erofs/pcpubuf.c diff --git a/fs/erofs/Makefile b/fs/erofs/Makefile index af159539fc1b..1f9aced49070 100644 --- a/fs/erofs/Makefile +++ b/fs/erofs/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_EROFS_FS) += erofs.o -erofs-objs := super.o inode.o data.o namei.o dir.o utils.o +erofs-objs := super.o inode.o data.o namei.o dir.o utils.o pcpubuf.o erofs-$(CONFIG_EROFS_FS_XATTR) += xattr.o erofs-$(CONFIG_EROFS_FS_ZIP) += decompressor.o zmap.o zdata.o diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 6e7a74ede63b..7292b1b130c6 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -46,7 +46,9 @@ int z_erofs_load_lz4_config(struct super_block *sb, EROFS_SB(sb)->lz4.max_distance_pages = distance ? DIV_ROUND_UP(distance, PAGE_SIZE) + 1 : LZ4_MAX_DISTANCE_PAGES; - return 0; + + /* TODO: use max pclusterblks after bigpcluster is enabled */ + return erofs_pcpubuf_growsize(1); } static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, @@ -113,7 +115,7 @@ static void *generic_copy_inplace_data(struct z_erofs_decompress_req *rq, * pages should be copied in order to avoid being overlapped. */ struct page **in = rq->in; - u8 *const tmp = erofs_get_pcpubuf(0); + u8 *const tmp = erofs_get_pcpubuf(1); u8 *tmpp = tmp; unsigned int inlen = rq->inputsize - pageofs_in; unsigned int count = min_t(uint, inlen, PAGE_SIZE - pageofs_in); @@ -269,7 +271,7 @@ static int z_erofs_decompress_generic(struct z_erofs_decompress_req *rq, * compressed data is preferred. */ if (rq->outputsize <= PAGE_SIZE * 7 / 8) { - dst = erofs_get_pcpubuf(0); + dst = erofs_get_pcpubuf(1); if (IS_ERR(dst)) return PTR_ERR(dst); diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 821d910cd1cc..c88daf2b10c3 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -192,9 +192,6 @@ static inline int erofs_wait_on_workgroup_freezed(struct erofs_workgroup *grp) /* hard limit of pages per compressed cluster */ #define Z_EROFS_CLUSTER_MAX_PAGES (CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT) -#define EROFS_PCPUBUF_NR_PAGES Z_EROFS_CLUSTER_MAX_PAGES -#else -#define EROFS_PCPUBUF_NR_PAGES 0 #endif /* !CONFIG_EROFS_FS_ZIP */ /* we strictly follow PAGE_SIZE and no buffer head yet */ @@ -399,24 +396,16 @@ int erofs_namei(struct inode *dir, struct qstr *name, /* dir.c */ extern const struct file_operations erofs_dir_fops; +/* pcpubuf.c */ +void *erofs_get_pcpubuf(unsigned int requiredpages); +void erofs_put_pcpubuf(void *ptr); +int erofs_pcpubuf_growsize(unsigned int nrpages); +void erofs_pcpubuf_init(void); +void erofs_pcpubuf_exit(void); + /* utils.c / zdata.c */ struct page *erofs_allocpage(struct list_head *pool, gfp_t gfp); -#if (EROFS_PCPUBUF_NR_PAGES > 0) -void *erofs_get_pcpubuf(unsigned int pagenr); -#define erofs_put_pcpubuf(buf) do { \ - (void)&(buf); \ - preempt_enable(); \ -} while (0) -#else -static inline void *erofs_get_pcpubuf(unsigned int pagenr) -{ - return ERR_PTR(-EOPNOTSUPP); -} - -#define erofs_put_pcpubuf(buf) do {} while (0) -#endif - #ifdef CONFIG_EROFS_FS_ZIP int erofs_workgroup_put(struct erofs_workgroup *grp); struct erofs_workgroup *erofs_find_workgroup(struct super_block *sb, diff --git a/fs/erofs/pcpubuf.c b/fs/erofs/pcpubuf.c new file mode 100644 index 000000000000..6c885575128a --- /dev/null +++ b/fs/erofs/pcpubuf.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) Gao Xiang + * + * For low-latency decompression algorithms (e.g. lz4), reserve consecutive + * per-CPU virtual memory (in pages) in advance to store such inplace I/O + * data if inplace decompression is failed (due to unmet inplace margin for + * example). + */ +#include "internal.h" + +struct erofs_pcpubuf { + raw_spinlock_t lock; + void *ptr; + struct page **pages; + unsigned int nrpages; +}; + +static DEFINE_PER_CPU(struct erofs_pcpubuf, erofs_pcb); + +void *erofs_get_pcpubuf(unsigned int requiredpages) + __acquires(pcb->lock) +{ + struct erofs_pcpubuf *pcb = &get_cpu_var(erofs_pcb); + + raw_spin_lock(&pcb->lock); + /* check if the per-CPU buffer is too small */ + if (requiredpages > pcb->nrpages) { + raw_spin_unlock(&pcb->lock); + put_cpu_var(erofs_pcb); + /* (for sparse checker) pretend pcb->lock is still taken */ + __acquire(pcb->lock); + return NULL; + } + return pcb->ptr; +} + +void erofs_put_pcpubuf(void *ptr) __releases(pcb->lock) +{ + struct erofs_pcpubuf *pcb = &per_cpu(erofs_pcb, smp_processor_id()); + + DBG_BUGON(pcb->ptr != ptr); + raw_spin_unlock(&pcb->lock); + put_cpu_var(erofs_pcb); +} + +/* the next step: support per-CPU page buffers hotplug */ +int erofs_pcpubuf_growsize(unsigned int nrpages) +{ + static DEFINE_MUTEX(pcb_resize_mutex); + static unsigned int pcb_nrpages; + LIST_HEAD(pagepool); + int delta, cpu, ret, i; + + mutex_lock(&pcb_resize_mutex); + delta = nrpages - pcb_nrpages; + ret = 0; + /* avoid shrinking pcpubuf, since no idea how many fses rely on */ + if (delta <= 0) + goto out; + + for_each_possible_cpu(cpu) { + struct erofs_pcpubuf *pcb = &per_cpu(erofs_pcb, cpu); + struct page **pages, **oldpages; + void *ptr, *old_ptr; + + pages = kmalloc_array(nrpages, sizeof(*pages), GFP_KERNEL); + if (!pages) { + ret = -ENOMEM; + break; + } + + for (i = 0; i < nrpages; ++i) { + pages[i] = erofs_allocpage(&pagepool, GFP_KERNEL); + if (!pages[i]) { + ret = -ENOMEM; + oldpages = pages; + goto free_pagearray; + } + } + ptr = vmap(pages, nrpages, VM_MAP, PAGE_KERNEL); + if (!ptr) { + ret = -ENOMEM; + oldpages = pages; + goto free_pagearray; + } + raw_spin_lock(&pcb->lock); + old_ptr = pcb->ptr; + pcb->ptr = ptr; + oldpages = pcb->pages; + pcb->pages = pages; + i = pcb->nrpages; + pcb->nrpages = nrpages; + raw_spin_unlock(&pcb->lock); + + if (!oldpages) { + DBG_BUGON(old_ptr); + continue; + } + + if (old_ptr) + vunmap(old_ptr); +free_pagearray: + while (i) + list_add(&oldpages[--i]->lru, &pagepool); + kfree(oldpages); + if (ret) + break; + } + pcb_nrpages = nrpages; + put_pages_list(&pagepool); +out: + mutex_unlock(&pcb_resize_mutex); + return ret; +} + +void erofs_pcpubuf_init(void) +{ + int cpu; + + for_each_possible_cpu(cpu) { + struct erofs_pcpubuf *pcb = &per_cpu(erofs_pcb, cpu); + + raw_spin_lock_init(&pcb->lock); + } +} + +void erofs_pcpubuf_exit(void) +{ + int cpu, i; + + for_each_possible_cpu(cpu) { + struct erofs_pcpubuf *pcb = &per_cpu(erofs_pcb, cpu); + + if (pcb->ptr) { + vunmap(pcb->ptr); + pcb->ptr = NULL; + } + if (!pcb->pages) + continue; + + for (i = 0; i < pcb->nrpages; ++i) + if (pcb->pages[i]) + put_page(pcb->pages[i]); + kfree(pcb->pages); + pcb->pages = NULL; + } +} diff --git a/fs/erofs/super.c b/fs/erofs/super.c index ba63008b2c28..f5c0be845bd7 100644 --- a/fs/erofs/super.c +++ b/fs/erofs/super.c @@ -668,6 +668,7 @@ static int __init erofs_module_init(void) if (err) goto shrinker_err; + erofs_pcpubuf_init(); err = z_erofs_init_zip_subsystem(); if (err) goto zip_err; @@ -697,6 +698,7 @@ static void __exit erofs_module_exit(void) /* Ensure all RCU free inodes are safe before cache is destroyed. */ rcu_barrier(); kmem_cache_destroy(erofs_inode_cachep); + erofs_pcpubuf_exit(); } /* get filesystem statistics */ diff --git a/fs/erofs/utils.c b/fs/erofs/utils.c index aab4a607f028..160554accdfb 100644 --- a/fs/erofs/utils.c +++ b/fs/erofs/utils.c @@ -20,18 +20,6 @@ struct page *erofs_allocpage(struct list_head *pool, gfp_t gfp) return page; } -#if (EROFS_PCPUBUF_NR_PAGES > 0) -static struct { - u8 data[PAGE_SIZE * EROFS_PCPUBUF_NR_PAGES]; -} ____cacheline_aligned_in_smp erofs_pcpubuf[NR_CPUS]; - -void *erofs_get_pcpubuf(unsigned int pagenr) -{ - preempt_disable(); - return &erofs_pcpubuf[smp_processor_id()].data[pagenr * PAGE_SIZE]; -} -#endif - #ifdef CONFIG_EROFS_FS_ZIP /* global shrink count (for all mounted EROFS instances) */ static atomic_long_t erofs_global_shrink_cnt; From e4d6726a4fc8c47d935d0eb30f6baa40aa4c601f Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:20 +0800 Subject: [PATCH 26/74] erofs: introduce physical cluster slab pools Since multiple pcluster sizes could be used at once, the number of compressed pages will become a variable factor. It's necessary to introduce slab pools rather than a single slab cache now. This limits the pclustersize to 1M (Z_EROFS_PCLUSTER_MAX_SIZE), and get rid of the obsolete EROFS_FS_CLUSTER_PAGE_LIMIT, which has no use now. Link: https://lore.kernel.org/r/20210407043927.10623-4-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/Kconfig | 14 ---- fs/erofs/erofs_fs.h | 3 + fs/erofs/internal.h | 3 - fs/erofs/zdata.c | 179 +++++++++++++++++++++++++++++--------------- fs/erofs/zdata.h | 14 ++-- 5 files changed, 127 insertions(+), 86 deletions(-) diff --git a/fs/erofs/Kconfig b/fs/erofs/Kconfig index 74b0aaa7114c..858b3339f381 100644 --- a/fs/erofs/Kconfig +++ b/fs/erofs/Kconfig @@ -76,17 +76,3 @@ config EROFS_FS_ZIP If you don't want to enable compression feature, say N. -config EROFS_FS_CLUSTER_PAGE_LIMIT - int "EROFS Cluster Pages Hard Limit" - depends on EROFS_FS_ZIP - range 1 256 - default "1" - help - Indicates maximum # of pages of a compressed - physical cluster. - - For example, if files in a image were compressed - into 8k-unit, hard limit should not be configured - less than 2. Otherwise, the image will be refused - to mount on this kernel. - diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h index 04010fb6b370..b766e65c9164 100644 --- a/fs/erofs/erofs_fs.h +++ b/fs/erofs/erofs_fs.h @@ -201,6 +201,9 @@ static inline unsigned int erofs_xattr_entry_size(struct erofs_xattr_entry *e) e->e_name_len + le16_to_cpu(e->e_value_size)); } +/* maximum supported size of a physical compression cluster */ +#define Z_EROFS_PCLUSTER_MAX_SIZE (1024 * 1024) + /* available compression algorithm types (for h_algorithmtype) */ enum { Z_EROFS_COMPRESSION_LZ4 = 0, diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index c88daf2b10c3..8c43fe34b92a 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -189,9 +189,6 @@ static inline int erofs_wait_on_workgroup_freezed(struct erofs_workgroup *grp) return v; } #endif /* !CONFIG_SMP */ - -/* hard limit of pages per compressed cluster */ -#define Z_EROFS_CLUSTER_MAX_PAGES (CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT) #endif /* !CONFIG_EROFS_FS_ZIP */ /* we strictly follow PAGE_SIZE and no buffer head yet */ diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index f93a23cfe257..2d65ef4253fe 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -9,6 +9,93 @@ #include +/* + * since pclustersize is variable for big pcluster feature, introduce slab + * pools implementation for different pcluster sizes. + */ +struct z_erofs_pcluster_slab { + struct kmem_cache *slab; + unsigned int maxpages; + char name[48]; +}; + +#define _PCLP(n) { .maxpages = n } + +static struct z_erofs_pcluster_slab pcluster_pool[] __read_mostly = { + _PCLP(1), _PCLP(4), _PCLP(16), _PCLP(64), _PCLP(128), + _PCLP(Z_EROFS_PCLUSTER_MAX_PAGES) +}; + +static void z_erofs_destroy_pcluster_pool(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcluster_pool); ++i) { + if (!pcluster_pool[i].slab) + continue; + kmem_cache_destroy(pcluster_pool[i].slab); + pcluster_pool[i].slab = NULL; + } +} + +static int z_erofs_create_pcluster_pool(void) +{ + struct z_erofs_pcluster_slab *pcs; + struct z_erofs_pcluster *a; + unsigned int size; + + for (pcs = pcluster_pool; + pcs < pcluster_pool + ARRAY_SIZE(pcluster_pool); ++pcs) { + size = struct_size(a, compressed_pages, pcs->maxpages); + + sprintf(pcs->name, "erofs_pcluster-%u", pcs->maxpages); + pcs->slab = kmem_cache_create(pcs->name, size, 0, + SLAB_RECLAIM_ACCOUNT, NULL); + if (pcs->slab) + continue; + + z_erofs_destroy_pcluster_pool(); + return -ENOMEM; + } + return 0; +} + +static struct z_erofs_pcluster *z_erofs_alloc_pcluster(unsigned int nrpages) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcluster_pool); ++i) { + struct z_erofs_pcluster_slab *pcs = pcluster_pool + i; + struct z_erofs_pcluster *pcl; + + if (nrpages > pcs->maxpages) + continue; + + pcl = kmem_cache_zalloc(pcs->slab, GFP_NOFS); + if (!pcl) + return ERR_PTR(-ENOMEM); + pcl->pclusterpages = nrpages; + return pcl; + } + return ERR_PTR(-EINVAL); +} + +static void z_erofs_free_pcluster(struct z_erofs_pcluster *pcl) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcluster_pool); ++i) { + struct z_erofs_pcluster_slab *pcs = pcluster_pool + i; + + if (pcl->pclusterpages > pcs->maxpages) + continue; + + kmem_cache_free(pcs->slab, pcl); + return; + } + DBG_BUGON(1); +} + /* * a compressed_pages[] placeholder in order to avoid * being filled with file pages for in-place decompression. @@ -36,12 +123,11 @@ typedef tagptr1_t compressed_page_t; tagptr_fold(compressed_page_t, page, 1) static struct workqueue_struct *z_erofs_workqueue __read_mostly; -static struct kmem_cache *pcluster_cachep __read_mostly; void z_erofs_exit_zip_subsystem(void) { destroy_workqueue(z_erofs_workqueue); - kmem_cache_destroy(pcluster_cachep); + z_erofs_destroy_pcluster_pool(); } static inline int z_erofs_init_workqueue(void) @@ -58,42 +144,16 @@ static inline int z_erofs_init_workqueue(void) return z_erofs_workqueue ? 0 : -ENOMEM; } -static void z_erofs_pcluster_init_once(void *ptr) -{ - struct z_erofs_pcluster *pcl = ptr; - struct z_erofs_collection *cl = z_erofs_primarycollection(pcl); - unsigned int i; - - mutex_init(&cl->lock); - cl->nr_pages = 0; - cl->vcnt = 0; - for (i = 0; i < Z_EROFS_CLUSTER_MAX_PAGES; ++i) - pcl->compressed_pages[i] = NULL; -} - -static void z_erofs_pcluster_init_always(struct z_erofs_pcluster *pcl) -{ - struct z_erofs_collection *cl = z_erofs_primarycollection(pcl); - - atomic_set(&pcl->obj.refcount, 1); - - DBG_BUGON(cl->nr_pages); - DBG_BUGON(cl->vcnt); -} - int __init z_erofs_init_zip_subsystem(void) { - pcluster_cachep = kmem_cache_create("erofs_compress", - Z_EROFS_WORKGROUP_SIZE, 0, - SLAB_RECLAIM_ACCOUNT, - z_erofs_pcluster_init_once); - if (pcluster_cachep) { - if (!z_erofs_init_workqueue()) - return 0; + int err = z_erofs_create_pcluster_pool(); - kmem_cache_destroy(pcluster_cachep); - } - return -ENOMEM; + if (err) + return err; + err = z_erofs_init_workqueue(); + if (err) + z_erofs_destroy_pcluster_pool(); + return err; } enum z_erofs_collectmode { @@ -178,7 +238,6 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, struct list_head *pagepool) { const struct z_erofs_pcluster *pcl = clt->pcl; - const unsigned int clusterpages = BIT(pcl->clusterbits); struct page **pages = clt->compressedpages; pgoff_t index = pcl->obj.index + (pages - pcl->compressed_pages); bool standalone = true; @@ -188,7 +247,7 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, if (clt->mode < COLLECT_PRIMARY_FOLLOWED) return; - for (; pages < pcl->compressed_pages + clusterpages; ++pages) { + for (; pages < pcl->compressed_pages + pcl->pclusterpages; ++pages) { struct page *page; compressed_page_t t; struct page *newpage = NULL; @@ -248,14 +307,13 @@ int erofs_try_to_free_all_cached_pages(struct erofs_sb_info *sbi, struct z_erofs_pcluster *const pcl = container_of(grp, struct z_erofs_pcluster, obj); struct address_space *const mapping = MNGD_MAPPING(sbi); - const unsigned int clusterpages = BIT(pcl->clusterbits); int i; /* * refcount of workgroup is now freezed as 1, * therefore no need to worry about available decompression users. */ - for (i = 0; i < clusterpages; ++i) { + for (i = 0; i < pcl->pclusterpages; ++i) { struct page *page = pcl->compressed_pages[i]; if (!page) @@ -283,13 +341,12 @@ int erofs_try_to_free_cached_page(struct address_space *mapping, struct page *page) { struct z_erofs_pcluster *const pcl = (void *)page_private(page); - const unsigned int clusterpages = BIT(pcl->clusterbits); int ret = 0; /* 0 - busy */ if (erofs_workgroup_try_to_freeze(&pcl->obj, 1)) { unsigned int i; - for (i = 0; i < clusterpages; ++i) { + for (i = 0; i < pcl->pclusterpages; ++i) { if (pcl->compressed_pages[i] == page) { WRITE_ONCE(pcl->compressed_pages[i], NULL); ret = 1; @@ -312,9 +369,9 @@ static inline bool z_erofs_try_inplace_io(struct z_erofs_collector *clt, struct page *page) { struct z_erofs_pcluster *const pcl = clt->pcl; - const unsigned int clusterpages = BIT(pcl->clusterbits); - while (clt->compressedpages < pcl->compressed_pages + clusterpages) { + while (clt->compressedpages < + pcl->compressed_pages + pcl->pclusterpages) { if (!cmpxchg(clt->compressedpages++, NULL, page)) return true; } @@ -434,12 +491,12 @@ static int z_erofs_register_collection(struct z_erofs_collector *clt, struct z_erofs_collection *cl; int err; - /* no available workgroup, let's allocate one */ - pcl = kmem_cache_alloc(pcluster_cachep, GFP_NOFS); - if (!pcl) - return -ENOMEM; + /* no available pcluster, let's allocate one */ + pcl = z_erofs_alloc_pcluster(map->m_plen >> PAGE_SHIFT); + if (IS_ERR(pcl)) + return PTR_ERR(pcl); - z_erofs_pcluster_init_always(pcl); + atomic_set(&pcl->obj.refcount, 1); pcl->obj.index = map->m_pa >> PAGE_SHIFT; pcl->length = (map->m_llen << Z_EROFS_PCLUSTER_LENGTH_BIT) | @@ -451,8 +508,6 @@ static int z_erofs_register_collection(struct z_erofs_collector *clt, else pcl->algorithmformat = Z_EROFS_COMPRESSION_SHIFTED; - pcl->clusterbits = 0; - /* new pclusters should be claimed as type 1, primary and followed */ pcl->next = clt->owned_head; clt->mode = COLLECT_PRIMARY_FOLLOWED; @@ -464,12 +519,13 @@ static int z_erofs_register_collection(struct z_erofs_collector *clt, * lock all primary followed works before visible to others * and mutex_trylock *never* fails for a new pcluster. */ - mutex_trylock(&cl->lock); + mutex_init(&cl->lock); + DBG_BUGON(!mutex_trylock(&cl->lock)); err = erofs_register_workgroup(inode->i_sb, &pcl->obj); if (err) { mutex_unlock(&cl->lock); - kmem_cache_free(pcluster_cachep, pcl); + z_erofs_free_pcluster(pcl); return -EAGAIN; } /* used to check tail merging loop due to corrupted images */ @@ -518,7 +574,7 @@ static int z_erofs_collector_begin(struct z_erofs_collector *clt, clt->compressedpages = clt->pcl->compressed_pages; if (clt->mode <= COLLECT_PRIMARY) /* cannot do in-place I/O */ - clt->compressedpages += Z_EROFS_CLUSTER_MAX_PAGES; + clt->compressedpages += clt->pcl->pclusterpages; return 0; } @@ -531,9 +587,8 @@ static void z_erofs_rcu_callback(struct rcu_head *head) struct z_erofs_collection *const cl = container_of(head, struct z_erofs_collection, rcu); - kmem_cache_free(pcluster_cachep, - container_of(cl, struct z_erofs_pcluster, - primary_collection)); + z_erofs_free_pcluster(container_of(cl, struct z_erofs_pcluster, + primary_collection)); } void erofs_workgroup_free_rcu(struct erofs_workgroup *grp) @@ -786,9 +841,8 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, struct list_head *pagepool) { struct erofs_sb_info *const sbi = EROFS_SB(sb); - const unsigned int clusterpages = BIT(pcl->clusterbits); struct z_erofs_pagevec_ctor ctor; - unsigned int i, outputsize, llen, nr_pages; + unsigned int i, inputsize, outputsize, llen, nr_pages; struct page *pages_onstack[Z_EROFS_VMAP_ONSTACK_PAGES]; struct page **pages, **compressed_pages, *page; @@ -868,7 +922,7 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, overlapped = false; compressed_pages = pcl->compressed_pages; - for (i = 0; i < clusterpages; ++i) { + for (i = 0; i < pcl->pclusterpages; ++i) { unsigned int pagenr; page = compressed_pages[i]; @@ -921,12 +975,13 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, partial = true; } + inputsize = pcl->pclusterpages * PAGE_SIZE; err = z_erofs_decompress(&(struct z_erofs_decompress_req) { .sb = sb, .in = compressed_pages, .out = pages, .pageofs_out = cl->pageofs, - .inputsize = PAGE_SIZE, + .inputsize = inputsize, .outputsize = outputsize, .alg = pcl->algorithmformat, .inplace_io = overlapped, @@ -935,7 +990,7 @@ static int z_erofs_decompress_pcluster(struct super_block *sb, out: /* must handle all compressed pages before ending pages */ - for (i = 0; i < clusterpages; ++i) { + for (i = 0; i < pcl->pclusterpages; ++i) { page = compressed_pages[i]; if (erofs_page_is_managed(sbi, page)) @@ -1237,7 +1292,7 @@ static void z_erofs_submit_queue(struct super_block *sb, pcl = container_of(owned_head, struct z_erofs_pcluster, next); cur = pcl->obj.index; - end = cur + BIT(pcl->clusterbits); + end = cur + pcl->pclusterpages; /* close the main owned chain at first */ owned_head = cmpxchg(&pcl->next, Z_EROFS_PCLUSTER_TAIL, diff --git a/fs/erofs/zdata.h b/fs/erofs/zdata.h index 658bda5efcda..3a008f1b9f78 100644 --- a/fs/erofs/zdata.h +++ b/fs/erofs/zdata.h @@ -9,6 +9,7 @@ #include "internal.h" #include "zpvec.h" +#define Z_EROFS_PCLUSTER_MAX_PAGES (Z_EROFS_PCLUSTER_MAX_SIZE / PAGE_SIZE) #define Z_EROFS_NR_INLINE_PAGEVECS 3 /* @@ -58,16 +59,17 @@ struct z_erofs_pcluster { /* A: point to next chained pcluster or TAILs */ z_erofs_next_pcluster_t next; - /* A: compressed pages (including multi-usage pages) */ - struct page *compressed_pages[Z_EROFS_CLUSTER_MAX_PAGES]; - /* A: lower limit of decompressed length and if full length or not */ unsigned int length; + /* I: physical cluster size in pages */ + unsigned short pclusterpages; + /* I: compression algorithm format */ unsigned char algorithmformat; - /* I: bit shift of physical cluster size */ - unsigned char clusterbits; + + /* A: compressed pages (can be cached or inplaced pages) */ + struct page *compressed_pages[]; }; #define z_erofs_primarycollection(pcluster) (&(pcluster)->primary_collection) @@ -81,8 +83,6 @@ struct z_erofs_pcluster { #define Z_EROFS_PCLUSTER_NIL (NULL) -#define Z_EROFS_WORKGROUP_SIZE sizeof(struct z_erofs_pcluster) - struct z_erofs_decompressqueue { struct super_block *sb; atomic_t pending_bios; From 57a75ccc50bf3191c189f89c6dca10d641b4377c Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:21 +0800 Subject: [PATCH 27/74] erofs: fix up inplace I/O pointer for big pcluster When picking up inplace I/O pages, it should be traversed in reverse order in aligned with the traversal order of file-backed online pages. Also, index should be updated together when preloading compressed pages. Previously, only page-sized pclustersize was supported so no problem at all. Also rename `compressedpages' to `icpage_ptr' to reflect its functionality. Link: https://lore.kernel.org/r/20210407043927.10623-5-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/zdata.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 2d65ef4253fe..2d2cbfac500b 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -203,7 +203,8 @@ struct z_erofs_collector { struct z_erofs_pcluster *pcl, *tailpcl; struct z_erofs_collection *cl; - struct page **compressedpages; + /* a pointer used to pick up inplace I/O pages */ + struct page **icpage_ptr; z_erofs_next_pcluster_t owned_head; enum z_erofs_collectmode mode; @@ -237,17 +238,19 @@ static void preload_compressed_pages(struct z_erofs_collector *clt, enum z_erofs_cache_alloctype type, struct list_head *pagepool) { - const struct z_erofs_pcluster *pcl = clt->pcl; - struct page **pages = clt->compressedpages; - pgoff_t index = pcl->obj.index + (pages - pcl->compressed_pages); + struct z_erofs_pcluster *pcl = clt->pcl; bool standalone = true; gfp_t gfp = (mapping_gfp_mask(mc) & ~__GFP_DIRECT_RECLAIM) | __GFP_NOMEMALLOC | __GFP_NORETRY | __GFP_NOWARN; + struct page **pages; + pgoff_t index; if (clt->mode < COLLECT_PRIMARY_FOLLOWED) return; - for (; pages < pcl->compressed_pages + pcl->pclusterpages; ++pages) { + pages = pcl->compressed_pages; + index = pcl->obj.index; + for (; index < pcl->obj.index + pcl->pclusterpages; ++index, ++pages) { struct page *page; compressed_page_t t; struct page *newpage = NULL; @@ -365,16 +368,14 @@ int erofs_try_to_free_cached_page(struct address_space *mapping, } /* page_type must be Z_EROFS_PAGE_TYPE_EXCLUSIVE */ -static inline bool z_erofs_try_inplace_io(struct z_erofs_collector *clt, - struct page *page) +static bool z_erofs_try_inplace_io(struct z_erofs_collector *clt, + struct page *page) { struct z_erofs_pcluster *const pcl = clt->pcl; - while (clt->compressedpages < - pcl->compressed_pages + pcl->pclusterpages) { - if (!cmpxchg(clt->compressedpages++, NULL, page)) + while (clt->icpage_ptr > pcl->compressed_pages) + if (!cmpxchg(--clt->icpage_ptr, NULL, page)) return true; - } return false; } @@ -572,9 +573,8 @@ static int z_erofs_collector_begin(struct z_erofs_collector *clt, z_erofs_pagevec_ctor_init(&clt->vector, Z_EROFS_NR_INLINE_PAGEVECS, clt->cl->pagevec, clt->cl->vcnt); - clt->compressedpages = clt->pcl->compressed_pages; - if (clt->mode <= COLLECT_PRIMARY) /* cannot do in-place I/O */ - clt->compressedpages += clt->pcl->pclusterpages; + /* since file-backed online pages are traversed in reverse order */ + clt->icpage_ptr = clt->pcl->compressed_pages + clt->pcl->pclusterpages; return 0; } From 850be2e6fbc33577dfc8e84d8397cccb893c56eb Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:22 +0800 Subject: [PATCH 28/74] erofs: add big physical cluster definition Big pcluster indicates the size of compressed data for each physical pcluster is no longer fixed as block size, but could be more than 1 block (more accurately, 1 logical pcluster) When big pcluster feature is enabled for head0/1, delta0 of the 1st non-head lcluster index will keep block count of this pcluster in lcluster size instead of 1. Or, the compressed size of pcluster should be 1 lcluster if pcluster has no non-head lcluster index. Also note that BIG_PCLUSTER feature reuses COMPR_CFGS feature since it depends on COMPR_CFGS and will be released together. Link: https://lore.kernel.org/r/20210407043927.10623-6-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/erofs_fs.h | 19 +++++++++++++++---- fs/erofs/internal.h | 1 + 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h index b766e65c9164..f9ac2060af9b 100644 --- a/fs/erofs/erofs_fs.h +++ b/fs/erofs/erofs_fs.h @@ -19,6 +19,7 @@ */ #define EROFS_FEATURE_INCOMPAT_LZ4_0PADDING 0x00000001 #define EROFS_FEATURE_INCOMPAT_COMPR_CFGS 0x00000002 +#define EROFS_FEATURE_INCOMPAT_BIG_PCLUSTER 0x00000002 #define EROFS_ALL_FEATURE_INCOMPAT EROFS_FEATURE_INCOMPAT_LZ4_0PADDING #define EROFS_SB_EXTSLOT_SIZE 16 @@ -214,17 +215,20 @@ enum { /* 14 bytes (+ length field = 16 bytes) */ struct z_erofs_lz4_cfgs { __le16 max_distance; - u8 reserved[12]; + __le16 max_pclusterblks; + u8 reserved[10]; } __packed; /* * bit 0 : COMPACTED_2B indexes (0 - off; 1 - on) * e.g. for 4k logical cluster size, 4B if compacted 2B is off; * (4B) + 2B + (4B) if compacted 2B is on. + * bit 1 : HEAD1 big pcluster (0 - off; 1 - on) + * bit 2 : HEAD2 big pcluster (0 - off; 1 - on) */ -#define Z_EROFS_ADVISE_COMPACTED_2B_BIT 0 - -#define Z_EROFS_ADVISE_COMPACTED_2B (1 << Z_EROFS_ADVISE_COMPACTED_2B_BIT) +#define Z_EROFS_ADVISE_COMPACTED_2B 0x0001 +#define Z_EROFS_ADVISE_BIG_PCLUSTER_1 0x0002 +#define Z_EROFS_ADVISE_BIG_PCLUSTER_2 0x0004 struct z_erofs_map_header { __le32 h_reserved1; @@ -279,6 +283,13 @@ enum { #define Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS 2 #define Z_EROFS_VLE_DI_CLUSTER_TYPE_BIT 0 +/* + * D0_CBLKCNT will be marked _only_ at the 1st non-head lcluster to store the + * compressed block count of a compressed extent (in logical clusters, aka. + * block count of a pcluster). + */ +#define Z_EROFS_VLE_DI_D0_CBLKCNT (1 << 11) + struct z_erofs_vle_decompressed_index { __le16 di_advise; /* where to decompress in the head cluster */ diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 8c43fe34b92a..2683709fdacd 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -225,6 +225,7 @@ static inline bool erofs_sb_has_##name(struct erofs_sb_info *sbi) \ EROFS_FEATURE_FUNCS(lz4_0padding, incompat, INCOMPAT_LZ4_0PADDING) EROFS_FEATURE_FUNCS(compr_cfgs, incompat, INCOMPAT_COMPR_CFGS) +EROFS_FEATURE_FUNCS(big_pcluster, incompat, INCOMPAT_BIG_PCLUSTER) EROFS_FEATURE_FUNCS(sb_chksum, compat, COMPAT_SB_CHKSUM) /* atomic flag definitions */ From 725d21c44d47d04defa4c1d5b52541e991fe9347 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:23 +0800 Subject: [PATCH 29/74] erofs: adjust per-CPU buffers according to max_pclusterblks Adjust per-CPU buffers on demand since big pcluster definition is available. Also, bail out unsupported pcluster size according to Z_EROFS_PCLUSTER_MAX_SIZE. Link: https://lore.kernel.org/r/20210407043927.10623-7-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/decompressor.c | 20 ++++++++++++++++---- fs/erofs/internal.h | 2 ++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 7292b1b130c6..562e05d7edc2 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -31,6 +31,7 @@ int z_erofs_load_lz4_config(struct super_block *sb, struct erofs_super_block *dsb, struct z_erofs_lz4_cfgs *lz4, int size) { + struct erofs_sb_info *sbi = EROFS_SB(sb); u16 distance; if (lz4) { @@ -39,16 +40,27 @@ int z_erofs_load_lz4_config(struct super_block *sb, return -EINVAL; } distance = le16_to_cpu(lz4->max_distance); + + sbi->lz4.max_pclusterblks = le16_to_cpu(lz4->max_pclusterblks); + if (!sbi->lz4.max_pclusterblks) { + sbi->lz4.max_pclusterblks = 1; /* reserved case */ + } else if (sbi->lz4.max_pclusterblks > + Z_EROFS_PCLUSTER_MAX_SIZE / EROFS_BLKSIZ) { + erofs_err(sb, "too large lz4 pclusterblks %u", + sbi->lz4.max_pclusterblks); + return -EINVAL; + } else if (sbi->lz4.max_pclusterblks >= 2) { + erofs_info(sb, "EXPERIMENTAL big pcluster feature in use. Use at your own risk!"); + } } else { distance = le16_to_cpu(dsb->u1.lz4_max_distance); + sbi->lz4.max_pclusterblks = 1; } - EROFS_SB(sb)->lz4.max_distance_pages = distance ? + sbi->lz4.max_distance_pages = distance ? DIV_ROUND_UP(distance, PAGE_SIZE) + 1 : LZ4_MAX_DISTANCE_PAGES; - - /* TODO: use max pclusterblks after bigpcluster is enabled */ - return erofs_pcpubuf_growsize(1); + return erofs_pcpubuf_growsize(sbi->lz4.max_pclusterblks); } static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 2683709fdacd..d510f8ff8f60 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -49,6 +49,8 @@ typedef u32 erofs_blk_t; struct erofs_sb_lz4_info { /* # of pages needed for EROFS lz4 rolling decompression */ u16 max_distance_pages; + /* maximum possible blocks for pclusters in the filesystem */ + u16 max_pclusterblks; }; struct erofs_sb_info { From 3cc2aca3bfc40d675d18310f0c0b57e31472b1b7 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:24 +0800 Subject: [PATCH 30/74] erofs: support parsing big pcluster compress indexes When INCOMPAT_BIG_PCLUSTER sb feature is enabled, legacy compress indexes will also have the same on-disk header compact indexes to keep per-file configurations instead of leaving it zeroed. If ADVISE_BIG_PCLUSTER is set for a file, CBLKCNT will be loaded for each pcluster in this file by parsing 1st non-head lcluster. Link: https://lore.kernel.org/r/20210407043927.10623-8-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/zmap.c | 79 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 73 insertions(+), 6 deletions(-) diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c index 4f504708c558..ee4345a86dca 100644 --- a/fs/erofs/zmap.c +++ b/fs/erofs/zmap.c @@ -10,8 +10,10 @@ int z_erofs_fill_inode(struct inode *inode) { struct erofs_inode *const vi = EROFS_I(inode); + struct erofs_sb_info *sbi = EROFS_SB(inode->i_sb); - if (vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY) { + if (!erofs_sb_has_big_pcluster(sbi) && + vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY) { vi->z_advise = 0; vi->z_algorithmtype[0] = 0; vi->z_algorithmtype[1] = 0; @@ -48,7 +50,8 @@ static int z_erofs_fill_inode_lazy(struct inode *inode) if (test_bit(EROFS_I_Z_INITED_BIT, &vi->flags)) goto out_unlock; - DBG_BUGON(vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY); + DBG_BUGON(!erofs_sb_has_big_pcluster(EROFS_SB(sb)) && + vi->datalayout == EROFS_INODE_FLAT_COMPRESSION_LEGACY); pos = ALIGN(iloc(EROFS_SB(sb), vi->nid) + vi->inode_isize + vi->xattr_isize, 8); @@ -95,7 +98,7 @@ struct z_erofs_maprecorder { u8 type; u16 clusterofs; u16 delta[2]; - erofs_blk_t pblk; + erofs_blk_t pblk, compressedlcs; }; static int z_erofs_reload_indexes(struct z_erofs_maprecorder *m, @@ -158,6 +161,15 @@ static int legacy_load_cluster_from_disk(struct z_erofs_maprecorder *m, case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: m->clusterofs = 1 << vi->z_logical_clusterbits; m->delta[0] = le16_to_cpu(di->di_u.delta[0]); + if (m->delta[0] & Z_EROFS_VLE_DI_D0_CBLKCNT) { + if (!(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1)) { + DBG_BUGON(1); + return -EFSCORRUPTED; + } + m->compressedlcs = m->delta[0] & + ~Z_EROFS_VLE_DI_D0_CBLKCNT; + m->delta[0] = 1; + } m->delta[1] = le16_to_cpu(di->di_u.delta[1]); break; case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: @@ -365,6 +377,58 @@ static int z_erofs_extent_lookback(struct z_erofs_maprecorder *m, return 0; } +static int z_erofs_get_extent_compressedlen(struct z_erofs_maprecorder *m, + unsigned int initial_lcn) +{ + struct erofs_inode *const vi = EROFS_I(m->inode); + struct erofs_map_blocks *const map = m->map; + const unsigned int lclusterbits = vi->z_logical_clusterbits; + unsigned long lcn; + int err; + + DBG_BUGON(m->type != Z_EROFS_VLE_CLUSTER_TYPE_PLAIN && + m->type != Z_EROFS_VLE_CLUSTER_TYPE_HEAD); + if (!(map->m_flags & EROFS_MAP_ZIPPED) || + !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1)) { + map->m_plen = 1 << lclusterbits; + return 0; + } + + lcn = m->lcn + 1; + if (m->compressedlcs) + goto out; + if (lcn == initial_lcn) + goto err_bonus_cblkcnt; + + err = z_erofs_load_cluster_from_disk(m, lcn); + if (err) + return err; + + switch (m->type) { + case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: + if (m->delta[0] != 1) + goto err_bonus_cblkcnt; + if (m->compressedlcs) + break; + /* fallthrough */ + default: + erofs_err(m->inode->i_sb, + "cannot found CBLKCNT @ lcn %lu of nid %llu", + lcn, vi->nid); + DBG_BUGON(1); + return -EFSCORRUPTED; + } +out: + map->m_plen = m->compressedlcs << lclusterbits; + return 0; +err_bonus_cblkcnt: + erofs_err(m->inode->i_sb, + "bogus CBLKCNT @ lcn %lu of nid %llu", + lcn, vi->nid); + DBG_BUGON(1); + return -EFSCORRUPTED; +} + int z_erofs_map_blocks_iter(struct inode *inode, struct erofs_map_blocks *map, int flags) @@ -376,6 +440,7 @@ int z_erofs_map_blocks_iter(struct inode *inode, }; int err = 0; unsigned int lclusterbits, endoff; + unsigned long initial_lcn; unsigned long long ofs, end; trace_z_erofs_map_blocks_iter_enter(inode, map, flags); @@ -394,10 +459,10 @@ int z_erofs_map_blocks_iter(struct inode *inode, lclusterbits = vi->z_logical_clusterbits; ofs = map->m_la; - m.lcn = ofs >> lclusterbits; + initial_lcn = ofs >> lclusterbits; endoff = ofs & ((1 << lclusterbits) - 1); - err = z_erofs_load_cluster_from_disk(&m, m.lcn); + err = z_erofs_load_cluster_from_disk(&m, initial_lcn); if (err) goto unmap_out; @@ -441,10 +506,12 @@ int z_erofs_map_blocks_iter(struct inode *inode, } map->m_llen = end - map->m_la; - map->m_plen = 1 << lclusterbits; map->m_pa = blknr_to_addr(m.pblk); map->m_flags |= EROFS_MAP_MAPPED; + err = z_erofs_get_extent_compressedlen(&m, initial_lcn); + if (err) + goto out; unmap_out: if (m.kaddr) kunmap_atomic(m.kaddr); From d4d480d7cc61524145ba34586ec04f8d0974dd59 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:25 +0800 Subject: [PATCH 31/74] erofs: support parsing big pcluster compact indexes Different from non-compact indexes, several lclusters are packed as the compact form at once and an unique base blkaddr is stored for each pack, so each lcluster index would take less space on avarage (e.g. 2 bytes for COMPACT_2B.) btw, that is also why BIG_PCLUSTER switch should be consistent for compact head0/1. Prior to big pcluster, the size of all pclusters was 1 lcluster. Therefore, when a new HEAD lcluster was scanned, blkaddr would be bumped by 1 lcluster. However, that way doesn't work anymore for big pcluster since we actually don't know the compressed size of pclusters in advance (before reading CBLKCNT lcluster). So, instead, let blkaddr of each pack be the first pcluster blkaddr with a valid CBLKCNT, in detail, 1) if CBLKCNT starts at the pack, this first valid pcluster is itself, e.g. _____________________________________________________________ |_CBLKCNT0_|_NONHEAD_| .. |_HEAD_|_CBLKCNT1_| ... |_HEAD_| ... ^ = blkaddr base ^ += CBLKCNT0 ^ += CBLKCNT1 2) if CBLKCNT doesn't start at the pack, the first valid pcluster is the next pcluster, e.g. _________________________________________________________ | NONHEAD_| .. |_HEAD_|_CBLKCNT0_| ... |_HEAD_|_HEAD_| ... ^ = blkaddr base ^ += CBLKCNT0 ^ += 1 When a CBLKCNT is found, blkaddr will be increased by CBLKCNT lclusters, or a new HEAD is found immediately, bump blkaddr by 1 instead (see the picture above.) Also noted if CBLKCNT is the end of the pack, instead of storing delta1 (distance of the next HEAD lcluster) as normal NONHEADs, it still uses the compressed block count (delta0) since delta1 can be calculated indirectly but the block count can't. Adjust decoding logic to fit big pcluster compact indexes as well. Link: https://lore.kernel.org/r/20210407043927.10623-9-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/zmap.c | 70 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 9 deletions(-) diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c index ee4345a86dca..9bf2c9170989 100644 --- a/fs/erofs/zmap.c +++ b/fs/erofs/zmap.c @@ -76,6 +76,22 @@ static int z_erofs_fill_inode_lazy(struct inode *inode) } vi->z_logical_clusterbits = LOG_BLOCK_SIZE + (h->h_clusterbits & 7); + if (!erofs_sb_has_big_pcluster(EROFS_SB(sb)) && + vi->z_advise & (Z_EROFS_ADVISE_BIG_PCLUSTER_1 | + Z_EROFS_ADVISE_BIG_PCLUSTER_2)) { + erofs_err(sb, "per-inode big pcluster without sb feature for nid %llu", + vi->nid); + err = -EFSCORRUPTED; + goto unmap_done; + } + if (vi->datalayout == EROFS_INODE_FLAT_COMPRESSION && + !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1) ^ + !(vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_2)) { + erofs_err(sb, "big pcluster head1/2 of compact indexes should be consistent for nid %llu", + vi->nid); + err = -EFSCORRUPTED; + goto unmap_done; + } /* paired with smp_mb() at the beginning of the function */ smp_mb(); set_bit(EROFS_I_Z_INITED_BIT, &vi->flags); @@ -206,6 +222,7 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m, unsigned int vcnt, base, lo, encodebits, nblk; int i; u8 *in, type; + bool big_pcluster; if (1 << amortizedshift == 4) vcnt = 2; @@ -214,6 +231,7 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m, else return -EOPNOTSUPP; + big_pcluster = vi->z_advise & Z_EROFS_ADVISE_BIG_PCLUSTER_1; encodebits = ((vcnt << amortizedshift) - sizeof(__le32)) * 8 / vcnt; base = round_down(eofs, vcnt << amortizedshift); in = m->kaddr + base; @@ -225,7 +243,15 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m, m->type = type; if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) { m->clusterofs = 1 << lclusterbits; - if (i + 1 != vcnt) { + if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT) { + if (!big_pcluster) { + DBG_BUGON(1); + return -EFSCORRUPTED; + } + m->compressedlcs = lo & ~Z_EROFS_VLE_DI_D0_CBLKCNT; + m->delta[0] = 1; + return 0; + } else if (i + 1 != (int)vcnt) { m->delta[0] = lo; return 0; } @@ -238,22 +264,48 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m, in, encodebits * (i - 1), &type); if (type != Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) lo = 0; + else if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT) + lo = 1; m->delta[0] = lo + 1; return 0; } m->clusterofs = lo; m->delta[0] = 0; /* figout out blkaddr (pblk) for HEAD lclusters */ - nblk = 1; - while (i > 0) { - --i; - lo = decode_compactedbits(lclusterbits, lomask, - in, encodebits * i, &type); - if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) - i -= lo; + if (!big_pcluster) { + nblk = 1; + while (i > 0) { + --i; + lo = decode_compactedbits(lclusterbits, lomask, + in, encodebits * i, &type); + if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) + i -= lo; - if (i >= 0) + if (i >= 0) + ++nblk; + } + } else { + nblk = 0; + while (i > 0) { + --i; + lo = decode_compactedbits(lclusterbits, lomask, + in, encodebits * i, &type); + if (type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD) { + if (lo & Z_EROFS_VLE_DI_D0_CBLKCNT) { + --i; + nblk += lo & ~Z_EROFS_VLE_DI_D0_CBLKCNT; + continue; + } + /* bigpcluster shouldn't have plain d0 == 1 */ + if (lo <= 1) { + DBG_BUGON(1); + return -EFSCORRUPTED; + } + i -= lo - 2; + continue; + } ++nblk; + } } in += (vcnt << amortizedshift) - sizeof(__le32); m->pblk = le32_to_cpu(*(__le32 *)in) + nblk; From 3337f637087fce04bcc5ba28f66abdefe21142fa Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:26 +0800 Subject: [PATCH 32/74] erofs: support decompress big pcluster for lz4 backend Prior to big pcluster, there was only one compressed page so it'd easy to map this. However, when big pcluster is enabled, more work needs to be done to handle multiple compressed pages. In detail, - (maptype 0) if there is only one compressed page + no need to copy inplace I/O, just map it directly what we did before; - (maptype 1) if there are more compressed pages + no need to copy inplace I/O, vmap such compressed pages instead; - (maptype 2) if inplace I/O needs to be copied, use per-CPU buffers for decompression then. Another thing is how to detect inplace decompression is feasable or not (it's still quite easy for non big pclusters), apart from the inplace margin calculation, inplace I/O page reusing order is also needed to be considered for each compressed page. Currently, if the compressed page is the xth page, it shouldn't be reused as [0 ... nrpages_out - nrpages_in + x], otherwise a full copy will be triggered. Although there are some extra optimization ideas for this, I'd like to make big pcluster work correctly first and obviously it can be further optimized later since it has nothing with the on-disk format at all. Link: https://lore.kernel.org/r/20210407043927.10623-10-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/decompressor.c | 220 ++++++++++++++++++++++------------------ fs/erofs/internal.h | 15 +++ 2 files changed, 139 insertions(+), 96 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 562e05d7edc2..ad3f31380e6b 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -119,44 +119,85 @@ static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, return kaddr ? 1 : 0; } -static void *generic_copy_inplace_data(struct z_erofs_decompress_req *rq, - u8 *src, unsigned int pageofs_in) +static void *z_erofs_handle_inplace_io(struct z_erofs_decompress_req *rq, + void *inpage, unsigned int *inputmargin, int *maptype, + bool support_0padding) { - /* - * if in-place decompression is ongoing, those decompressed - * pages should be copied in order to avoid being overlapped. - */ - struct page **in = rq->in; - u8 *const tmp = erofs_get_pcpubuf(1); - u8 *tmpp = tmp; - unsigned int inlen = rq->inputsize - pageofs_in; - unsigned int count = min_t(uint, inlen, PAGE_SIZE - pageofs_in); + unsigned int nrpages_in, nrpages_out; + unsigned int ofull, oend, inputsize, total, i, j; + struct page **in; + void *src, *tmp; - while (tmpp < tmp + inlen) { - if (!src) - src = kmap_atomic(*in); - memcpy(tmpp, src + pageofs_in, count); - kunmap_atomic(src); - src = NULL; - tmpp += count; - pageofs_in = 0; - count = PAGE_SIZE; - ++in; + inputsize = rq->inputsize; + nrpages_in = PAGE_ALIGN(inputsize) >> PAGE_SHIFT; + oend = rq->pageofs_out + rq->outputsize; + ofull = PAGE_ALIGN(oend); + nrpages_out = ofull >> PAGE_SHIFT; + + if (rq->inplace_io) { + if (rq->partial_decoding || !support_0padding || + ofull - oend < LZ4_DECOMPRESS_INPLACE_MARGIN(inputsize)) + goto docopy; + + for (i = 0; i < nrpages_in; ++i) { + DBG_BUGON(rq->in[i] == NULL); + for (j = 0; j < nrpages_out - nrpages_in + i; ++j) + if (rq->out[j] == rq->in[i]) + goto docopy; + } } - return tmp; + + if (nrpages_in <= 1) { + *maptype = 0; + return inpage; + } + kunmap_atomic(inpage); + might_sleep(); + src = erofs_vm_map_ram(rq->in, nrpages_in); + if (!src) + return ERR_PTR(-ENOMEM); + *maptype = 1; + return src; + +docopy: + /* Or copy compressed data which can be overlapped to per-CPU buffer */ + in = rq->in; + src = erofs_get_pcpubuf(nrpages_in); + if (!src) { + DBG_BUGON(1); + kunmap_atomic(inpage); + return ERR_PTR(-EFAULT); + } + + tmp = src; + total = rq->inputsize; + while (total) { + unsigned int page_copycnt = + min_t(unsigned int, total, PAGE_SIZE - *inputmargin); + + if (!inpage) + inpage = kmap_atomic(*in); + memcpy(tmp, inpage + *inputmargin, page_copycnt); + kunmap_atomic(inpage); + inpage = NULL; + tmp += page_copycnt; + total -= page_copycnt; + ++in; + *inputmargin = 0; + } + *maptype = 2; + return src; } static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) { - unsigned int inputmargin, inlen; - u8 *src; - bool copied, support_0padding; - int ret; + unsigned int inputmargin; + u8 *headpage, *src; + bool support_0padding; + int ret, maptype; - if (rq->inputsize > PAGE_SIZE) - return -EOPNOTSUPP; - - src = kmap_atomic(*rq->in); + DBG_BUGON(*rq->in == NULL); + headpage = kmap_atomic(*rq->in); inputmargin = 0; support_0padding = false; @@ -164,49 +205,36 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) if (erofs_sb_has_lz4_0padding(EROFS_SB(rq->sb))) { support_0padding = true; - while (!src[inputmargin & ~PAGE_MASK]) + while (!headpage[inputmargin & ~PAGE_MASK]) if (!(++inputmargin & ~PAGE_MASK)) break; if (inputmargin >= rq->inputsize) { - kunmap_atomic(src); + kunmap_atomic(headpage); return -EIO; } } - copied = false; - inlen = rq->inputsize - inputmargin; - if (rq->inplace_io) { - const uint oend = (rq->pageofs_out + - rq->outputsize) & ~PAGE_MASK; - const uint nr = PAGE_ALIGN(rq->pageofs_out + - rq->outputsize) >> PAGE_SHIFT; - - if (rq->partial_decoding || !support_0padding || - rq->out[nr - 1] != rq->in[0] || - rq->inputsize - oend < - LZ4_DECOMPRESS_INPLACE_MARGIN(inlen)) { - src = generic_copy_inplace_data(rq, src, inputmargin); - inputmargin = 0; - copied = true; - } - } + rq->inputsize -= inputmargin; + src = z_erofs_handle_inplace_io(rq, headpage, &inputmargin, &maptype, + support_0padding); + if (IS_ERR(src)) + return PTR_ERR(src); /* legacy format could compress extra data in a pcluster. */ if (rq->partial_decoding || !support_0padding) ret = LZ4_decompress_safe_partial(src + inputmargin, out, - inlen, rq->outputsize, - rq->outputsize); + rq->inputsize, rq->outputsize, rq->outputsize); else ret = LZ4_decompress_safe(src + inputmargin, out, - inlen, rq->outputsize); + rq->inputsize, rq->outputsize); if (ret != rq->outputsize) { erofs_err(rq->sb, "failed to decompress %d in[%u, %u] out[%u]", - ret, inlen, inputmargin, rq->outputsize); + ret, rq->inputsize, inputmargin, rq->outputsize); print_hex_dump(KERN_DEBUG, "[ in]: ", DUMP_PREFIX_OFFSET, - 16, 1, src + inputmargin, inlen, true); + 16, 1, src + inputmargin, rq->inputsize, true); print_hex_dump(KERN_DEBUG, "[out]: ", DUMP_PREFIX_OFFSET, 16, 1, out, rq->outputsize, true); @@ -215,10 +243,16 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) ret = -EIO; } - if (copied) - erofs_put_pcpubuf(src); - else + if (maptype == 0) { kunmap_atomic(src); + } else if (maptype == 1) { + vm_unmap_ram(src, PAGE_ALIGN(rq->inputsize) >> PAGE_SHIFT); + } else if (maptype == 2) { + erofs_put_pcpubuf(src); + } else { + DBG_BUGON(1); + return -EFAULT; + } return ret; } @@ -268,57 +302,51 @@ static int z_erofs_decompress_generic(struct z_erofs_decompress_req *rq, const struct z_erofs_decompressor *alg = decompressors + rq->alg; unsigned int dst_maptype; void *dst; - int ret, i; + int ret; - if (nrpages_out == 1 && !rq->inplace_io) { - DBG_BUGON(!*rq->out); - dst = kmap_atomic(*rq->out); - dst_maptype = 0; - goto dstmap_out; - } - - /* - * For the case of small output size (especially much less - * than PAGE_SIZE), memcpy the decompressed data rather than - * compressed data is preferred. - */ - if (rq->outputsize <= PAGE_SIZE * 7 / 8) { - dst = erofs_get_pcpubuf(1); - if (IS_ERR(dst)) - return PTR_ERR(dst); - - rq->inplace_io = false; - ret = alg->decompress(rq, dst); - if (!ret) - copy_from_pcpubuf(rq->out, dst, rq->pageofs_out, - rq->outputsize); - - erofs_put_pcpubuf(dst); - return ret; + /* two optimized fast paths only for non bigpcluster cases yet */ + if (rq->inputsize <= PAGE_SIZE) { + if (nrpages_out == 1 && !rq->inplace_io) { + DBG_BUGON(!*rq->out); + dst = kmap_atomic(*rq->out); + dst_maptype = 0; + goto dstmap_out; + } + + /* + * For the case of small output size (especially much less + * than PAGE_SIZE), memcpy the decompressed data rather than + * compressed data is preferred. + */ + if (rq->outputsize <= PAGE_SIZE * 7 / 8) { + dst = erofs_get_pcpubuf(1); + if (IS_ERR(dst)) + return PTR_ERR(dst); + + rq->inplace_io = false; + ret = alg->decompress(rq, dst); + if (!ret) + copy_from_pcpubuf(rq->out, dst, rq->pageofs_out, + rq->outputsize); + + erofs_put_pcpubuf(dst); + return ret; + } } + /* general decoding path which can be used for all cases */ ret = alg->prepare_destpages(rq, pagepool); - if (ret < 0) { + if (ret < 0) return ret; - } else if (ret) { + if (ret) { dst = page_address(*rq->out); dst_maptype = 1; goto dstmap_out; } - i = 0; - while (1) { - dst = vm_map_ram(rq->out, nrpages_out, -1, PAGE_KERNEL); - - /* retry two more times (totally 3 times) */ - if (dst || ++i >= 3) - break; - vm_unmap_aliases(); - } - + dst = erofs_vm_map_ram(rq->out, nrpages_out); if (!dst) return -ENOMEM; - dst_maptype = 2; dstmap_out: diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index d510f8ff8f60..c8f904bbe985 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -396,6 +396,21 @@ int erofs_namei(struct inode *dir, struct qstr *name, /* dir.c */ extern const struct file_operations erofs_dir_fops; +static inline void *erofs_vm_map_ram(struct page **pages, unsigned int count) +{ + int retried = 0; + + while (1) { + void *p = vm_map_ram(pages, count, -1, PAGE_KERNEL); + + /* retry two more times (totally 3 times) */ + if (p || ++retried >= 3) + return p; + vm_unmap_aliases(); + } + return NULL; +} + /* pcpubuf.c */ void *erofs_get_pcpubuf(unsigned int requiredpages); void erofs_put_pcpubuf(void *ptr); From 50ea9ae0027c3a7b22ebe602c7a9c50c66a0eaeb Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 7 Apr 2021 12:39:27 +0800 Subject: [PATCH 33/74] erofs: enable big pcluster feature Enable COMPR_CFGS and BIG_PCLUSTER since the implementations are all settled properly. Link: https://lore.kernel.org/r/20210407043927.10623-11-xiang@kernel.org Acked-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/erofs_fs.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/erofs/erofs_fs.h b/fs/erofs/erofs_fs.h index f9ac2060af9b..32f79b14ef50 100644 --- a/fs/erofs/erofs_fs.h +++ b/fs/erofs/erofs_fs.h @@ -20,7 +20,10 @@ #define EROFS_FEATURE_INCOMPAT_LZ4_0PADDING 0x00000001 #define EROFS_FEATURE_INCOMPAT_COMPR_CFGS 0x00000002 #define EROFS_FEATURE_INCOMPAT_BIG_PCLUSTER 0x00000002 -#define EROFS_ALL_FEATURE_INCOMPAT EROFS_FEATURE_INCOMPAT_LZ4_0PADDING +#define EROFS_ALL_FEATURE_INCOMPAT \ + (EROFS_FEATURE_INCOMPAT_LZ4_0PADDING | \ + EROFS_FEATURE_INCOMPAT_COMPR_CFGS | \ + EROFS_FEATURE_INCOMPAT_BIG_PCLUSTER) #define EROFS_SB_EXTSLOT_SIZE 16 From f68c34ca41a19fb33fc6bfaee1b1b383264ad01c Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Mon, 10 May 2021 14:47:15 +0800 Subject: [PATCH 34/74] erofs: fix 1 lcluster-sized pcluster for big pcluster If the 1st NONHEAD lcluster of a pcluster isn't CBLKCNT lcluster type rather than a HEAD or PLAIN type instead, which means its pclustersize _must_ be 1 lcluster (since its uncompressed size < 2 lclusters), as illustrated below: HEAD HEAD / PLAIN lcluster type ____________ ____________ |_:__________|_________:__| file data (uncompressed) . . .____________. |____________| pcluster data (compressed) Such on-disk case was explained before [1] but missed to be handled properly in the runtime implementation. It can be observed if manually generating 1 lcluster-sized pcluster with 2 lclusters (thus CBLKCNT doesn't exist.) Let's fix it now. [1] https://lore.kernel.org/r/20210407043927.10623-1-xiang@kernel.org Link: https://lore.kernel.org/r/20210510064715.29123-1-xiang@kernel.org Fixes: cec6e93beadf ("erofs: support parsing big pcluster compress indexes") Reviewed-by: Chao Yu Signed-off-by: Gao Xiang --- fs/erofs/zmap.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c index 9bf2c9170989..a7da7ed4bda7 100644 --- a/fs/erofs/zmap.c +++ b/fs/erofs/zmap.c @@ -449,14 +449,31 @@ static int z_erofs_get_extent_compressedlen(struct z_erofs_maprecorder *m, lcn = m->lcn + 1; if (m->compressedlcs) goto out; - if (lcn == initial_lcn) - goto err_bonus_cblkcnt; err = z_erofs_load_cluster_from_disk(m, lcn); if (err) return err; + /* + * If the 1st NONHEAD lcluster has already been handled initially w/o + * valid compressedlcs, which means at least it mustn't be CBLKCNT, or + * an internal implemenatation error is detected. + * + * The following code can also handle it properly anyway, but let's + * BUG_ON in the debugging mode only for developers to notice that. + */ + DBG_BUGON(lcn == initial_lcn && + m->type == Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD); + switch (m->type) { + case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: + case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: + /* + * if the 1st NONHEAD lcluster is actually PLAIN or HEAD type + * rather than CBLKCNT, it's a 1 lcluster-sized pcluster. + */ + m->compressedlcs = 1; + break; case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD: if (m->delta[0] != 1) goto err_bonus_cblkcnt; From 8f2ef48ebc3320c3ee8fd8b9ed4e4114ff0c1a38 Mon Sep 17 00:00:00 2001 From: Namita Nair Date: Tue, 21 Nov 2023 12:48:09 -0800 Subject: [PATCH 35/74] fw-api: Get V2 HW header files for peach Bring in V2 HW header files for peach, also cleanup the header files 1. Remove comments; 2. Add appropriate copyright header; 3. Remove references to HW sensitive IP (structs, macros and etc). Change-Id: Iaa4db993ce08d04e5e571c740a4f30ff42890474 CRs-Fixed: 3691183 --- hw/peach/v2/HALcomdef.h | 49 + hw/peach/v2/HALhwio.h | 303 + hw/peach/v2/ack_report.h | 64 + hw/peach/v2/beryllium_top_reg.h | 23 + hw/peach/v2/buffer_addr_info.h | 57 + hw/peach/v2/ce_src_desc.h | 134 + hw/peach/v2/ce_stat_desc.h | 127 + hw/peach/v2/coex_rx_status.h | 141 + hw/peach/v2/coex_tx_req.h | 190 + hw/peach/v2/coex_tx_status.h | 120 + hw/peach/v2/com_dtypes.h | 178 + hw/peach/v2/eht_sig_usr_mu_mimo_info.h | 106 + hw/peach/v2/eht_sig_usr_ofdma_info.h | 120 + hw/peach/v2/eht_sig_usr_su_info.h | 85 + hw/peach/v2/expected_response.h | 204 + hw/peach/v2/he_sig_a_mu_dl_info.h | 183 + hw/peach/v2/he_sig_a_mu_ul_info.h | 113 + hw/peach/v2/he_sig_a_su_info.h | 218 + hw/peach/v2/he_sig_b1_mu_info.h | 50 + hw/peach/v2/he_sig_b2_mu_info.h | 106 + hw/peach/v2/he_sig_b2_ofdma_info.h | 106 + hw/peach/v2/ht_sig_info.h | 141 + hw/peach/v2/l_sig_a_info.h | 92 + hw/peach/v2/l_sig_b_info.h | 57 + hw/peach/v2/macrx_abort_request_info.h | 43 + hw/peach/v2/mactx_eht_sig_usr_mu_mimo.h | 87 + hw/peach/v2/mactx_eht_sig_usr_ofdma.h | 97 + hw/peach/v2/mactx_eht_sig_usr_su.h | 72 + hw/peach/v2/mactx_he_sig_a_mu_dl.h | 142 + hw/peach/v2/mactx_he_sig_a_mu_ul.h | 92 + hw/peach/v2/mactx_he_sig_a_su.h | 167 + hw/peach/v2/mactx_he_sig_b1_mu.h | 47 + hw/peach/v2/mactx_he_sig_b2_mu.h | 87 + hw/peach/v2/mactx_he_sig_b2_ofdma.h | 87 + hw/peach/v2/mactx_ht_sig.h | 112 + hw/peach/v2/mactx_l_sig_a.h | 77 + hw/peach/v2/mactx_l_sig_b.h | 52 + hw/peach/v2/mactx_phy_desc.h | 365 + hw/peach/v2/mactx_u_sig_eht_su_mu.h | 132 + hw/peach/v2/mactx_u_sig_eht_tb.h | 107 + hw/peach/v2/mactx_user_desc_common.h | 478 + hw/peach/v2/mactx_user_desc_per_user.h | 190 + hw/peach/v2/mactx_vht_sig_a.h | 122 + hw/peach/v2/mactx_vht_sig_b_mu160.h | 192 + hw/peach/v2/mactx_vht_sig_b_mu20.h | 57 + hw/peach/v2/mactx_vht_sig_b_mu40.h | 77 + hw/peach/v2/mactx_vht_sig_b_mu80.h | 112 + hw/peach/v2/mactx_vht_sig_b_su160.h | 232 + hw/peach/v2/mactx_vht_sig_b_su20.h | 57 + hw/peach/v2/mactx_vht_sig_b_su40.h | 82 + hw/peach/v2/mactx_vht_sig_b_su80.h | 132 + hw/peach/v2/mlo_sta_id_details.h | 64 + hw/peach/v2/mon_buffer_addr.h | 78 + hw/peach/v2/mon_destination_ring.h | 106 + hw/peach/v2/mon_drop.h | 71 + hw/peach/v2/mon_ingress_ring.h | 66 + hw/peach/v2/msmhwioreg.h | 24 + hw/peach/v2/no_ack_report.h | 120 + hw/peach/v2/ofdma_trigger_details.h | 834 + hw/peach/v2/pcu_ppdu_setup_init.h | 2282 +++ hw/peach/v2/pdg_response.h | 473 + hw/peach/v2/pdg_response_rate_setting.h | 414 + hw/peach/v2/pdg_tx_req.h | 99 + hw/peach/v2/phyrx_abort_request_info.h | 99 + hw/peach/v2/phyrx_common_user_info.h | 176 + hw/peach/v2/phyrx_he_sig_a_mu_dl.h | 142 + hw/peach/v2/phyrx_he_sig_a_mu_ul.h | 92 + hw/peach/v2/phyrx_he_sig_a_su.h | 167 + hw/peach/v2/phyrx_he_sig_b1_mu.h | 47 + hw/peach/v2/phyrx_he_sig_b2_mu.h | 87 + hw/peach/v2/phyrx_he_sig_b2_ofdma.h | 87 + hw/peach/v2/phyrx_ht_sig.h | 112 + hw/peach/v2/phyrx_l_sig_a.h | 77 + hw/peach/v2/phyrx_l_sig_b.h | 52 + hw/peach/v2/phyrx_location.h | 347 + .../v2/phyrx_other_receive_info_ru_details.h | 50 + hw/peach/v2/phyrx_pkt_end.h | 432 + hw/peach/v2/phyrx_pkt_end_info.h | 457 + hw/peach/v2/phyrx_rssi_legacy.h | 811 + hw/peach/v2/phyrx_user_info.h | 202 + hw/peach/v2/phyrx_vht_sig_a.h | 122 + hw/peach/v2/phytx_abort_request_info.h | 50 + hw/peach/v2/phytx_pkt_end.h | 241 + hw/peach/v2/phytx_ppdu_header_info_request.h | 52 + hw/peach/v2/receive_pkt_start_info.h | 99 + hw/peach/v2/receive_rssi_info.h | 477 + hw/peach/v2/receive_user_info.h | 269 + hw/peach/v2/received_response_user_15_8.h | 1126 ++ hw/peach/v2/received_response_user_23_16.h | 1126 ++ hw/peach/v2/received_response_user_31_24.h | 1126 ++ hw/peach/v2/received_response_user_36_32.h | 715 + hw/peach/v2/received_response_user_7_0.h | 1126 ++ hw/peach/v2/received_response_user_info.h | 218 + hw/peach/v2/received_trigger_info.h | 127 + hw/peach/v2/received_trigger_info_details.h | 162 + .../reo_descriptor_threshold_reached_status.h | 274 + hw/peach/v2/reo_destination_ring.h | 275 + hw/peach/v2/reo_destination_ring_with_pn.h | 233 + hw/peach/v2/reo_entrance_ring.h | 252 + hw/peach/v2/reo_flush_cache.h | 159 + hw/peach/v2/reo_flush_cache_status.h | 302 + hw/peach/v2/reo_flush_queue.h | 124 + hw/peach/v2/reo_flush_queue_status.h | 246 + hw/peach/v2/reo_flush_timeout_list.h | 117 + hw/peach/v2/reo_flush_timeout_list_status.h | 260 + hw/peach/v2/reo_get_queue_stats.h | 117 + hw/peach/v2/reo_get_queue_stats_status.h | 323 + hw/peach/v2/reo_unblock_cache.h | 117 + hw/peach/v2/reo_unblock_cache_status.h | 253 + hw/peach/v2/reo_update_rx_reo_queue.h | 425 + hw/peach/v2/reo_update_rx_reo_queue_status.h | 239 + hw/peach/v2/response_end_status.h | 294 + hw/peach/v2/response_start_status.h | 73 + hw/peach/v2/ru_allocation_160_info.h | 127 + hw/peach/v2/rx_attention.h | 379 + hw/peach/v2/rx_flow_search_entry.h | 225 + hw/peach/v2/rx_frame_1k_bitmap_ack.h | 337 + hw/peach/v2/rx_frame_bitmap_ack.h | 183 + hw/peach/v2/rx_frame_bitmap_req.h | 78 + hw/peach/v2/rx_location_info.h | 470 + hw/peach/v2/rx_mpdu_desc_info.h | 113 + hw/peach/v2/rx_mpdu_details.h | 115 + hw/peach/v2/rx_mpdu_end.h | 192 + hw/peach/v2/rx_mpdu_info.h | 835 + hw/peach/v2/rx_mpdu_link_ptr.h | 52 + hw/peach/v2/rx_mpdu_start.h | 617 + hw/peach/v2/rx_msdu_desc_info.h | 143 + hw/peach/v2/rx_msdu_details.h | 168 + hw/peach/v2/rx_msdu_end.h | 1097 ++ hw/peach/v2/rx_msdu_ext_desc_info.h | 71 + hw/peach/v2/rx_msdu_link.h | 917 ++ hw/peach/v2/rx_msdu_start.h | 309 + hw/peach/v2/rx_ppdu_ack_report.h | 57 + hw/peach/v2/rx_ppdu_end_user_stats.h | 703 + hw/peach/v2/rx_ppdu_end_user_stats_ext.h | 143 + hw/peach/v2/rx_ppdu_no_ack_report.h | 97 + hw/peach/v2/rx_ppdu_start.h | 78 + hw/peach/v2/rx_ppdu_start_user_info.h | 202 + hw/peach/v2/rx_preamble.h | 57 + hw/peach/v2/rx_reo_queue.h | 514 + hw/peach/v2/rx_reo_queue_1k.h | 269 + hw/peach/v2/rx_reo_queue_ext.h | 390 + hw/peach/v2/rx_response_required_info.h | 700 + .../v2/rx_rxpcu_classification_overview.h | 106 + hw/peach/v2/rx_start_param.h | 50 + hw/peach/v2/rx_timing_info.h | 71 + hw/peach/v2/rx_trig_info.h | 64 + hw/peach/v2/rxpcu_early_rx_indication.h | 64 + hw/peach/v2/rxpcu_ppdu_end_info.h | 861 + hw/peach/v2/rxpcu_ppdu_end_layout_info.h | 332 + hw/peach/v2/rxpt_classify_info.h | 134 + hw/peach/v2/seq_hwio.h | 53 + hw/peach/v2/soc_ce_seq_hwioreg.h | 13194 ++++++++++++++++ hw/peach/v2/tcl_data_cmd.h | 290 + hw/peach/v2/tcl_gse_cmd.h | 155 + hw/peach/v2/tcl_status_ring.h | 141 + hw/peach/v2/tlv_hdr.h | 416 + hw/peach/v2/tlv_tag_def.h | 510 + hw/peach/v2/tx_cbf_info.h | 458 + hw/peach/v2/tx_fes_setup.h | 511 + hw/peach/v2/tx_fes_status_1k_ba.h | 323 + hw/peach/v2/tx_fes_status_ack_or_ba.h | 155 + hw/peach/v2/tx_fes_status_end.h | 649 + hw/peach/v2/tx_fes_status_prot.h | 159 + hw/peach/v2/tx_fes_status_start.h | 127 + hw/peach/v2/tx_fes_status_start_ppdu.h | 169 + hw/peach/v2/tx_fes_status_start_prot.h | 162 + hw/peach/v2/tx_fes_status_user_ppdu.h | 204 + hw/peach/v2/tx_fes_status_user_response.h | 68 + hw/peach/v2/tx_flush_req.h | 64 + hw/peach/v2/tx_mpdu_start.h | 295 + hw/peach/v2/tx_msdu_extension.h | 372 + hw/peach/v2/tx_msdu_start.h | 253 + hw/peach/v2/tx_peer_entry.h | 289 + hw/peach/v2/tx_queue_extension.h | 316 + hw/peach/v2/tx_rate_stats_info.h | 106 + hw/peach/v2/tx_raw_or_native_frame_setup.h | 274 + hw/peach/v2/txpcu_buffer_basics.h | 50 + hw/peach/v2/txpcu_buffer_status.h | 68 + hw/peach/v2/txpcu_user_buffer_status.h | 75 + hw/peach/v2/u_sig_eht_su_mu_info.h | 169 + hw/peach/v2/u_sig_eht_tb_info.h | 134 + hw/peach/v2/unallocated_ru_160_info.h | 57 + hw/peach/v2/uniform_descriptor_header.h | 57 + hw/peach/v2/uniform_reo_cmd_header.h | 50 + hw/peach/v2/uniform_reo_status_header.h | 64 + hw/peach/v2/vht_sig_a_info.h | 155 + hw/peach/v2/vht_sig_b_mu160_info.h | 253 + hw/peach/v2/vht_sig_b_mu20_info.h | 64 + hw/peach/v2/vht_sig_b_mu40_info.h | 92 + hw/peach/v2/vht_sig_b_mu80_info.h | 141 + hw/peach/v2/vht_sig_b_su160_info.h | 309 + hw/peach/v2/vht_sig_b_su20_info.h | 64 + hw/peach/v2/vht_sig_b_su40_info.h | 99 + hw/peach/v2/vht_sig_b_su80_info.h | 169 + hw/peach/v2/wbm2sw_completion_ring_rx.h | 301 + hw/peach/v2/wbm2sw_completion_ring_tx.h | 255 + hw/peach/v2/wbm_buffer_ring.h | 52 + hw/peach/v2/wbm_link_descriptor_ring.h | 52 + hw/peach/v2/wbm_release_ring.h | 129 + hw/peach/v2/wbm_release_ring_rx.h | 310 + hw/peach/v2/wbm_release_ring_tx.h | 271 + hw/peach/v2/wcss_seq_hwiobase.h | 111 + hw/peach/v2/wcss_seq_hwioreg_umac.h | 2264 +++ hw/peach/v2/wcss_version.h | 16 + 205 files changed, 62515 insertions(+) create mode 100644 hw/peach/v2/HALcomdef.h create mode 100644 hw/peach/v2/HALhwio.h create mode 100644 hw/peach/v2/ack_report.h create mode 100644 hw/peach/v2/beryllium_top_reg.h create mode 100644 hw/peach/v2/buffer_addr_info.h create mode 100644 hw/peach/v2/ce_src_desc.h create mode 100644 hw/peach/v2/ce_stat_desc.h create mode 100644 hw/peach/v2/coex_rx_status.h create mode 100644 hw/peach/v2/coex_tx_req.h create mode 100644 hw/peach/v2/coex_tx_status.h create mode 100644 hw/peach/v2/com_dtypes.h create mode 100644 hw/peach/v2/eht_sig_usr_mu_mimo_info.h create mode 100644 hw/peach/v2/eht_sig_usr_ofdma_info.h create mode 100644 hw/peach/v2/eht_sig_usr_su_info.h create mode 100644 hw/peach/v2/expected_response.h create mode 100644 hw/peach/v2/he_sig_a_mu_dl_info.h create mode 100644 hw/peach/v2/he_sig_a_mu_ul_info.h create mode 100644 hw/peach/v2/he_sig_a_su_info.h create mode 100644 hw/peach/v2/he_sig_b1_mu_info.h create mode 100644 hw/peach/v2/he_sig_b2_mu_info.h create mode 100644 hw/peach/v2/he_sig_b2_ofdma_info.h create mode 100644 hw/peach/v2/ht_sig_info.h create mode 100644 hw/peach/v2/l_sig_a_info.h create mode 100644 hw/peach/v2/l_sig_b_info.h create mode 100644 hw/peach/v2/macrx_abort_request_info.h create mode 100644 hw/peach/v2/mactx_eht_sig_usr_mu_mimo.h create mode 100644 hw/peach/v2/mactx_eht_sig_usr_ofdma.h create mode 100644 hw/peach/v2/mactx_eht_sig_usr_su.h create mode 100644 hw/peach/v2/mactx_he_sig_a_mu_dl.h create mode 100644 hw/peach/v2/mactx_he_sig_a_mu_ul.h create mode 100644 hw/peach/v2/mactx_he_sig_a_su.h create mode 100644 hw/peach/v2/mactx_he_sig_b1_mu.h create mode 100644 hw/peach/v2/mactx_he_sig_b2_mu.h create mode 100644 hw/peach/v2/mactx_he_sig_b2_ofdma.h create mode 100644 hw/peach/v2/mactx_ht_sig.h create mode 100644 hw/peach/v2/mactx_l_sig_a.h create mode 100644 hw/peach/v2/mactx_l_sig_b.h create mode 100644 hw/peach/v2/mactx_phy_desc.h create mode 100644 hw/peach/v2/mactx_u_sig_eht_su_mu.h create mode 100644 hw/peach/v2/mactx_u_sig_eht_tb.h create mode 100644 hw/peach/v2/mactx_user_desc_common.h create mode 100644 hw/peach/v2/mactx_user_desc_per_user.h create mode 100644 hw/peach/v2/mactx_vht_sig_a.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_mu160.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_mu20.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_mu40.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_mu80.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_su160.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_su20.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_su40.h create mode 100644 hw/peach/v2/mactx_vht_sig_b_su80.h create mode 100644 hw/peach/v2/mlo_sta_id_details.h create mode 100644 hw/peach/v2/mon_buffer_addr.h create mode 100644 hw/peach/v2/mon_destination_ring.h create mode 100644 hw/peach/v2/mon_drop.h create mode 100644 hw/peach/v2/mon_ingress_ring.h create mode 100644 hw/peach/v2/msmhwioreg.h create mode 100644 hw/peach/v2/no_ack_report.h create mode 100644 hw/peach/v2/ofdma_trigger_details.h create mode 100644 hw/peach/v2/pcu_ppdu_setup_init.h create mode 100644 hw/peach/v2/pdg_response.h create mode 100644 hw/peach/v2/pdg_response_rate_setting.h create mode 100644 hw/peach/v2/pdg_tx_req.h create mode 100644 hw/peach/v2/phyrx_abort_request_info.h create mode 100644 hw/peach/v2/phyrx_common_user_info.h create mode 100644 hw/peach/v2/phyrx_he_sig_a_mu_dl.h create mode 100644 hw/peach/v2/phyrx_he_sig_a_mu_ul.h create mode 100644 hw/peach/v2/phyrx_he_sig_a_su.h create mode 100644 hw/peach/v2/phyrx_he_sig_b1_mu.h create mode 100644 hw/peach/v2/phyrx_he_sig_b2_mu.h create mode 100644 hw/peach/v2/phyrx_he_sig_b2_ofdma.h create mode 100644 hw/peach/v2/phyrx_ht_sig.h create mode 100644 hw/peach/v2/phyrx_l_sig_a.h create mode 100644 hw/peach/v2/phyrx_l_sig_b.h create mode 100644 hw/peach/v2/phyrx_location.h create mode 100644 hw/peach/v2/phyrx_other_receive_info_ru_details.h create mode 100644 hw/peach/v2/phyrx_pkt_end.h create mode 100644 hw/peach/v2/phyrx_pkt_end_info.h create mode 100644 hw/peach/v2/phyrx_rssi_legacy.h create mode 100644 hw/peach/v2/phyrx_user_info.h create mode 100644 hw/peach/v2/phyrx_vht_sig_a.h create mode 100644 hw/peach/v2/phytx_abort_request_info.h create mode 100644 hw/peach/v2/phytx_pkt_end.h create mode 100644 hw/peach/v2/phytx_ppdu_header_info_request.h create mode 100644 hw/peach/v2/receive_pkt_start_info.h create mode 100644 hw/peach/v2/receive_rssi_info.h create mode 100644 hw/peach/v2/receive_user_info.h create mode 100644 hw/peach/v2/received_response_user_15_8.h create mode 100644 hw/peach/v2/received_response_user_23_16.h create mode 100644 hw/peach/v2/received_response_user_31_24.h create mode 100644 hw/peach/v2/received_response_user_36_32.h create mode 100644 hw/peach/v2/received_response_user_7_0.h create mode 100644 hw/peach/v2/received_response_user_info.h create mode 100644 hw/peach/v2/received_trigger_info.h create mode 100644 hw/peach/v2/received_trigger_info_details.h create mode 100644 hw/peach/v2/reo_descriptor_threshold_reached_status.h create mode 100644 hw/peach/v2/reo_destination_ring.h create mode 100644 hw/peach/v2/reo_destination_ring_with_pn.h create mode 100644 hw/peach/v2/reo_entrance_ring.h create mode 100644 hw/peach/v2/reo_flush_cache.h create mode 100644 hw/peach/v2/reo_flush_cache_status.h create mode 100644 hw/peach/v2/reo_flush_queue.h create mode 100644 hw/peach/v2/reo_flush_queue_status.h create mode 100644 hw/peach/v2/reo_flush_timeout_list.h create mode 100644 hw/peach/v2/reo_flush_timeout_list_status.h create mode 100644 hw/peach/v2/reo_get_queue_stats.h create mode 100644 hw/peach/v2/reo_get_queue_stats_status.h create mode 100644 hw/peach/v2/reo_unblock_cache.h create mode 100644 hw/peach/v2/reo_unblock_cache_status.h create mode 100644 hw/peach/v2/reo_update_rx_reo_queue.h create mode 100644 hw/peach/v2/reo_update_rx_reo_queue_status.h create mode 100644 hw/peach/v2/response_end_status.h create mode 100644 hw/peach/v2/response_start_status.h create mode 100644 hw/peach/v2/ru_allocation_160_info.h create mode 100644 hw/peach/v2/rx_attention.h create mode 100644 hw/peach/v2/rx_flow_search_entry.h create mode 100644 hw/peach/v2/rx_frame_1k_bitmap_ack.h create mode 100644 hw/peach/v2/rx_frame_bitmap_ack.h create mode 100644 hw/peach/v2/rx_frame_bitmap_req.h create mode 100644 hw/peach/v2/rx_location_info.h create mode 100644 hw/peach/v2/rx_mpdu_desc_info.h create mode 100644 hw/peach/v2/rx_mpdu_details.h create mode 100644 hw/peach/v2/rx_mpdu_end.h create mode 100644 hw/peach/v2/rx_mpdu_info.h create mode 100644 hw/peach/v2/rx_mpdu_link_ptr.h create mode 100644 hw/peach/v2/rx_mpdu_start.h create mode 100644 hw/peach/v2/rx_msdu_desc_info.h create mode 100644 hw/peach/v2/rx_msdu_details.h create mode 100644 hw/peach/v2/rx_msdu_end.h create mode 100644 hw/peach/v2/rx_msdu_ext_desc_info.h create mode 100644 hw/peach/v2/rx_msdu_link.h create mode 100644 hw/peach/v2/rx_msdu_start.h create mode 100644 hw/peach/v2/rx_ppdu_ack_report.h create mode 100644 hw/peach/v2/rx_ppdu_end_user_stats.h create mode 100644 hw/peach/v2/rx_ppdu_end_user_stats_ext.h create mode 100644 hw/peach/v2/rx_ppdu_no_ack_report.h create mode 100644 hw/peach/v2/rx_ppdu_start.h create mode 100644 hw/peach/v2/rx_ppdu_start_user_info.h create mode 100644 hw/peach/v2/rx_preamble.h create mode 100644 hw/peach/v2/rx_reo_queue.h create mode 100644 hw/peach/v2/rx_reo_queue_1k.h create mode 100644 hw/peach/v2/rx_reo_queue_ext.h create mode 100644 hw/peach/v2/rx_response_required_info.h create mode 100644 hw/peach/v2/rx_rxpcu_classification_overview.h create mode 100644 hw/peach/v2/rx_start_param.h create mode 100644 hw/peach/v2/rx_timing_info.h create mode 100644 hw/peach/v2/rx_trig_info.h create mode 100644 hw/peach/v2/rxpcu_early_rx_indication.h create mode 100644 hw/peach/v2/rxpcu_ppdu_end_info.h create mode 100644 hw/peach/v2/rxpcu_ppdu_end_layout_info.h create mode 100644 hw/peach/v2/rxpt_classify_info.h create mode 100644 hw/peach/v2/seq_hwio.h create mode 100644 hw/peach/v2/soc_ce_seq_hwioreg.h create mode 100644 hw/peach/v2/tcl_data_cmd.h create mode 100644 hw/peach/v2/tcl_gse_cmd.h create mode 100644 hw/peach/v2/tcl_status_ring.h create mode 100644 hw/peach/v2/tlv_hdr.h create mode 100644 hw/peach/v2/tlv_tag_def.h create mode 100644 hw/peach/v2/tx_cbf_info.h create mode 100644 hw/peach/v2/tx_fes_setup.h create mode 100644 hw/peach/v2/tx_fes_status_1k_ba.h create mode 100644 hw/peach/v2/tx_fes_status_ack_or_ba.h create mode 100644 hw/peach/v2/tx_fes_status_end.h create mode 100644 hw/peach/v2/tx_fes_status_prot.h create mode 100644 hw/peach/v2/tx_fes_status_start.h create mode 100644 hw/peach/v2/tx_fes_status_start_ppdu.h create mode 100644 hw/peach/v2/tx_fes_status_start_prot.h create mode 100644 hw/peach/v2/tx_fes_status_user_ppdu.h create mode 100644 hw/peach/v2/tx_fes_status_user_response.h create mode 100644 hw/peach/v2/tx_flush_req.h create mode 100644 hw/peach/v2/tx_mpdu_start.h create mode 100644 hw/peach/v2/tx_msdu_extension.h create mode 100644 hw/peach/v2/tx_msdu_start.h create mode 100644 hw/peach/v2/tx_peer_entry.h create mode 100644 hw/peach/v2/tx_queue_extension.h create mode 100644 hw/peach/v2/tx_rate_stats_info.h create mode 100644 hw/peach/v2/tx_raw_or_native_frame_setup.h create mode 100644 hw/peach/v2/txpcu_buffer_basics.h create mode 100644 hw/peach/v2/txpcu_buffer_status.h create mode 100644 hw/peach/v2/txpcu_user_buffer_status.h create mode 100644 hw/peach/v2/u_sig_eht_su_mu_info.h create mode 100644 hw/peach/v2/u_sig_eht_tb_info.h create mode 100644 hw/peach/v2/unallocated_ru_160_info.h create mode 100644 hw/peach/v2/uniform_descriptor_header.h create mode 100644 hw/peach/v2/uniform_reo_cmd_header.h create mode 100644 hw/peach/v2/uniform_reo_status_header.h create mode 100644 hw/peach/v2/vht_sig_a_info.h create mode 100644 hw/peach/v2/vht_sig_b_mu160_info.h create mode 100644 hw/peach/v2/vht_sig_b_mu20_info.h create mode 100644 hw/peach/v2/vht_sig_b_mu40_info.h create mode 100644 hw/peach/v2/vht_sig_b_mu80_info.h create mode 100644 hw/peach/v2/vht_sig_b_su160_info.h create mode 100644 hw/peach/v2/vht_sig_b_su20_info.h create mode 100644 hw/peach/v2/vht_sig_b_su40_info.h create mode 100644 hw/peach/v2/vht_sig_b_su80_info.h create mode 100644 hw/peach/v2/wbm2sw_completion_ring_rx.h create mode 100644 hw/peach/v2/wbm2sw_completion_ring_tx.h create mode 100644 hw/peach/v2/wbm_buffer_ring.h create mode 100644 hw/peach/v2/wbm_link_descriptor_ring.h create mode 100644 hw/peach/v2/wbm_release_ring.h create mode 100644 hw/peach/v2/wbm_release_ring_rx.h create mode 100644 hw/peach/v2/wbm_release_ring_tx.h create mode 100644 hw/peach/v2/wcss_seq_hwiobase.h create mode 100644 hw/peach/v2/wcss_seq_hwioreg_umac.h create mode 100644 hw/peach/v2/wcss_version.h diff --git a/hw/peach/v2/HALcomdef.h b/hw/peach/v2/HALcomdef.h new file mode 100644 index 000000000000..0047e377aa48 --- /dev/null +++ b/hw/peach/v2/HALcomdef.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +#ifndef _ARM_ASM_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/hw/peach/v2/HALhwio.h b/hw/peach/v2/HALhwio.h new file mode 100644 index 000000000000..eb3039f11334 --- /dev/null +++ b/hw/peach/v2/HALhwio.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +#include "HALcomdef.h" + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +static uint32 Readdata, Val_temp, Val; +static uint32 Readdata1, Val_temp1, Val1; +static uint32 Readdata2, Val_temp2, Val2; + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) + +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + Readdata = HWIO_INX(base, hwiosym); \ + Val_temp = Readdata & ~mask1 & ~mask2; \ + Val = Val_temp | val1 | val2; \ + HWIO_##hwiosym##_OUT(base, Val); \ + } + +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + Readdata1 = HWIO_INX(base, hwiosym); \ + Val_temp1 = Readdata & ~mask1 & ~mask2 & ~mask3; \ + Val1 = Val_temp1 | val1 | val2 | val3; \ + HWIO_##hwiosym##_OUT(base, Val1); \ + } + +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + Readdata2 = HWIO_INX(base, hwiosym); \ + Val_temp2 = Readdata2 & ~mask1 & ~mask2 & ~mask3 & ~mask4; \ + Val2 = Val_temp2 | val1 | val2 | val3 | val4; \ + HWIO_##hwiosym##_OUT(base, Val2); \ + } + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + +#ifdef HAL_HWIO_EXTERNAL + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +#endif + diff --git a/hw/peach/v2/ack_report.h b/hw/peach/v2/ack_report.h new file mode 100644 index 000000000000..5620de716f88 --- /dev/null +++ b/hw/peach/v2/ack_report.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ + +#define NUM_OF_DWORDS_ACK_REPORT 1 + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, + ax_trigger_type : 4, + sr_ppdu : 1, + reserved : 7, + frame_control : 16; +#else + uint32_t frame_control : 16, + reserved : 7, + sr_ppdu : 1, + ax_trigger_type : 4, + selfgen_response_reason : 4; +#endif +}; + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/beryllium_top_reg.h b/hw/peach/v2/beryllium_top_reg.h new file mode 100644 index 000000000000..000b3f461645 --- /dev/null +++ b/hw/peach/v2/beryllium_top_reg.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef BERYLLIUM_TOP_REG_H +#define BERYLLIUM_TOP_REG_H + +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) + +#endif diff --git a/hw/peach/v2/buffer_addr_info.h b/hw/peach/v2/buffer_addr_info.h new file mode 100644 index 000000000000..6c30d247a42f --- /dev/null +++ b/hw/peach/v2/buffer_addr_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 4, + sw_buffer_cookie : 20; +#else + uint32_t buffer_addr_31_0 : 32; + uint32_t sw_buffer_cookie : 20, + return_buffer_manager : 4, + buffer_addr_39_32 : 8; +#endif +}; + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/ce_src_desc.h b/hw/peach/v2/ce_src_desc.h new file mode 100644 index 000000000000..52d633ab50a5 --- /dev/null +++ b/hw/peach/v2/ce_src_desc.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 1, + barrier_read : 1, + ce_res_1 : 2, + length : 16; + uint32_t fw_metadata : 16, + ce_res_2 : 16; + uint32_t ce_res_3 : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t src_buffer_low : 32; + uint32_t length : 16, + ce_res_1 : 2, + barrier_read : 1, + ce_res_0 : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + src_buffer_high : 8; + uint32_t ce_res_2 : 16, + fw_metadata : 16; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_3 : 20; +#endif +}; + +#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff + +#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff + +#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_SRC_SWAP_MSB 9 +#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_DEST_SWAP_MSB 10 +#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_GATHER_LSB 11 +#define CE_SRC_DESC_GATHER_MSB 11 +#define CE_SRC_DESC_GATHER_MASK 0x00000800 + +#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_0_LSB 12 +#define CE_SRC_DESC_CE_RES_0_MSB 12 +#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 + +#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 +#define CE_SRC_DESC_BARRIER_READ_LSB 13 +#define CE_SRC_DESC_BARRIER_READ_MSB 13 +#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 + +#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_1_LSB 14 +#define CE_SRC_DESC_CE_RES_1_MSB 15 +#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 + +#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_LENGTH_LSB 16 +#define CE_SRC_DESC_LENGTH_MSB 31 +#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 + +#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_FW_METADATA_LSB 0 +#define CE_SRC_DESC_FW_METADATA_MSB 15 +#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 +#define CE_SRC_DESC_CE_RES_2_LSB 16 +#define CE_SRC_DESC_CE_RES_2_MSB 31 +#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 + +#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c +#define CE_SRC_DESC_CE_RES_3_LSB 0 +#define CE_SRC_DESC_CE_RES_3_MSB 19 +#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff + +#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_RING_ID_LSB 20 +#define CE_SRC_DESC_RING_ID_MSB 27 +#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 +#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/ce_stat_desc.h b/hw/peach/v2/ce_stat_desc.h new file mode 100644 index 000000000000..0323137f0f62 --- /dev/null +++ b/hw/peach/v2/ce_stat_desc.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + barrier_read : 1, + ce_res_6 : 3, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +#else + uint32_t length : 16, + ce_res_6 : 3, + barrier_read : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + ce_res_5 : 8; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_7 : 4, + fw_metadata : 16; +#endif +}; + +#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_5_LSB 0 +#define CE_STAT_DESC_CE_RES_5_MSB 7 +#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff + +#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_SRC_SWAP_MSB 9 +#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_DEST_SWAP_MSB 10 +#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_GATHER_LSB 11 +#define CE_STAT_DESC_GATHER_MSB 11 +#define CE_STAT_DESC_GATHER_MASK 0x00000800 + +#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 +#define CE_STAT_DESC_BARRIER_READ_LSB 12 +#define CE_STAT_DESC_BARRIER_READ_MSB 12 +#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 + +#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_6_LSB 13 +#define CE_STAT_DESC_CE_RES_6_MSB 15 +#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 + +#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_LENGTH_LSB 16 +#define CE_STAT_DESC_LENGTH_MSB 31 +#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 + +#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff + +#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff + +#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_FW_METADATA_LSB 0 +#define CE_STAT_DESC_FW_METADATA_MSB 15 +#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_CE_RES_7_LSB 16 +#define CE_STAT_DESC_CE_RES_7_MSB 19 +#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 + +#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_RING_ID_LSB 20 +#define CE_STAT_DESC_RING_ID_MSB 27 +#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 +#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/coex_rx_status.h b/hw/peach/v2/coex_rx_status.h new file mode 100644 index 000000000000..f29875bc551f --- /dev/null +++ b/hw/peach/v2/coex_rx_status.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, + rx_with_tx_response : 1, + rx_rate : 5, + rx_bw : 3, + single_mpdu : 1, + filter_status : 1, + ampdu : 1, + directed : 1, + reserved_0 : 1, + rx_nss : 3, + rx_rssi : 8, + rx_type : 3, + retry_bit_setting : 1, + more_data_bit_setting : 1; + uint32_t remain_rx_packet_time : 16, + rx_remaining_fes_time : 16; +#else + uint32_t more_data_bit_setting : 1, + retry_bit_setting : 1, + rx_type : 3, + rx_rssi : 8, + rx_nss : 3, + reserved_0 : 1, + directed : 1, + ampdu : 1, + filter_status : 1, + single_mpdu : 1, + rx_bw : 3, + rx_rate : 5, + rx_with_tx_response : 1, + rx_mac_frame_status : 2; + uint32_t rx_remaining_fes_time : 16, + remain_rx_packet_time : 16; +#endif +}; + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x00000003 + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x00000004 + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x000000f8 + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x00000700 + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x00000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x00000800 + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x00000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x00001000 + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x00000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x00002000 + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x00000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x00004000 + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x00000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x00008000 + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x00070000 + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x07f80000 + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x38000000 + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x00000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x40000000 + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x00000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x80000000 + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x00000004 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 0 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 15 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x00000004 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 16 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 31 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/coex_tx_req.h b/hw/peach/v2/coex_tx_req.h new file mode 100644 index 000000000000..f5cdb3b400d8 --- /dev/null +++ b/hw/peach/v2/coex_tx_req.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, + min_tx_pwr : 8, + nss : 3, + tx_chain_mask : 8, + bw : 3, + reserved_0 : 2; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + reserved_1 : 2; + uint32_t tx_pwr_1 : 8, + alt_tx_pwr_1 : 8, + wlan_request_duration : 16; + uint32_t wlan_pkt_type : 4, + coex_tx_reason : 2, + response_frame_type : 5, + wlan_low_priority_slicing_allowed : 1, + wlan_high_priority_slicing_allowed : 1, + sch_tx_burst_ongoing : 1, + coex_tx_priority : 4, + reserved_3a : 14; +#else + uint32_t reserved_0 : 2, + bw : 3, + tx_chain_mask : 8, + nss : 3, + min_tx_pwr : 8, + tx_pwr : 8; + uint32_t reserved_1 : 2, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t wlan_request_duration : 16, + alt_tx_pwr_1 : 8, + tx_pwr_1 : 8; + uint32_t reserved_3a : 14, + coex_tx_priority : 4, + sch_tx_burst_ongoing : 1, + wlan_high_priority_slicing_allowed : 1, + wlan_low_priority_slicing_allowed : 1, + response_frame_type : 5, + coex_tx_reason : 2, + wlan_pkt_type : 4; +#endif +}; + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x00000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x000000ff + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x00000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_REQ_NSS_OFFSET 0x00000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x00070000 + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x00000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x07f80000 + +#define COEX_TX_REQ_BW_OFFSET 0x00000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x38000000 + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x00000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0xc0000000 + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 0 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 7 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_NSS_LSB 16 +#define COEX_TX_REQ_ALT_NSS_MSB 18 +#define COEX_TX_REQ_ALT_NSS_MASK 0x00070000 + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_BW_LSB 27 +#define COEX_TX_REQ_ALT_BW_MSB 29 +#define COEX_TX_REQ_ALT_BW_MASK 0x38000000 + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x00000004 +#define COEX_TX_REQ_RESERVED_1_LSB 30 +#define COEX_TX_REQ_RESERVED_1_MSB 31 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc0000000 + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x00000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x000000ff + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x00000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x0000ff00 + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x00000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0xffff0000 + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 0 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 3 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000c +#define COEX_TX_REQ_COEX_TX_REASON_LSB 4 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 5 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x00000030 + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000c +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 6 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 10 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c0 + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 11 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 11 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x00000800 + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 12 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 12 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x00001000 + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000c +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 13 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 13 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x00002000 + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000c +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 14 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 17 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c000 + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000c +#define COEX_TX_REQ_RESERVED_3A_LSB 18 +#define COEX_TX_REQ_RESERVED_3A_MSB 31 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/hw/peach/v2/coex_tx_status.h b/hw/peach/v2/coex_tx_status.h new file mode 100644 index 000000000000..4205e3a72256 --- /dev/null +++ b/hw/peach/v2/coex_tx_status.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ + +#define NUM_OF_DWORDS_COEX_TX_STATUS 3 + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, + tx_bw : 3, + tx_status_reason : 3, + tx_wait_ack : 1, + fes_tx_is_gen_frame : 1, + sch_tx_burst_ongoing : 1, + current_tx_duration : 16; + uint32_t next_rx_active_time : 16, + remaining_fes_time : 16; + uint32_t tx_antenna_mask : 8, + shared_ant_tx_pwr : 8, + other_ant_tx_pwr : 8, + reserved_2 : 8; +#else + uint32_t current_tx_duration : 16, + sch_tx_burst_ongoing : 1, + fes_tx_is_gen_frame : 1, + tx_wait_ack : 1, + tx_status_reason : 3, + tx_bw : 3, + reserved_0a : 7; + uint32_t remaining_fes_time : 16, + next_rx_active_time : 16; + uint32_t reserved_2 : 8, + other_ant_tx_pwr : 8, + shared_ant_tx_pwr : 8, + tx_antenna_mask : 8; +#endif +}; + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x00000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x0000007f + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x00000380 + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x00001c00 + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x00002000 + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x00000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x00004000 + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x00000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x00008000 + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x00000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0xffff0000 + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x00000004 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 0 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 15 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x00000004 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 16 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 31 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff0000 + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x00000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x000000ff + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x00000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x00000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x00ff0000 + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x00000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/com_dtypes.h b/hw/peach/v2/com_dtypes.h new file mode 100644 index 000000000000..2e06b1cefdc9 --- /dev/null +++ b/hw/peach/v2/com_dtypes.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + +#ifndef _UINT32_DEFINED + +typedef unsigned int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +typedef unsigned short word; + +typedef unsigned long dword; + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/peach/v2/eht_sig_usr_mu_mimo_info.h b/hw/peach/v2/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 000000000000..de8ff3f9edc5 --- /dev/null +++ b/hw/peach/v2/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + sta_coding : 1, + sta_spatial_config : 6, + reserved_0a : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0a : 1, + sta_spatial_config : 6, + sta_coding : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/eht_sig_usr_ofdma_info.h b/hw/peach/v2/eht_sig_usr_ofdma_info.h new file mode 100644 index 000000000000..6dfb89be9258 --- /dev/null +++ b/hw/peach/v2/eht_sig_usr_ofdma_info.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0b : 1, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/eht_sig_usr_su_info.h b/hw/peach/v2/eht_sig_usr_su_info.h new file mode 100644 index 000000000000..47efaa2937a2 --- /dev/null +++ b/hw/peach/v2/eht_sig_usr_su_info.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 9, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0b : 9, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; +#endif +}; + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/expected_response.h b/hw/peach/v2/expected_response.h new file mode 100644 index 000000000000..8f1db3fb5cba --- /dev/null +++ b/hw/peach/v2/expected_response.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 5 + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; + uint32_t tx_ad2_47_32 : 16, + expected_response_type : 5, + response_to_response : 3, + su_ba_user_number : 1, + response_info_part2_required : 1, + transmitted_bssid_check_en : 1, + reserved_1 : 5; + uint32_t ndp_sta_partial_aid_2_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid1_8_0 : 11; + uint32_t ast_index : 16, + capture_ack_ba_sounding : 1, + capture_sounding_1str_20mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_320mhz : 1, + reserved_3a : 9; + uint32_t fcs : 9, + reserved_4a : 1, + crc : 4, + scrambler_seed : 7, + reserved_4b : 11; +#else + uint32_t tx_ad2_31_0 : 32; + uint32_t reserved_1 : 5, + transmitted_bssid_check_en : 1, + response_info_part2_required : 1, + su_ba_user_number : 1, + response_to_response : 3, + expected_response_type : 5, + tx_ad2_47_32 : 16; + uint32_t ndp_sta_partial_aid1_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid_2_8_0 : 11; + uint32_t reserved_3a : 9, + capture_sounding_1str_320mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_20mhz : 1, + capture_ack_ba_sounding : 1, + ast_index : 16; + uint32_t reserved_4b : 11, + scrambler_seed : 7, + crc : 4, + reserved_4a : 1, + fcs : 9; +#endif +}; + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x00000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0xffffffff + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 15 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 16 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 20 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f0000 + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 21 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 23 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e00000 + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 24 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 24 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x01000000 + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 25 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 25 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x02000000 + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 26 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 26 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x04000000 + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 27 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf8000000 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x000007ff + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x001ff800 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0xffe00000 + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_AST_INDEX_LSB 0 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 15 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 16 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 16 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x00010000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 17 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 17 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x00020000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 18 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 18 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x00040000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 19 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 19 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x00080000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 20 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 20 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x00100000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 21 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 21 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x00200000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 22 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 22 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x00400000 + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 23 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff800000 + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x000001ff + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x00000200 + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x00003c00 + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x001fc000 + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0xffe00000 + +#endif diff --git a/hw/peach/v2/he_sig_a_mu_dl_info.h b/hw/peach/v2/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..dfee9225a12e --- /dev/null +++ b/hw/peach/v2/he_sig_a_mu_dl_info.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0a : 6, + doppler_indication : 1, + cp_ltf_size : 2, + comp_mode_sig_b : 1, + num_sig_b_symbols : 4, + transmit_bw : 3, + spatial_reuse : 4, + bss_color_id : 6, + dcm_of_sig_b : 1, + mcs_of_sig_b : 3, + dl_ul_flag : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + stbc : 1, + ldpc_extra_symbol : 1, + num_ltf_symbols : 3, + reserved_1a : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 + +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e + +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 + +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 + +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 + +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 + +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 + +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 + +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 + +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 + +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/he_sig_a_mu_ul_info.h b/hw/peach/v2/he_sig_a_mu_ul_info.h new file mode 100644 index 000000000000..7c59345eb72a --- /dev/null +++ b/hw/peach/v2/he_sig_a_mu_ul_info.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + bss_color_id : 6, + spatial_reuse : 16, + reserved_0a : 1, + transmit_bw : 2, + reserved_0b : 6; + uint32_t txop_duration : 7, + reserved_1a : 9, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + transmit_bw : 2, + reserved_0a : 1, + spatial_reuse : 16, + bss_color_id : 6, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + reserved_1a : 9, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e + +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 + +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 + +#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/he_sig_a_su_info.h b/hw/peach/v2/he_sig_a_su_info.h new file mode 100644 index 000000000000..b79ecd2f4aa1 --- /dev/null +++ b/hw/peach/v2/he_sig_a_su_info.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + nsts : 3, + cp_ltf_size : 2, + transmit_bw : 2, + spatial_reuse : 4, + reserved_0a : 1, + bss_color_id : 6, + dcm : 1, + transmit_mcs : 4, + dl_ul_flag : 1, + beam_change : 1, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + dot11ax_ext_ru_size : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + doppler_indication : 1, + reserved_1a : 1, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + txbf : 1, + stbc : 1, + ldpc_extra_symbol : 1, + coding : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 + +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 + +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 + +#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_DCM_MSB 7 +#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 + +#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 + +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 + +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 + +#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_NSTS_MSB 25 +#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 + +#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_CODING_MSB 7 +#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_STBC_MSB 9 +#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 + +#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 + +#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_CRC_MSB 19 +#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_TAIL_MSB 25 +#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 + +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/he_sig_b1_mu_info.h b/hw/peach/v2/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..78d2ed40afa7 --- /dev/null +++ b/hw/peach/v2/he_sig_b1_mu_info.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation : 8, + reserved_0 : 23, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 23, + ru_allocation : 8; +#endif +}; + +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff + +#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 + +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/he_sig_b2_mu_info.h b/hw/peach/v2/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..a808c847228f --- /dev/null +++ b/hw/peach/v2/he_sig_b2_mu_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 + +struct he_sig_b2_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 7, + nsts : 3, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + nsts : 3, + reserved_0a : 7, + sta_coding : 1, + reserved_set_to_1 : 1, + sta_mcs : 4, + sta_spatial_config : 4, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 + +#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 + +#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 +#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 +#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 + +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/he_sig_b2_ofdma_info.h b/hw/peach/v2/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..13d7e2e39aa5 --- /dev/null +++ b/hw/peach/v2/he_sig_b2_ofdma_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 + +struct he_sig_b2_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 10, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 10, + sta_coding : 1, + sta_dcm : 1, + sta_mcs : 4, + txbf : 1, + nsts : 3, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 + +#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 + +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 + +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 + +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/ht_sig_info.h b/hw/peach/v2/ht_sig_info.h new file mode 100644 index 000000000000..cc433337b2e4 --- /dev/null +++ b/hw/peach/v2/ht_sig_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + length : 16, + cbw : 1, + mcs : 7; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + signal_tail : 6, + crc : 8, + num_ext_sp_str : 2, + short_gi : 1, + fec_coding : 1, + stbc : 2, + aggregation : 1, + ht_reserved : 1, + not_sounding : 1, + smoothing : 1; +#endif +}; + +#define HT_SIG_INFO_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_MCS_LSB 0 +#define HT_SIG_INFO_MCS_MSB 6 +#define HT_SIG_INFO_MCS_MASK 0x0000007f + +#define HT_SIG_INFO_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_CBW_LSB 7 +#define HT_SIG_INFO_CBW_MSB 7 +#define HT_SIG_INFO_CBW_MASK 0x00000080 + +#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_LENGTH_LSB 8 +#define HT_SIG_INFO_LENGTH_MSB 23 +#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 + +#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_RESERVED_0_LSB 24 +#define HT_SIG_INFO_RESERVED_0_MSB 31 +#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 + +#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_SMOOTHING_LSB 0 +#define HT_SIG_INFO_SMOOTHING_MSB 0 +#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 + +#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 + +#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_HT_RESERVED_MSB 2 +#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 + +#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_AGGREGATION_LSB 3 +#define HT_SIG_INFO_AGGREGATION_MSB 3 +#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 + +#define HT_SIG_INFO_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_STBC_LSB 4 +#define HT_SIG_INFO_STBC_MSB 5 +#define HT_SIG_INFO_STBC_MASK 0x00000030 + +#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_FEC_CODING_LSB 6 +#define HT_SIG_INFO_FEC_CODING_MSB 6 +#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 + +#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_SHORT_GI_LSB 7 +#define HT_SIG_INFO_SHORT_GI_MSB 7 +#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 + +#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 + +#define HT_SIG_INFO_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_CRC_LSB 10 +#define HT_SIG_INFO_CRC_MSB 17 +#define HT_SIG_INFO_CRC_MASK 0x0003fc00 + +#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 +#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 + +#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_RESERVED_1_LSB 24 +#define HT_SIG_INFO_RESERVED_1_MSB 30 +#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 + +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/l_sig_a_info.h b/hw/peach/v2/l_sig_a_info.h new file mode 100644 index 000000000000..9b1c9def1828 --- /dev/null +++ b/hw/peach/v2/l_sig_a_info.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 2, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 2, + captured_implicit_sounding : 1, + pkt_type : 4, + tail : 6, + parity : 1, + length : 12, + lsig_reserved : 1, + rate : 4; +#endif +}; + +#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_RATE_LSB 0 +#define L_SIG_A_INFO_RATE_MSB 3 +#define L_SIG_A_INFO_RATE_MASK 0x0000000f + +#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 + +#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_LENGTH_LSB 5 +#define L_SIG_A_INFO_LENGTH_MSB 16 +#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 + +#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_PARITY_LSB 17 +#define L_SIG_A_INFO_PARITY_MSB 17 +#define L_SIG_A_INFO_PARITY_MASK 0x00020000 + +#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_TAIL_LSB 18 +#define L_SIG_A_INFO_TAIL_MSB 23 +#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_PKT_TYPE_MSB 27 +#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 + +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RESERVED_LSB 29 +#define L_SIG_A_INFO_RESERVED_MSB 30 +#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 + +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/l_sig_b_info.h b/hw/peach/v2/l_sig_b_info.h new file mode 100644 index 000000000000..ece176f0f999 --- /dev/null +++ b/hw/peach/v2/l_sig_b_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + length : 12, + reserved : 15, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 15, + length : 12, + rate : 4; +#endif +}; + +#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_RATE_LSB 0 +#define L_SIG_B_INFO_RATE_MSB 3 +#define L_SIG_B_INFO_RATE_MASK 0x0000000f + +#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_LENGTH_LSB 4 +#define L_SIG_B_INFO_LENGTH_MSB 15 +#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 + +#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RESERVED_LSB 16 +#define L_SIG_B_INFO_RESERVED_MSB 30 +#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 + +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/macrx_abort_request_info.h b/hw/peach/v2/macrx_abort_request_info.h new file mode 100644 index 000000000000..c3ee8e01c815 --- /dev/null +++ b/hw/peach/v2/macrx_abort_request_info.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +#else + uint16_t reserved_0 : 8, + macrx_abort_reason : 8; +#endif +}; + +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff + +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 + +#endif diff --git a/hw/peach/v2/mactx_eht_sig_usr_mu_mimo.h b/hw/peach/v2/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 000000000000..e10f98c5dc62 --- /dev/null +++ b/hw/peach/v2/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x00400000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/mactx_eht_sig_usr_ofdma.h b/hw/peach/v2/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 000000000000..20cf3dbe46d0 --- /dev/null +++ b/hw/peach/v2/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x000f0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x00100000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00200000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x00400000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/mactx_eht_sig_usr_su.h b/hw/peach/v2/mactx_eht_sig_usr_su.h new file mode 100644 index 000000000000..af2c25e75ac9 --- /dev/null +++ b/hw/peach/v2/mactx_eht_sig_usr_su.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 1 + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x000f0000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x00100000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x00200000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x7fc00000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_he_sig_a_mu_dl.h b/hw/peach/v2/mactx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..487cc46baf60 --- /dev/null +++ b/hw/peach/v2/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_he_sig_a_mu_ul.h b/hw/peach/v2/mactx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..1aba73b315dd --- /dev/null +++ b/hw/peach/v2/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_he_sig_a_su.h b/hw/peach/v2/mactx_he_sig_a_su.h new file mode 100644 index 000000000000..e49918fecd4b --- /dev/null +++ b/hw/peach/v2/mactx_he_sig_a_su.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_he_sig_b1_mu.h b/hw/peach/v2/mactx_he_sig_b1_mu.h new file mode 100644 index 000000000000..fb58c0a4db18 --- /dev/null +++ b/hw/peach/v2/mactx_he_sig_b1_mu.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 1 + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00 + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_he_sig_b2_mu.h b/hw/peach/v2/mactx_he_sig_b2_mu.h new file mode 100644 index 000000000000..4ee4527e6eab --- /dev/null +++ b/hw/peach/v2/mactx_he_sig_b2_mu.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/mactx_he_sig_b2_ofdma.h b/hw/peach/v2/mactx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..c9bf83f08b08 --- /dev/null +++ b/hw/peach/v2/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/mactx_ht_sig.h b/hw/peach/v2/mactx_ht_sig.h new file mode 100644 index 000000000000..f484d484b22e --- /dev/null +++ b/hw/peach/v2/mactx_ht_sig.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 5 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 17 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_l_sig_a.h b/hw/peach/v2/mactx_l_sig_a.h new file mode 100644 index 000000000000..d6b2fd9eb141 --- /dev/null +++ b/hw/peach/v2/mactx_l_sig_a.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 1 + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; +#else + struct l_sig_a_info mactx_l_sig_a_info_details; +#endif +}; + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_l_sig_b.h b/hw/peach/v2/mactx_l_sig_b.h new file mode 100644 index 000000000000..dc73e4949039 --- /dev/null +++ b/hw/peach/v2/mactx_l_sig_b.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 1 + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; +#else + struct l_sig_b_info mactx_l_sig_b_info_details; +#endif +}; + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_phy_desc.h b/hw/peach/v2/mactx_phy_desc.h new file mode 100644 index 000000000000..c69ee3e7f83a --- /dev/null +++ b/hw/peach/v2/mactx_phy_desc.h @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, + bf_type : 2, + wait_sifs : 2, + dot11b_preamble_type : 1, + pkt_type : 4, + su_or_mu : 2, + mu_type : 1, + bandwidth : 3, + channel_capture : 1; + uint32_t mcs : 4, + global_ofdma_mimo_enable : 1, + reserved_1a : 1, + stbc : 1, + dot11ax_su_extended : 1, + dot11ax_trigger_frame_embedded : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8, + measure_power : 1, + tpc_glut_self_cal : 1, + back_to_back_transmission_expected : 1, + heavy_clip_nss : 3, + txbf_per_packet_no_csd_no_walsh : 1; + uint32_t ndp : 2, + ul_flag : 1, + triggered : 1, + ap_pkt_bw : 3, + ru_position_start : 8, + pcu_ppdu_setup_start_reason : 3, + tlv_source : 1, + reserved_2a : 2, + nss : 3, + stream_offset : 3, + reserved_2b : 2, + clpc_enable : 1, + mu_ndp : 1, + response_expected : 1; + uint32_t rx_chain_mask : 8, + rx_chain_mask_valid : 1, + ant_sel_valid : 1, + ant_sel : 1, + cp_setting : 2, + he_ppdu_subtype : 2, + active_channel : 3, + generate_phyrx_tx_start_timing : 1, + ltf_size : 2, + ru_size_updated_v2 : 4, + reserved_3c : 1, + u_sig_puncture_pattern_encoding : 6; +#else + uint32_t channel_capture : 1, + bandwidth : 3, + mu_type : 1, + su_or_mu : 2, + pkt_type : 4, + dot11b_preamble_type : 1, + wait_sifs : 2, + bf_type : 2, + reserved_0a : 16; + uint32_t txbf_per_packet_no_csd_no_walsh : 1, + heavy_clip_nss : 3, + back_to_back_transmission_expected : 1, + tpc_glut_self_cal : 1, + measure_power : 1, + tx_pwr_unshared : 8, + tx_pwr_shared : 8, + dot11ax_trigger_frame_embedded : 1, + dot11ax_su_extended : 1, + stbc : 1, + reserved_1a : 1, + global_ofdma_mimo_enable : 1, + mcs : 4; + uint32_t response_expected : 1, + mu_ndp : 1, + clpc_enable : 1, + reserved_2b : 2, + stream_offset : 3, + nss : 3, + reserved_2a : 2, + tlv_source : 1, + pcu_ppdu_setup_start_reason : 3, + ru_position_start : 8, + ap_pkt_bw : 3, + triggered : 1, + ul_flag : 1, + ndp : 2; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_3c : 1, + ru_size_updated_v2 : 4, + ltf_size : 2, + generate_phyrx_tx_start_timing : 1, + active_channel : 3, + he_ppdu_subtype : 2, + cp_setting : 2, + ant_sel : 1, + ant_sel_valid : 1, + rx_chain_mask_valid : 1, + rx_chain_mask : 8; +#endif +}; + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x0000ffff + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x00030000 + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x00000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x000c0000 + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x00100000 + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x01e00000 + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x00000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x06000000 + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x08000000 + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x00000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x70000000 + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x80000000 + +#define MACTX_PHY_DESC_MCS_OFFSET 0x00000004 +#define MACTX_PHY_DESC_MCS_LSB 0 +#define MACTX_PHY_DESC_MCS_MSB 3 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x00000004 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 4 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 4 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x00000010 + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 5 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 5 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x00000020 + +#define MACTX_PHY_DESC_STBC_OFFSET 0x00000004 +#define MACTX_PHY_DESC_STBC_LSB 6 +#define MACTX_PHY_DESC_STBC_MSB 6 +#define MACTX_PHY_DESC_STBC_MASK 0x00000040 + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 7 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 7 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x00000080 + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 8 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 8 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x00000100 + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 9 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 16 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe00 + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 17 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 24 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe0000 + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x00000004 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 25 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 25 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x02000000 + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 26 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 26 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x04000000 + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 27 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 27 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x08000000 + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x00000004 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 28 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 30 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x70000000 + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 31 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 31 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x80000000 + +#define MACTX_PHY_DESC_NDP_OFFSET 0x00000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x00000003 + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x00000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x00000004 + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x00000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x00000008 + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x00000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000070 + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x00007f80 + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x00000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x00038000 + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x00000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x00040000 + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x00180000 + +#define MACTX_PHY_DESC_NSS_OFFSET 0x00000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x00e00000 + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x00000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x07000000 + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x18000000 + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x00000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x20000000 + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x00000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x40000000 + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x80000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 0 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 7 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 8 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 8 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x00000100 + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 9 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 9 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x00000200 + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ANT_SEL_LSB 10 +#define MACTX_PHY_DESC_ANT_SEL_MSB 10 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x00000400 + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_CP_SETTING_LSB 11 +#define MACTX_PHY_DESC_CP_SETTING_MSB 12 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x00001800 + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000c +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 13 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 14 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x00006000 + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 15 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 17 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x00038000 + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 18 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 18 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x00040000 + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000c +#define MACTX_PHY_DESC_LTF_SIZE_LSB 19 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 20 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x00180000 + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 21 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 24 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e00000 + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RESERVED_3C_LSB 25 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 25 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x02000000 + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#endif diff --git a/hw/peach/v2/mactx_u_sig_eht_su_mu.h b/hw/peach/v2/mactx_u_sig_eht_su_mu.h new file mode 100644 index 000000000000..94292c64f4c9 --- /dev/null +++ b/hw/peach/v2/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x00000007 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x01f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x02000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 8 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 8 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x00000100 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 9 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 10 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 16 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 27 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 29 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x38000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 30 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 30 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_u_sig_eht_tb.h b/hw/peach/v2/mactx_u_sig_eht_tb.h new file mode 100644 index 000000000000..f06f9d660587 --- /dev/null +++ b/hw/peach/v2/mactx_u_sig_eht_tb.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x00000007 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 10 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f8 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 11 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 15 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f800 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 16 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 30 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_user_desc_common.h b/hw/peach/v2/mactx_user_desc_common.h new file mode 100644 index 000000000000..e9c2a667c334 --- /dev/null +++ b/hw/peach/v2/mactx_user_desc_common.h @@ -0,0 +1,478 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + reserved_0b : 5, + ltf_size : 2, + reserved_0c : 3, + he_stf_long : 1, + reserved_0d : 7, + num_users_he_sigb_band0 : 8; + uint32_t num_ltf_symbols : 3, + reserved_1a : 5, + num_users_he_sigb_band1 : 8, + reserved_1b : 16; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + reserved : 2, + he_sigb_dcm : 1, + reserved_2b : 7, + he_sigb_compression : 1, + reserved_2c : 15; + uint32_t he_sigb_0_mcs : 3, + reserved_3a : 13, + num_he_sigb_sym : 5, + center_ru_0 : 1, + center_ru_1 : 1, + reserved_3b : 1, + ftm_en : 1, + pe_nss : 3, + pe_ltf_size : 2, + pe_content : 1, + pe_chain_csd_en : 1; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, + ndp_ru_tone_set_index : 7, + ndp_feedback_status : 1, + doppler_indication : 1, + reserved_14a : 7; + uint32_t spatial_reuse : 16, + reserved_15a : 16; +#else + uint32_t num_users_he_sigb_band0 : 8, + reserved_0d : 7, + he_stf_long : 1, + reserved_0c : 3, + ltf_size : 2, + reserved_0b : 5, + num_users : 6; + uint32_t reserved_1b : 16, + num_users_he_sigb_band1 : 8, + reserved_1a : 5, + num_ltf_symbols : 3; + uint32_t reserved_2c : 15, + he_sigb_compression : 1, + reserved_2b : 7, + he_sigb_dcm : 1, + reserved : 2, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t pe_chain_csd_en : 1, + pe_content : 1, + pe_ltf_size : 2, + pe_nss : 3, + ftm_en : 1, + reserved_3b : 1, + center_ru_1 : 1, + center_ru_0 : 1, + num_he_sigb_sym : 5, + reserved_3a : 13, + he_sigb_0_mcs : 3; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, + doppler_indication : 1, + ndp_feedback_status : 1, + ndp_ru_tone_set_index : 7, + num_data_symbols : 16; + uint32_t reserved_15a : 16, + spatial_reuse : 16; +#endif +}; + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x0000003f + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x000007c0 + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x00001800 + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x0000e000 + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x00010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x00fe0000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 2 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x00000007 + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 3 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f8 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 8 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 16 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff0000 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x00000038 + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x000000c0 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x00000100 + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x0000fe00 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x00010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0xfffe0000 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 0 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 2 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x00000007 + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 3 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff8 + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 16 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 20 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f0000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 21 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 21 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x00200000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 22 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 22 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x00400000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x00800000 + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 24 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 24 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x01000000 + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 25 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 27 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e000000 + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 28 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 29 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x30000000 + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 30 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 30 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x40000000 + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 31 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 31 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x80000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x00fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x00fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x0000ffff + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x007f0000 + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x00800000 + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x01000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0xfe000000 + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000003c +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 0 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 15 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000003c +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 16 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/mactx_user_desc_per_user.h b/hw/peach/v2/mactx_user_desc_per_user.h new file mode 100644 index 000000000000..9f22d33367ba --- /dev/null +++ b/hw/peach/v2/mactx_user_desc_per_user.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, + reserved_0a : 8; + uint32_t ru_start_index : 8, + ru_size : 4, + reserved_1b : 4, + ofdma_mu_mimo_enabled : 1, + nss : 3, + stream_offset : 3, + reserved_1c : 1, + mcs : 4, + dcm : 1, + reserved_1d : 3; + uint32_t fec_type : 1, + reserved_2a : 7, + user_bf_type : 2, + reserved_2b : 6, + drop_user_cbf : 1, + reserved_2c : 7, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_2d : 6; + uint32_t sw_peer_id : 16, + per_user_subband_mask : 16; +#else + uint32_t reserved_0a : 8, + psdu_length : 24; + uint32_t reserved_1d : 3, + dcm : 1, + mcs : 4, + reserved_1c : 1, + stream_offset : 3, + nss : 3, + ofdma_mu_mimo_enabled : 1, + reserved_1b : 4, + ru_size : 4, + ru_start_index : 8; + uint32_t reserved_2d : 6, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + reserved_2c : 7, + drop_user_cbf : 1, + reserved_2b : 6, + user_bf_type : 2, + reserved_2a : 7, + fec_type : 1; + uint32_t per_user_subband_mask : 16, + sw_peer_id : 16; +#endif +}; + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x00000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x00ffffff + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0xff000000 + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 0 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 7 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 8 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 11 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f00 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 12 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f000 + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 16 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 16 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x00010000 + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 17 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 19 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e0000 + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 20 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 22 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x00700000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x00800000 + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 24 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 27 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f000000 + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 28 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 28 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x10000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 29 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe0000000 + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x00000001 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x000000fe + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x00000300 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000fc00 + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x00010000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x00fe0000 + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x01000000 + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x02000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0xfc000000 + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000c +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 0 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 15 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000c +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 16 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 31 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_a.h b/hw/peach/v2/mactx_vht_sig_a.h new file mode 100644 index 000000000000..83aceb6dd650 --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_a.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_mu160.h b/hw/peach/v2/mactx_vht_sig_b_mu160.h new file mode 100644 index 000000000000..86f07a8692ec --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_mu160.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_mu20.h b/hw/peach/v2/mactx_vht_sig_b_mu20.h new file mode 100644 index 000000000000..880486d2cbaf --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_mu20.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 1 + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x0000ffff + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x000f0000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x1c000000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_mu40.h b/hw/peach/v2/mactx_vht_sig_b_mu40.h new file mode 100644 index 000000000000..e3ac2dab7201 --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_mu40.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x18000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_mu80.h b/hw/peach/v2/mactx_vht_sig_b_mu80.h new file mode 100644 index 000000000000..3a535da89d0e --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_mu80.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_su160.h b/hw/peach/v2/mactx_vht_sig_b_su160.h new file mode 100644 index 000000000000..b0354abed195 --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_su160.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_su20.h b/hw/peach/v2/mactx_vht_sig_b_su20.h new file mode 100644 index 000000000000..c12f02d6beb9 --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_su20.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 1 + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x000e0000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x7c000000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_su40.h b/hw/peach/v2/mactx_vht_sig_b_su40.h new file mode 100644 index 000000000000..3e66e9306365 --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_su40.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x00180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x78000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x78000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mactx_vht_sig_b_su80.h b/hw/peach/v2/mactx_vht_sig_b_su80.h new file mode 100644 index 000000000000..0bda57476790 --- /dev/null +++ b/hw/peach/v2/mactx_vht_sig_b_su80.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mlo_sta_id_details.h b/hw/peach/v2/mlo_sta_id_details.h new file mode 100644 index 000000000000..3a50ea9b66e6 --- /dev/null +++ b/hw/peach/v2/mlo_sta_id_details.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, + block_self_ml_sync : 1, + block_partner_ml_sync : 1, + nstr_mlo_sta_id_valid : 1, + reserved_0a : 3; +#else + uint16_t reserved_0a : 3, + nstr_mlo_sta_id_valid : 1, + block_partner_ml_sync : 1, + block_self_ml_sync : 1, + nstr_mlo_sta_id : 10; +#endif +}; + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + +#endif diff --git a/hw/peach/v2/mon_buffer_addr.h b/hw/peach/v2/mon_buffer_addr.h new file mode 100644 index 000000000000..1d89c9573f89 --- /dev/null +++ b/hw/peach/v2/mon_buffer_addr.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 3 + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t dma_length : 12, + reserved_2a : 4, + msdu_continuation : 1, + truncated : 1, + reserved_2b : 14; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reserved_2b : 14, + truncated : 1, + msdu_continuation : 1, + reserved_2a : 4, + dma_length : 12; +#endif +}; + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x00000fff + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x0000f000 + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x00010000 + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x00020000 + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0xfffc0000 + +#endif diff --git a/hw/peach/v2/mon_destination_ring.h b/hw/peach/v2/mon_destination_ring.h new file mode 100644 index 000000000000..145dce54fdc9 --- /dev/null +++ b/hw/peach/v2/mon_destination_ring.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t end_offset : 12, + reserved_3a : 2, + link_info : 2, + end_reason : 2, + initiator : 1, + empty_descriptor : 1, + ring_id : 8, + looping_count : 4; +#else + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t looping_count : 4, + ring_id : 8, + empty_descriptor : 1, + initiator : 1, + end_reason : 2, + link_info : 2, + reserved_3a : 2, + end_offset : 12; +#endif +}; + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 + +#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LINK_INFO_LSB 14 +#define MON_DESTINATION_RING_LINK_INFO_MSB 15 +#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/mon_drop.h b/hw/peach/v2/mon_drop.h new file mode 100644 index 000000000000..311f5c0982e7 --- /dev/null +++ b/hw/peach/v2/mon_drop.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ + +#define NUM_OF_DWORDS_MON_DROP 2 + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; + uint32_t ppdu_drop_cnt : 10, + mpdu_drop_cnt : 10, + tlv_drop_cnt : 10, + end_of_ppdu_seen : 1, + reserved_1a : 1; +#else + uint32_t ppdu_id : 32; + uint32_t reserved_1a : 1, + end_of_ppdu_seen : 1, + tlv_drop_cnt : 10, + mpdu_drop_cnt : 10, + ppdu_drop_cnt : 10; +#endif +}; + +#define MON_DROP_PPDU_ID_OFFSET 0x00000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0xffffffff + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_PPDU_DROP_CNT_LSB 0 +#define MON_DROP_PPDU_DROP_CNT_MSB 9 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_MPDU_DROP_CNT_LSB 10 +#define MON_DROP_MPDU_DROP_CNT_MSB 19 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc00 + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_TLV_DROP_CNT_LSB 20 +#define MON_DROP_TLV_DROP_CNT_MSB 29 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff00000 + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000004 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 30 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 30 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x40000000 + +#define MON_DROP_RESERVED_1A_OFFSET 0x00000004 +#define MON_DROP_RESERVED_1A_LSB 31 +#define MON_DROP_RESERVED_1A_MSB 31 +#define MON_DROP_RESERVED_1A_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/mon_ingress_ring.h b/hw/peach/v2/mon_ingress_ring.h new file mode 100644 index 000000000000..90b58ccba573 --- /dev/null +++ b/hw/peach/v2/mon_ingress_ring.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#endif +}; + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/msmhwioreg.h b/hw/peach/v2/msmhwioreg.h new file mode 100644 index 000000000000..dfc3a5a0205a --- /dev/null +++ b/hw/peach/v2/msmhwioreg.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __MSMHWIOREG_H__ +#define __MSMHWIOREG_H__ + +#include "msmhwiobase.h" + + + +#endif diff --git a/hw/peach/v2/no_ack_report.h b/hw/peach/v2/no_ack_report.h new file mode 100644 index 000000000000..7652d71b493d --- /dev/null +++ b/hw/peach/v2/no_ack_report.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, + macrx_abort_reason : 4, + phyrx_abort_reason : 8, + frame_control : 16; + uint32_t rx_ppdu_duration : 24, + sr_ppdu_during_obss : 1, + selfgen_response_reason_to_sr_ppdu : 4, + reserved_1 : 3; + uint32_t pre_bt_broadcast_status_details : 12, + first_bt_broadcast_status_details : 12, + reserved_2 : 8; + uint32_t second_bt_broadcast_status_details : 12, + reserved_3 : 20; +#else + uint32_t frame_control : 16, + phyrx_abort_reason : 8, + macrx_abort_reason : 4, + no_ack_transmit_reason : 4; + uint32_t reserved_1 : 3, + selfgen_response_reason_to_sr_ppdu : 4, + sr_ppdu_during_obss : 1, + rx_ppdu_duration : 24; + uint32_t reserved_2 : 8, + first_bt_broadcast_status_details : 12, + pre_bt_broadcast_status_details : 12; + uint32_t reserved_3 : 20, + second_bt_broadcast_status_details : 12; +#endif +}; + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/ofdma_trigger_details.h b/hw/peach/v2/ofdma_trigger_details.h new file mode 100644 index 000000000000..a8f0ce15f921 --- /dev/null +++ b/hw/peach/v2/ofdma_trigger_details.h @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, + rx_trigger_frame_user_source : 2, + received_bandwidth : 3, + txop_duration_all_ones : 1, + eht_trigger_response : 1, + pre_rssi_comb : 8, + rssi_comb : 8, + rxpcu_pcie_l0_req_duration : 8; + uint32_t he_trigger_ul_ppdu_length : 5, + he_trigger_ru_allocation : 8, + he_trigger_dl_tx_power : 5, + he_trigger_ul_target_rssi : 5, + he_trigger_ul_mcs : 2, + he_trigger_reserved : 1, + bss_color : 6; + uint32_t trigger_type : 4, + lsig_response_length : 12, + cascade_indication : 1, + carrier_sense : 1, + bandwidth : 2, + cp_ltf_size : 2, + mu_mimo_ltf_mode : 1, + number_of_ltfs : 3, + stbc : 1, + ldpc_extra_symbol : 1, + ap_tx_power_lsb_part : 4; + uint32_t ap_tx_power_msb_part : 2, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + spatial_reuse : 16, + doppler : 1, + he_siga_reserved : 9, + reserved_3b : 1; + uint32_t aid12 : 12, + ru_allocation : 9, + mcs : 4, + dcm : 1, + start_spatial_stream : 3, + number_of_spatial_stream : 3; + uint32_t target_rssi : 7, + coding_type : 1, + mpdu_mu_spacing_factor : 2, + tid_aggregation_limit : 3, + reserved_5b : 1, + prefered_ac : 2, + bar_control_ack_policy : 1, + bar_control_multi_tid : 1, + bar_control_compressed_bitmap : 1, + bar_control_reserved : 9, + bar_control_tid_info : 4; + uint32_t nr0_per_tid_info_reserved : 12, + nr0_per_tid_info_tid_value : 4, + nr0_start_seq_ctrl_frag_number : 4, + nr0_start_seq_ctrl_start_seq_number : 12; + uint32_t nr1_per_tid_info_reserved : 12, + nr1_per_tid_info_tid_value : 4, + nr1_start_seq_ctrl_frag_number : 4, + nr1_start_seq_ctrl_start_seq_number : 12; + uint32_t nr2_per_tid_info_reserved : 12, + nr2_per_tid_info_tid_value : 4, + nr2_start_seq_ctrl_frag_number : 4, + nr2_start_seq_ctrl_start_seq_number : 12; + uint32_t nr3_per_tid_info_reserved : 12, + nr3_per_tid_info_tid_value : 4, + nr3_start_seq_ctrl_frag_number : 4, + nr3_start_seq_ctrl_start_seq_number : 12; + uint32_t nr4_per_tid_info_reserved : 12, + nr4_per_tid_info_tid_value : 4, + nr4_start_seq_ctrl_frag_number : 4, + nr4_start_seq_ctrl_start_seq_number : 12; + uint32_t nr5_per_tid_info_reserved : 12, + nr5_per_tid_info_tid_value : 4, + nr5_start_seq_ctrl_frag_number : 4, + nr5_start_seq_ctrl_start_seq_number : 12; + uint32_t nr6_per_tid_info_reserved : 12, + nr6_per_tid_info_tid_value : 4, + nr6_start_seq_ctrl_frag_number : 4, + nr6_start_seq_ctrl_start_seq_number : 12; + uint32_t nr7_per_tid_info_reserved : 12, + nr7_per_tid_info_tid_value : 4, + nr7_start_seq_ctrl_frag_number : 4, + nr7_start_seq_ctrl_start_seq_number : 12; + uint32_t fb_segment_retransmission_bitmap : 8, + reserved_14a : 2, + u_sig_puncture_pattern_encoding : 6, + dot11be_puncture_bitmap : 16; + uint32_t rx_chain_mask : 8, + rx_duration_field : 16, + scrambler_seed : 7, + rx_chain_mask_type : 1; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t sw_peer_id : 16, + response_tx_duration : 16; + uint32_t __reserved_g_0005_trigger_subtype : 4, + tbr_trigger_common_info_79_68 : 12, + tbr_trigger_sound_reserved_20_12 : 9, + i2r_rep : 3, + tbr_trigger_sound_reserved_25_24 : 2, + reserved_18a : 1, + qos_null_only_response_tx : 1; + uint32_t tbr_trigger_sound_sac : 16, + reserved_19a : 8, + u_sig_reserved2 : 5, + reserved_19b : 3; + uint32_t eht_special_aid12 : 12, + phy_version : 3, + bandwidth_ext : 2, + eht_spatial_reuse : 8, + u_sig_reserved1 : 7; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, + rssi_comb : 8, + pre_rssi_comb : 8, + eht_trigger_response : 1, + txop_duration_all_ones : 1, + received_bandwidth : 3, + rx_trigger_frame_user_source : 2, + ax_trigger_source : 1; + uint32_t bss_color : 6, + he_trigger_reserved : 1, + he_trigger_ul_mcs : 2, + he_trigger_ul_target_rssi : 5, + he_trigger_dl_tx_power : 5, + he_trigger_ru_allocation : 8, + he_trigger_ul_ppdu_length : 5; + uint32_t ap_tx_power_lsb_part : 4, + ldpc_extra_symbol : 1, + stbc : 1, + number_of_ltfs : 3, + mu_mimo_ltf_mode : 1, + cp_ltf_size : 2, + bandwidth : 2, + carrier_sense : 1, + cascade_indication : 1, + lsig_response_length : 12, + trigger_type : 4; + uint32_t reserved_3b : 1, + he_siga_reserved : 9, + doppler : 1, + spatial_reuse : 16, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + ap_tx_power_msb_part : 2; + uint32_t number_of_spatial_stream : 3, + start_spatial_stream : 3, + dcm : 1, + mcs : 4, + ru_allocation : 9, + aid12 : 12; + uint32_t bar_control_tid_info : 4, + bar_control_reserved : 9, + bar_control_compressed_bitmap : 1, + bar_control_multi_tid : 1, + bar_control_ack_policy : 1, + prefered_ac : 2, + reserved_5b : 1, + tid_aggregation_limit : 3, + mpdu_mu_spacing_factor : 2, + coding_type : 1, + target_rssi : 7; + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, + nr0_start_seq_ctrl_frag_number : 4, + nr0_per_tid_info_tid_value : 4, + nr0_per_tid_info_reserved : 12; + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, + nr1_start_seq_ctrl_frag_number : 4, + nr1_per_tid_info_tid_value : 4, + nr1_per_tid_info_reserved : 12; + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, + nr2_start_seq_ctrl_frag_number : 4, + nr2_per_tid_info_tid_value : 4, + nr2_per_tid_info_reserved : 12; + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, + nr3_start_seq_ctrl_frag_number : 4, + nr3_per_tid_info_tid_value : 4, + nr3_per_tid_info_reserved : 12; + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, + nr4_start_seq_ctrl_frag_number : 4, + nr4_per_tid_info_tid_value : 4, + nr4_per_tid_info_reserved : 12; + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, + nr5_start_seq_ctrl_frag_number : 4, + nr5_per_tid_info_tid_value : 4, + nr5_per_tid_info_reserved : 12; + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, + nr6_start_seq_ctrl_frag_number : 4, + nr6_per_tid_info_tid_value : 4, + nr6_per_tid_info_reserved : 12; + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, + nr7_start_seq_ctrl_frag_number : 4, + nr7_per_tid_info_tid_value : 4, + nr7_per_tid_info_reserved : 12; + uint32_t dot11be_puncture_bitmap : 16, + u_sig_puncture_pattern_encoding : 6, + reserved_14a : 2, + fb_segment_retransmission_bitmap : 8; + uint32_t rx_chain_mask_type : 1, + scrambler_seed : 7, + rx_duration_field : 16, + rx_chain_mask : 8; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, + sw_peer_id : 16; + uint32_t qos_null_only_response_tx : 1, + reserved_18a : 1, + tbr_trigger_sound_reserved_25_24 : 2, + i2r_rep : 3, + tbr_trigger_sound_reserved_20_12 : 9, + tbr_trigger_common_info_79_68 : 12, + __reserved_g_0005_trigger_subtype : 4; + uint32_t reserved_19b : 3, + u_sig_reserved2 : 5, + reserved_19a : 8, + tbr_trigger_sound_sac : 16; + uint32_t u_sig_reserved1 : 7, + eht_spatial_reuse : 8, + bandwidth_ext : 2, + phy_version : 3, + eht_special_aid12 : 12; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#endif +}; + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000001 + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x00000006 + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x00000038 + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x00000040 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x00000080 + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x0000ff00 + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0xff000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 0 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 4 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 5 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 12 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe0 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 13 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 17 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 18 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 22 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c0000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x01800000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 25 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 25 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x02000000 + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 26 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 31 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc000000 + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0000fff0 + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x00010000 + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x00020000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x000c0000 + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x00300000 + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x00400000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x03800000 + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x04000000 + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x08000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0xf0000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 1 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x00000003 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 2 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 3 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 4 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 4 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000010 + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 5 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 20 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe0 + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 21 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 21 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x00200000 + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 22 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 30 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc00000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x001ff000 + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x01e00000 + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x02000000 + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x1c000000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0xe0000000 + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x00000080 + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 8 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x00000300 + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 10 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 12 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c00 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 13 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 13 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x00002000 + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 14 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 16 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x00010000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 17 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 17 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x00020000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 18 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x00040000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 19 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 27 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff80000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 28 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 31 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf0000000 + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x000000ff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x00000300 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000fc00 + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0xffff0000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 7 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff00 + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 24 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 30 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f000000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 31 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x00000044 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 15 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x00000044 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff0000 + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x0000000f + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x0000fff0 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x01ff0000 + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x0e000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x30000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x40000000 + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 24 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 28 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 29 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe0000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x00007000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x00018000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x01fe0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0xfe000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x00000054 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 31 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/pcu_ppdu_setup_init.h b/hw/peach/v2/pcu_ppdu_setup_init.h new file mode 100644 index 000000000000..ff7f47041aee --- /dev/null +++ b/hw/peach/v2/pcu_ppdu_setup_init.h @@ -0,0 +1,2282 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, + response_type : 5, + response_info_part2_required : 1, + response_to_response : 3, + mba_user_order : 2, + expected_mba_size : 11, + required_ul_mu_resp_user_count : 6, + transmitted_bssid_check_en : 1; + uint32_t mprot_required_bw1 : 1, + mprot_required_bw20 : 1, + mprot_required_bw40 : 1, + mprot_required_bw80 : 1, + mprot_required_bw160 : 1, + mprot_required_bw240 : 1, + mprot_required_bw320 : 1, + ppdu_allowed_bw1 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw320 : 1, + set_fc_pwr_mgt : 1, + use_cts_duration_for_data_tx : 1, + update_timestamp_64 : 1, + update_timestamp_32_lower : 1, + update_timestamp_32_upper : 1, + reserved_1a : 13; + uint32_t insert_timestamp_offset_0 : 16, + insert_timestamp_offset_1 : 16; + uint32_t max_bw40_try_count : 4, + max_bw80_try_count : 4, + max_bw160_try_count : 4, + max_bw240_try_count : 4, + max_bw320_try_count : 4, + insert_wur_timestamp_offset : 6, + update_wur_timestamp : 1, + wur_embedded_bssid_present : 1, + insert_wur_fcs : 1, + reserved_3b : 3; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, + r2r_rx_duration_field : 16; + uint32_t r2r_group_id : 6, + r2r_response_frame_type : 4, + r2r_sta_partial_aid : 11, + use_address_fields_for_protection : 1, + r2r_set_required_response_time : 1, + reserved_29a : 3, + r2r_bw20_active_channel : 3, + r2r_bw40_active_channel : 3; + uint32_t r2r_bw80_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw320_active_channel : 3, + r2r_bw20 : 3, + r2r_bw40 : 3, + r2r_bw80 : 3, + r2r_bw160 : 3, + r2r_bw240 : 3, + r2r_bw320 : 3, + reserved_30a : 2; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t mu_response_expected_bitmap_36_32 : 5, + mu_expected_response_cbf_count : 6, + mu_expected_response_sta_count : 6, + transmit_includes_multidestination : 1, + insert_prev_tx_start_timing_info : 1, + insert_current_tx_start_timing_info : 1, + tx_start_transmit_time_byte_offset : 12; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad1_47_32 : 16, + protection_frame_ad2_15_0 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t dynamic_medium_prot_threshold : 24, + dynamic_medium_prot_type : 1, + reserved_54a : 7; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad3_47_32 : 16, + protection_frame_ad4_15_0 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#else + uint32_t transmitted_bssid_check_en : 1, + required_ul_mu_resp_user_count : 6, + expected_mba_size : 11, + mba_user_order : 2, + response_to_response : 3, + response_info_part2_required : 1, + response_type : 5, + medium_prot_type : 3; + uint32_t reserved_1a : 13, + update_timestamp_32_upper : 1, + update_timestamp_32_lower : 1, + update_timestamp_64 : 1, + use_cts_duration_for_data_tx : 1, + set_fc_pwr_mgt : 1, + ppdu_allowed_bw320 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw1 : 1, + mprot_required_bw320 : 1, + mprot_required_bw240 : 1, + mprot_required_bw160 : 1, + mprot_required_bw80 : 1, + mprot_required_bw40 : 1, + mprot_required_bw20 : 1, + mprot_required_bw1 : 1; + uint32_t insert_timestamp_offset_1 : 16, + insert_timestamp_offset_0 : 16; + uint32_t reserved_3b : 3, + insert_wur_fcs : 1, + wur_embedded_bssid_present : 1, + update_wur_timestamp : 1, + insert_wur_timestamp_offset : 6, + max_bw320_try_count : 4, + max_bw240_try_count : 4, + max_bw160_try_count : 4, + max_bw80_try_count : 4, + max_bw40_try_count : 4; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, + r2r_hw_response_tx_duration : 16; + uint32_t r2r_bw40_active_channel : 3, + r2r_bw20_active_channel : 3, + reserved_29a : 3, + r2r_set_required_response_time : 1, + use_address_fields_for_protection : 1, + r2r_sta_partial_aid : 11, + r2r_response_frame_type : 4, + r2r_group_id : 6; + uint32_t reserved_30a : 2, + r2r_bw320 : 3, + r2r_bw240 : 3, + r2r_bw160 : 3, + r2r_bw80 : 3, + r2r_bw40 : 3, + r2r_bw20 : 3, + r2r_bw320_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw80_active_channel : 3; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t tx_start_transmit_time_byte_offset : 12, + insert_current_tx_start_timing_info : 1, + insert_prev_tx_start_timing_info : 1, + transmit_includes_multidestination : 1, + mu_expected_response_sta_count : 6, + mu_expected_response_cbf_count : 6, + mu_response_expected_bitmap_36_32 : 5; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad2_15_0 : 16, + protection_frame_ad1_47_32 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t reserved_54a : 7, + dynamic_medium_prot_type : 1, + dynamic_medium_prot_threshold : 24; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad4_15_0 : 16, + protection_frame_ad3_47_32 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#endif +}; + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x00000007 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x000000f8 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x00000100 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x00000e00 + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x00003000 + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x01ffc000 + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x7e000000 + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 0 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 0 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 1 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 1 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x00000002 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 2 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 2 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x00000004 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 3 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 3 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x00000008 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 4 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 4 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x00000010 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 5 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 5 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x00000020 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 6 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 6 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x00000040 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 7 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 7 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 8 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 8 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x00000100 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 9 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 9 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x00000200 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 10 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 10 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 11 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 11 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 12 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 12 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 13 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 13 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 14 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 14 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 15 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 15 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 16 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 16 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x00010000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 17 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 17 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x00020000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 18 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 18 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x00040000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff80000 + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x00000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x00000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 0 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 3 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 4 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 7 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 8 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 11 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f00 + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 12 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 15 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 16 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 19 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f0000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 25 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 26 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 26 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 27 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 27 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x08000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 28 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 28 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x10000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c0 + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 10 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc00 + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 21 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 21 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 22 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 22 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x00400000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 23 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x03800000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 28 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe0000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x00000007 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x00000038 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x000001c0 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x00000e00 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x00007000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x00038000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x00e00000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x07000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0xc0000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x000000c4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x0000001f + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x000007e0 + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x0001f800 + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x00020000 + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x00040000 + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0xfff00000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x000000cc +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x000000d4 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x00ffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0xfe000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x000000dc +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x000000e4 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/pdg_response.h b/hw/peach/v2/pdg_response.h new file mode 100644 index 000000000000..f89792c4bcdb --- /dev/null +++ b/hw/peach/v2/pdg_response.h @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, + rx_duration_field : 16; + uint32_t punctured_response_transmission : 1, + cca_subband_channel_bonding_mask : 16, + scrambler_seed_override : 2, + response_density_valid : 1, + response_density : 5, + more_data : 1, + duration_indication : 1, + relayed_frame : 1, + address_indicator : 1, + bandwidth : 3; + uint32_t ack_id : 16, + block_ack_bitmap : 16; + uint32_t response_frame_type : 4, + ack_id_ext : 10, + ftm_en : 1, + group_id : 6, + sta_partial_aid : 11; + uint32_t ndp_ba_start_seq_ctrl : 12, + active_channel : 3, + txop_duration_all_ones : 1, + frame_length : 16; +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, + hw_response_tx_duration : 16; + uint32_t bandwidth : 3, + address_indicator : 1, + relayed_frame : 1, + duration_indication : 1, + more_data : 1, + response_density : 5, + response_density_valid : 1, + scrambler_seed_override : 2, + cca_subband_channel_bonding_mask : 16, + punctured_response_transmission : 1; + uint32_t block_ack_bitmap : 16, + ack_id : 16; + uint32_t sta_partial_aid : 11, + group_id : 6, + ftm_en : 1, + ack_id_ext : 10, + response_frame_type : 4; + uint32_t frame_length : 16, + txop_duration_all_ones : 1, + active_channel : 3, + ndp_ba_start_seq_ctrl : 12; +#endif +}; + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000001c +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000001c +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 16 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 31 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff0000 + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x00000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x00000001 + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x00000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x0001fffe + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x00000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x00060000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x00000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x00080000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x00000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x01f00000 + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x00000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x02000000 + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x00000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x04000000 + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x00000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x08000000 + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x00000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x10000000 + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x00000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0xe0000000 + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x00000024 +#define PDG_RESPONSE_ACK_ID_LSB 0 +#define PDG_RESPONSE_ACK_ID_MSB 15 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x00000024 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 16 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 31 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff0000 + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x00000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x0000000f + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x00000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x00003ff0 + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x00000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x00004000 + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x00000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x001f8000 + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x00000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0xffe00000 + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000002c +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 0 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 11 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000002c +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 12 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 14 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x00007000 + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000002c +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 15 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 15 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x00008000 + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000002c +#define PDG_RESPONSE_FRAME_LENGTH_LSB 16 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 31 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/pdg_response_rate_setting.h b/hw/peach/v2/pdg_response_rate_setting.h new file mode 100644 index 000000000000..27678126a32d --- /dev/null +++ b/hw/peach/v2/pdg_response_rate_setting.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, + tx_antenna_sector_ctrl : 24, + pkt_type : 4, + smoothing : 1, + ldpc : 1, + stbc : 1; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + stf_ltf_3db_boost : 1, + force_extra_symbol : 1; + uint32_t alt_rate_mcs : 4, + nss : 3, + dpd_enable : 1, + tx_pwr : 8, + min_tx_pwr : 8, + tx_chain_mask : 8; + uint32_t reserved_3a : 8, + sgi : 2, + rate_mcs : 4, + reserved_3b : 2, + tx_pwr_1 : 8, + alt_tx_pwr_1 : 8; + uint32_t aggregation : 1, + dot11ax_bss_color_id : 6, + dot11ax_spatial_reuse : 4, + dot11ax_cp_ltf_size : 2, + dot11ax_dcm : 1, + dot11ax_doppler_indication : 1, + dot11ax_su_extended : 1, + dot11ax_min_packet_extension : 2, + dot11ax_pe_nss : 3, + dot11ax_pe_content : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_chain_csd_en : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_dl_ul_flag : 1, + reserved_4a : 5; + uint32_t dot11ax_ext_ru_start_index : 4, + dot11ax_ext_ru_size : 4, + eht_duplicate_mode : 2, + he_sigb_dcm : 1, + he_sigb_0_mcs : 3, + num_he_sigb_sym : 5, + required_response_time_source : 1, + reserved_5a : 6, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, + dot11be_params_placeholder : 4; +#else + uint32_t stbc : 1, + ldpc : 1, + smoothing : 1, + pkt_type : 4, + tx_antenna_sector_ctrl : 24, + reserved_0a : 1; + uint32_t force_extra_symbol : 1, + stf_ltf_3db_boost : 1, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t tx_chain_mask : 8, + min_tx_pwr : 8, + tx_pwr : 8, + dpd_enable : 1, + nss : 3, + alt_rate_mcs : 4; + uint32_t alt_tx_pwr_1 : 8, + tx_pwr_1 : 8, + reserved_3b : 2, + rate_mcs : 4, + sgi : 2, + reserved_3a : 8; + uint32_t reserved_4a : 5, + dot11ax_dl_ul_flag : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_chain_csd_en : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_pe_content : 1, + dot11ax_pe_nss : 3, + dot11ax_min_packet_extension : 2, + dot11ax_su_extended : 1, + dot11ax_doppler_indication : 1, + dot11ax_dcm : 1, + dot11ax_cp_ltf_size : 2, + dot11ax_spatial_reuse : 4, + dot11ax_bss_color_id : 6, + aggregation : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_5a : 6, + required_response_time_source : 1, + num_he_sigb_sym : 5, + he_sigb_0_mcs : 3, + he_sigb_dcm : 1, + eht_duplicate_mode : 2, + dot11ax_ext_ru_size : 4, + dot11ax_ext_ru_start_index : 4; + uint32_t dot11be_params_placeholder : 4, + required_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/pdg_tx_req.h b/hw/peach/v2/pdg_tx_req.h new file mode 100644 index 000000000000..b0df53a0f7d9 --- /dev/null +++ b/hw/peach/v2/pdg_tx_req.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, + use_puncture_pattern : 2, + req_bw : 3, + puncture_pattern_number : 6, + reserved_0b : 1, + req_paprd : 1, + duration_field_boundary_valid : 1, + duration_field_boundary : 16; + uint32_t puncture_subband_mask : 16, + reserved_0c : 16; +#else + uint32_t duration_field_boundary : 16, + duration_field_boundary_valid : 1, + req_paprd : 1, + reserved_0b : 1, + puncture_pattern_number : 6, + req_bw : 3, + use_puncture_pattern : 2, + tx_reason : 2; + uint32_t reserved_0c : 16, + puncture_subband_mask : 16; +#endif +}; + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x00000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x00000003 + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x00000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x0000000c + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x00000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x00000070 + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x00000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x00001f80 + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x00000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x00002000 + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x00000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x00004000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x00000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x00008000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x00000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0xffff0000 + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x00000004 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 0 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 15 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x00000004 +#define PDG_TX_REQ_RESERVED_0C_LSB 16 +#define PDG_TX_REQ_RESERVED_0C_MSB 31 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/phyrx_abort_request_info.h b/hw/peach/v2/phyrx_abort_request_info.h new file mode 100644 index 000000000000..d43ec8487fff --- /dev/null +++ b/hw/peach/v2/phyrx_abort_request_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + gain_change_by_main : 1, + gain_change_by_bt : 1, + main_tx_indication : 1, + bt_tx_indication : 1, + concurrent_mode : 1, + reserved_0 : 1, + receive_duration : 16; +#else + uint32_t receive_duration : 16, + reserved_0 : 1, + concurrent_mode : 1, + bt_tx_indication : 1, + main_tx_indication : 1, + gain_change_by_bt : 1, + gain_change_by_main : 1, + phy_enters_defer_state : 1, + phy_enters_nap_state : 1, + phyrx_abort_reason : 8; +#endif +}; + +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 + +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 + +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 + +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 + +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 + +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 + +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/phyrx_common_user_info.h b/hw/peach/v2/phyrx_common_user_info.h new file mode 100644 index 000000000000..b17fb41f3a85 --- /dev/null +++ b/hw/peach/v2/phyrx_common_user_info.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 + +struct phyrx_common_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t receive_duration : 16, + reserved_0a : 16; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_1a : 9, + obss_nav_update_enable : 1, + obss_nav_value : 16; + uint32_t eht_ppdu_type : 2, + bss_color_id : 6, + dl_ul_flag : 1, + txop_duration : 7, + cp_setting : 2, + ltf_size : 2, + spatial_reuse : 4, + rx_ndp : 1, + dot11be_su_extended : 1, + reserved_2a : 6; + uint32_t eht_duplicate : 2, + eht_sig_cmn_field_type : 2, + doppler_indication : 1, + sta_id : 11, + puncture_bitmap : 16; +#else + uint32_t reserved_0a : 16, + receive_duration : 16; + uint32_t obss_nav_value : 16, + obss_nav_update_enable : 1, + reserved_1a : 9, + u_sig_puncture_pattern_encoding : 6; + uint32_t reserved_2a : 6, + dot11be_su_extended : 1, + rx_ndp : 1, + spatial_reuse : 4, + ltf_size : 2, + cp_setting : 2, + txop_duration : 7, + dl_ul_flag : 1, + bss_color_id : 6, + eht_ppdu_type : 2; + uint32_t puncture_bitmap : 16, + sta_id : 11, + doppler_indication : 1, + eht_sig_cmn_field_type : 2, + eht_duplicate : 2; +#endif +}; + +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x0000ffff + +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0xffff0000 + +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 0 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 5 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f + +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 6 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 14 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007fc0 + +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 15 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 15 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x00008000 + +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 16 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 31 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff0000 + +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x00000003 + +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x000000fc + +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x00000100 + +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x0000fe00 + +#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x00030000 + +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x000c0000 + +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x00f00000 + +#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x01000000 + +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x02000000 + +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0xfc000000 + +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x00000003 + +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 2 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 3 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c + +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 4 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 4 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x00000010 + +#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 5 +#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 15 +#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe0 + +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 16 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 31 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/phyrx_he_sig_a_mu_dl.h b/hw/peach/v2/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..13f98bb5a72f --- /dev/null +++ b/hw/peach/v2/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +struct phyrx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phyrx_he_sig_a_mu_ul.h b/hw/peach/v2/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..853905a07d63 --- /dev/null +++ b/hw/peach/v2/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +struct phyrx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phyrx_he_sig_a_su.h b/hw/peach/v2/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..2529c5680b82 --- /dev/null +++ b/hw/peach/v2/phyrx_he_sig_a_su.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +struct phyrx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phyrx_he_sig_b1_mu.h b/hw/peach/v2/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..f7ab0158e6f3 --- /dev/null +++ b/hw/peach/v2/phyrx_he_sig_b1_mu.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +#else + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00 + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phyrx_he_sig_b2_mu.h b/hw/peach/v2/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..3028568923d9 --- /dev/null +++ b/hw/peach/v2/phyrx_he_sig_b2_mu.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 + +struct phyrx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/phyrx_he_sig_b2_ofdma.h b/hw/peach/v2/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..76f9efb06495 --- /dev/null +++ b/hw/peach/v2/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 + +struct phyrx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/phyrx_ht_sig.h b/hw/peach/v2/phyrx_ht_sig.h new file mode 100644 index 000000000000..4ab8c99b5b3d --- /dev/null +++ b/hw/peach/v2/phyrx_ht_sig.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +struct phyrx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info phyrx_ht_sig_info_details; +#else + struct ht_sig_info phyrx_ht_sig_info_details; +#endif +}; + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 5 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 17 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phyrx_l_sig_a.h b/hw/peach/v2/phyrx_l_sig_a.h new file mode 100644 index 000000000000..c59493935f8a --- /dev/null +++ b/hw/peach/v2/phyrx_l_sig_a.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info phyrx_l_sig_a_info_details; +#else + struct l_sig_a_info phyrx_l_sig_a_info_details; +#endif +}; + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phyrx_l_sig_b.h b/hw/peach/v2/phyrx_l_sig_b.h new file mode 100644 index 000000000000..02d0049adf31 --- /dev/null +++ b/hw/peach/v2/phyrx_l_sig_b.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info phyrx_l_sig_b_info_details; +#else + struct l_sig_b_info phyrx_l_sig_b_info_details; +#endif +}; + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phyrx_location.h b/hw/peach/v2/phyrx_location.h new file mode 100644 index 000000000000..e1d1b48d52ff --- /dev/null +++ b/hw/peach/v2/phyrx_location.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_LOCATION_H_ +#define _PHYRX_LOCATION_H_ + +#include "rx_location_info.h" +#define NUM_OF_DWORDS_PHYRX_LOCATION 28 + +struct phyrx_location { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_location_info rx_location_info_details; +#else + struct rx_location_info rx_location_info_details; +#endif +}; + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x00000001 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x00000002 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x0000000c + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x000000f0 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 19 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 20 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f00000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000014 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x00000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000001c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x00000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x00000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x00000024 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x00000024 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000002c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000002c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x00000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x00000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x00000034 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x00000034 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x00000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x00000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000003c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000003c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x00000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x00000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x00000044 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x00000044 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x00000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x00000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000004c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000004c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x00000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x00000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x00000054 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x00000054 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x00000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x00000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000005c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000005c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x00000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x00000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x00000064 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x00000064 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x00000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x00000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/phyrx_other_receive_info_ru_details.h b/hw/peach/v2/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..dd65c0a5f4c0 --- /dev/null +++ b/hw/peach/v2/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3 + +struct phyrx_other_receive_info_ru_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +#else + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +#endif +}; + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x00000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/phyrx_pkt_end.h b/hw/peach/v2/phyrx_pkt_end.h new file mode 100644 index 000000000000..dd32b3f2255a --- /dev/null +++ b/hw/peach/v2/phyrx_pkt_end.h @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ + +#include "phyrx_pkt_end_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END 24 + +struct phyrx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct phyrx_pkt_end_info rx_pkt_end_details; +#else + struct phyrx_pkt_end_info rx_pkt_end_details; +#endif +}; + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000010 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x000000c0 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0xffff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/phyrx_pkt_end_info.h b/hw/peach/v2/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..096122c04547 --- /dev/null +++ b/hw/peach/v2/phyrx_pkt_end_info.h @@ -0,0 +1,457 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ + +#include "receive_rssi_info.h" +#include "rx_timing_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 + +struct phyrx_pkt_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t __reserved_g_0001 : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + reserved_0a : 1, + frameless_frame_received : 1, + reserved_0b : 2, + rssi_comb : 8, + reserved_0c : 16; + struct rx_timing_info rx_timing_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#else + uint32_t reserved_0c : 16, + rssi_comb : 8, + reserved_0b : 2, + frameless_frame_received : 1, + reserved_0a : 1, + rssi_info_valid : 1, + timing_info_valid : 1, + location_info_valid : 1, + __reserved_g_0001 : 1; + struct rx_timing_info rx_timing_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#endif +}; + +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 + +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 + +#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/phyrx_rssi_legacy.h b/hw/peach/v2/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..f1a95baddde6 --- /dev/null +++ b/hw/peach/v2/phyrx_rssi_legacy.h @@ -0,0 +1,811 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ + +#include "receive_rssi_info.h" +#include "receive_pkt_start_info.h" +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 + +struct phyrx_rssi_legacy { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_pkt_start_info rx_pkt_start_details; + uint32_t sw_phy_meta_data : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +#else + struct receive_pkt_start_info rx_pkt_start_details; + uint32_t sw_phy_meta_data : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8, + rssi_comb : 8, + pre_rssi_comb : 8; + uint32_t rssi_for_trigger_resp : 8, + rssi_for_spatial_reuse : 8, + rssi_db_to_dbm_offset : 8, + rssi_comb_ppdu : 8; +#endif +}; + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x0000000f + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000e0 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 7 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 8 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x00000100 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 9 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe00 + +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 7 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 16 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 23 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 24 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 31 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/phyrx_user_info.h b/hw/peach/v2/phyrx_user_info.h new file mode 100644 index 000000000000..8b115be92e06 --- /dev/null +++ b/hw/peach/v2/phyrx_user_info.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 + +struct phyrx_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/phyrx_vht_sig_a.h b/hw/peach/v2/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..44e3d16af0f2 --- /dev/null +++ b/hw/peach/v2/phyrx_vht_sig_a.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +struct phyrx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#else + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#endif +}; + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/phytx_abort_request_info.h b/hw/peach/v2/phytx_abort_request_info.h new file mode 100644 index 000000000000..c3b1f353df85 --- /dev/null +++ b/hw/peach/v2/phytx_abort_request_info.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, + user_number : 6, + reserved : 2; +#else + uint16_t reserved : 2, + user_number : 6, + phytx_abort_reason : 8; +#endif +}; + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + +#endif diff --git a/hw/peach/v2/phytx_pkt_end.h b/hw/peach/v2/phytx_pkt_end.h new file mode 100644 index 000000000000..bc8194310e59 --- /dev/null +++ b/hw/peach/v2/phytx_pkt_end.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_PKT_END_H_ +#define _PHYTX_PKT_END_H_ + +#define NUM_OF_WORDS_PHYTX_PKT_END 26 + +#define NUM_OF_DWORDS_PHYTX_PKT_END 13 + +struct phytx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t start_of_frame_timestamp_15_0 : 16; + uint16_t start_of_frame_timestamp_31_16 : 16; + uint16_t end_of_frame_timestamp_15_0 : 16; + uint16_t end_of_frame_timestamp_31_16 : 16; + uint16_t tx_group_delay : 12, + timing_status : 2, + phyrx_entered_nap_state : 1, + dpdtrain_done : 1; + uint16_t transmit_delay : 16; + uint16_t tpc_dbg_info_cmn_15_0 : 16; + uint16_t tpc_dbg_info_cmn_31_16 : 16; + uint16_t tpc_dbg_info_cmn_47_32 : 16; + uint16_t tpc_dbg_info_chn1_15_0 : 16; + uint16_t tpc_dbg_info_chn1_31_16 : 16; + uint16_t tpc_dbg_info_chn1_47_32 : 16; + uint16_t tpc_dbg_info_chn1_63_48 : 16; + uint16_t tpc_dbg_info_chn1_79_64 : 16; + uint16_t tpc_dbg_info_chn2_15_0 : 16; + uint16_t tpc_dbg_info_chn2_31_16 : 16; + uint16_t tpc_dbg_info_chn2_47_32 : 16; + uint16_t tpc_dbg_info_chn2_63_48 : 16; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint16_t phytx_tx_end_sw_info_15_0 : 16; + uint16_t phytx_tx_end_sw_info_31_16 : 16; + uint16_t phytx_tx_end_sw_info_47_32 : 16; + uint16_t phytx_tx_end_sw_info_63_48 : 16; + uint16_t beamform_masked_user_bitmap_15_0 : 16; + uint16_t beamform_masked_user_bitmap_31_16 : 16; + uint16_t beamform_masked_user_bitmap_36_32 : 5, + reserved_23 : 11; +#else + uint16_t start_of_frame_timestamp_15_0 : 16; + uint16_t start_of_frame_timestamp_31_16 : 16; + uint16_t end_of_frame_timestamp_15_0 : 16; + uint16_t end_of_frame_timestamp_31_16 : 16; + uint16_t dpdtrain_done : 1, + phyrx_entered_nap_state : 1, + timing_status : 2, + tx_group_delay : 12; + uint16_t transmit_delay : 16; + uint16_t tpc_dbg_info_cmn_15_0 : 16; + uint16_t tpc_dbg_info_cmn_31_16 : 16; + uint16_t tpc_dbg_info_cmn_47_32 : 16; + uint16_t tpc_dbg_info_chn1_15_0 : 16; + uint16_t tpc_dbg_info_chn1_31_16 : 16; + uint16_t tpc_dbg_info_chn1_47_32 : 16; + uint16_t tpc_dbg_info_chn1_63_48 : 16; + uint16_t tpc_dbg_info_chn1_79_64 : 16; + uint16_t tpc_dbg_info_chn2_15_0 : 16; + uint16_t tpc_dbg_info_chn2_31_16 : 16; + uint16_t tpc_dbg_info_chn2_47_32 : 16; + uint16_t tpc_dbg_info_chn2_63_48 : 16; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint16_t phytx_tx_end_sw_info_15_0 : 16; + uint16_t phytx_tx_end_sw_info_31_16 : 16; + uint16_t phytx_tx_end_sw_info_47_32 : 16; + uint16_t phytx_tx_end_sw_info_63_48 : 16; + uint16_t beamform_masked_user_bitmap_15_0 : 16; + uint16_t beamform_masked_user_bitmap_31_16 : 16; + uint16_t reserved_23 : 11, + beamform_masked_user_bitmap_36_32 : 5; +#endif +}; + +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 +#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 +#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 +#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff + +#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 +#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 +#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 +#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 + +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 + +#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 +#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 +#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 +#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 + +#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a +#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 +#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 +#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f + +#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 +#define PHYTX_PKT_END_RESERVED_23_LSB 5 +#define PHYTX_PKT_END_RESERVED_23_MSB 15 +#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 + +#endif diff --git a/hw/peach/v2/phytx_ppdu_header_info_request.h b/hw/peach/v2/phytx_ppdu_header_info_request.h new file mode 100644 index 000000000000..5d7a67d0a62c --- /dev/null +++ b/hw/peach/v2/phytx_ppdu_header_info_request.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, + reserved : 11; + uint16_t tlv32_padding : 16; +#else + uint16_t reserved : 11, + request_type : 5; + uint16_t tlv32_padding : 16; +#endif +}; + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + +#endif diff --git a/hw/peach/v2/receive_pkt_start_info.h b/hw/peach/v2/receive_pkt_start_info.h new file mode 100644 index 000000000000..0cf588079745 --- /dev/null +++ b/hw/peach/v2/receive_pkt_start_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_PKT_START_INFO_H_ +#define _RECEIVE_PKT_START_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 + +struct receive_pkt_start_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + receive_bandwidth : 3, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t preamble_time_to_rxframe : 8, + standalone_sniffer_mode : 1, + reserved_3a : 23; +#else + uint32_t phy_ppdu_id : 16, + rx_chain_mask : 8, + receive_bandwidth : 3, + rx_chain_mask_type : 1, + reception_type : 4; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t reserved_3a : 23, + standalone_sniffer_mode : 1, + preamble_time_to_rxframe : 8; +#endif +}; + +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f + +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 + +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 + +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff + +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 + +#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 +#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 +#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 + +#endif diff --git a/hw/peach/v2/receive_rssi_info.h b/hw/peach/v2/receive_rssi_info.h new file mode 100644 index 000000000000..afabffff6f28 --- /dev/null +++ b/hw/peach/v2/receive_rssi_info.h @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_ext160_0_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_3_chain0 : 8; + uint32_t rssi_ext160_4_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_7_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_ext160_0_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_3_chain1 : 8; + uint32_t rssi_ext160_4_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_7_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_ext160_0_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_3_chain2 : 8; + uint32_t rssi_ext160_4_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_7_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_ext160_0_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_3_chain3 : 8; + uint32_t rssi_ext160_4_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_7_chain3 : 8; +#else + uint32_t rssi_ext40_high20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_pri20_chain0 : 8; + uint32_t rssi_ext80_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_low20_chain0 : 8; + uint32_t rssi_ext160_3_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_0_chain0 : 8; + uint32_t rssi_ext160_7_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_4_chain0 : 8; + uint32_t rssi_ext40_high20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_pri20_chain1 : 8; + uint32_t rssi_ext80_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_low20_chain1 : 8; + uint32_t rssi_ext160_3_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_0_chain1 : 8; + uint32_t rssi_ext160_7_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_4_chain1 : 8; + uint32_t rssi_ext40_high20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_pri20_chain2 : 8; + uint32_t rssi_ext80_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_low20_chain2 : 8; + uint32_t rssi_ext160_3_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_0_chain2 : 8; + uint32_t rssi_ext160_7_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_4_chain2 : 8; + uint32_t rssi_ext40_high20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_pri20_chain3 : 8; + uint32_t rssi_ext80_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_low20_chain3 : 8; + uint32_t rssi_ext160_3_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_0_chain3 : 8; + uint32_t rssi_ext160_7_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_4_chain3 : 8; +#endif +}; + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/receive_user_info.h b/hw/peach/v2/receive_user_info.h new file mode 100644 index 000000000000..ea1061482a53 --- /dev/null +++ b/hw/peach/v2/receive_user_info.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 + +struct receive_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + __reserved_g_0004 : 1, + reserved_1a : 1, + mimo_ss_bitmap : 8, + receive_bandwidth : 3, + reserved_1b : 5, + dl_ofdma_user_index : 8; + uint32_t dl_ofdma_content_channel : 1, + reserved_2a : 7, + nss : 3, + stream_offset : 3, + sta_dcm : 1, + ldpc : 1, + ru_type_80_0 : 4, + ru_type_80_1 : 4, + ru_type_80_2 : 4, + ru_type_80_3 : 4; + uint32_t ru_start_index_80_0 : 6, + reserved_3a : 2, + ru_start_index_80_1 : 6, + reserved_3b : 2, + ru_start_index_80_2 : 6, + reserved_3c : 2, + ru_start_index_80_3 : 6, + reserved_3d : 2; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#else + uint32_t reception_type : 3, + stbc : 1, + pkt_type : 4, + user_rssi : 8, + phy_ppdu_id : 16; + uint32_t dl_ofdma_user_index : 8, + reserved_1b : 5, + receive_bandwidth : 3, + mimo_ss_bitmap : 8, + reserved_1a : 1, + __reserved_g_0004 : 1, + sgi : 2, + rate_mcs : 4; + uint32_t ru_type_80_3 : 4, + ru_type_80_2 : 4, + ru_type_80_1 : 4, + ru_type_80_0 : 4, + ldpc : 1, + sta_dcm : 1, + stream_offset : 3, + nss : 3, + reserved_2a : 7, + dl_ofdma_content_channel : 1; + uint32_t reserved_3d : 2, + ru_start_index_80_3 : 6, + reserved_3c : 2, + ru_start_index_80_2 : 6, + reserved_3b : 2, + ru_start_index_80_1 : 6, + reserved_3a : 2, + ru_start_index_80_0 : 6; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#endif +}; + +#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 +#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 +#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_STBC_LSB 28 +#define RECEIVE_USER_INFO_STBC_MSB 28 +#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 + +#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 + +#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_RATE_MCS_MSB 3 +#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f + +#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_SGI_LSB 4 +#define RECEIVE_USER_INFO_SGI_MSB 5 +#define RECEIVE_USER_INFO_SGI_MASK 0x00000030 + +#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080 + +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 +#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 + +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 +#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe + +#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_NSS_LSB 8 +#define RECEIVE_USER_INFO_NSS_MSB 10 +#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 + +#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 + +#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STA_DCM_LSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 + +#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_LDPC_LSB 15 +#define RECEIVE_USER_INFO_LDPC_MSB 15 +#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f + +#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 +#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 +#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 +#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 +#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 +#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 +#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/received_response_user_15_8.h b/hw/peach/v2/received_response_user_15_8.h new file mode 100644 index 000000000000..f62d4b8c2bea --- /dev/null +++ b/hw/peach/v2/received_response_user_15_8.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/received_response_user_23_16.h b/hw/peach/v2/received_response_user_23_16.h new file mode 100644 index 000000000000..87fc0a8ff72a --- /dev/null +++ b/hw/peach/v2/received_response_user_23_16.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/received_response_user_31_24.h b/hw/peach/v2/received_response_user_31_24.h new file mode 100644 index 000000000000..f15f2a1715d2 --- /dev/null +++ b/hw/peach/v2/received_response_user_31_24.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/received_response_user_36_32.h b/hw/peach/v2/received_response_user_36_32.h new file mode 100644 index 000000000000..66f201f1d526 --- /dev/null +++ b/hw/peach/v2/received_response_user_36_32.h @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/received_response_user_7_0.h b/hw/peach/v2/received_response_user_7_0.h new file mode 100644 index 000000000000..a90495fdbc8c --- /dev/null +++ b/hw/peach/v2/received_response_user_7_0.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/received_response_user_info.h b/hw/peach/v2/received_response_user_info.h new file mode 100644 index 000000000000..b0c7d9bc7546 --- /dev/null +++ b/hw/peach/v2/received_response_user_info.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, + mpdu_fcs_fail_count : 12, + qosnull_frame_count : 4, + reserved_0a : 3, + user_info_valid : 1; + uint32_t null_delimiter_count : 22, + reserved_1a : 9, + ht_control_valid : 1; + uint32_t ht_control : 32; + uint32_t qos_control_valid : 16, + eosp : 16; + uint32_t qos_control_15_8_tid_0 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_3 : 8; + uint32_t qos_control_15_8_tid_4 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_7 : 8; + uint32_t qos_control_15_8_tid_8 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_11 : 8; + uint32_t qos_control_15_8_tid_12 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_15 : 8; +#else + uint32_t user_info_valid : 1, + reserved_0a : 3, + qosnull_frame_count : 4, + mpdu_fcs_fail_count : 12, + mpdu_fcs_pass_count : 12; + uint32_t ht_control_valid : 1, + reserved_1a : 9, + null_delimiter_count : 22; + uint32_t ht_control : 32; + uint32_t eosp : 16, + qos_control_valid : 16; + uint32_t qos_control_15_8_tid_3 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_0 : 8; + uint32_t qos_control_15_8_tid_7 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_4 : 8; + uint32_t qos_control_15_8_tid_11 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_8 : 8; + uint32_t qos_control_15_8_tid_15 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_12 : 8; +#endif +}; + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/received_trigger_info.h b/hw/peach/v2/received_trigger_info.h new file mode 100644 index 000000000000..e36f4c102273 --- /dev/null +++ b/hw/peach/v2/received_trigger_info.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 5 + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; +#else + struct received_trigger_info_details received_trigger_details; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xfe000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/received_trigger_info_details.h b/hw/peach/v2/received_trigger_info_details.h new file mode 100644 index 000000000000..f292561f1a0b --- /dev/null +++ b/hw/peach/v2/received_trigger_info_details.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, + ax_trigger_source : 1, + ax_trigger_type : 4, + trigger_source_sta_full_aid : 13, + frame_control_valid : 1, + qos_control_valid : 1, + he_control_info_valid : 1, + __reserved_g_0005_trigger_subtype : 4, + txop_sharing_mode : 2, + tid_aggregation_limit_is_zero : 1; + uint32_t phy_ppdu_id : 16, + lsig_response_length : 12, + reserved_1a : 4; + uint32_t frame_control : 16, + qos_control : 16; + uint32_t sw_peer_id : 16, + txop_sharing_allocation_duration : 9, + reserved_3a : 7; + uint32_t he_control : 32; +#else + uint32_t tid_aggregation_limit_is_zero : 1, + txop_sharing_mode : 2, + __reserved_g_0005_trigger_subtype : 4, + he_control_info_valid : 1, + qos_control_valid : 1, + frame_control_valid : 1, + trigger_source_sta_full_aid : 13, + ax_trigger_type : 4, + ax_trigger_source : 1, + trigger_type : 4; + uint32_t reserved_1a : 4, + lsig_response_length : 12, + phy_ppdu_id : 16; + uint32_t qos_control : 16, + frame_control : 16; + uint32_t reserved_3a : 7, + txop_sharing_allocation_duration : 9, + sw_peer_id : 16; + uint32_t he_control : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xfe000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/reo_descriptor_threshold_reached_status.h b/hw/peach/v2/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..0985327ae495 --- /dev/null +++ b/hw/peach/v2/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 27 + +struct reo_descriptor_threshold_reached_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 30, + threshold_index : 2; + uint32_t reserved_3 : 8, + link_descriptor_counter0 : 24; + uint32_t reserved_4 : 8, + link_descriptor_counter1 : 24; + uint32_t reserved_5 : 8, + link_descriptor_counter2 : 24; + uint32_t reserved_6 : 6, + link_descriptor_counter_sum : 26; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x00000003 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0xfffffffc + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0xfc000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x00000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x00000024 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_destination_ring.h b/hw/peach/v2/reo_destination_ring.h new file mode 100644 index 000000000000..019dc7ee3b95 --- /dev/null +++ b/hw/peach/v2/reo_destination_ring.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 + +struct reo_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_RING_ID_LSB 20 +#define REO_DESTINATION_RING_RING_ID_MSB 27 +#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_destination_ring_with_pn.h b/hw/peach/v2/reo_destination_ring_with_pn.h new file mode 100644 index 000000000000..88e3b43cf977 --- /dev/null +++ b/hw/peach/v2/reo_destination_ring_with_pn.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESTINATION_RING_WITH_PN_H_ +#define _REO_DESTINATION_RING_WITH_PN_H_ + +#include "rx_msdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 + +struct reo_destination_ring_with_pn { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t msdu_count : 8, + prev_pn_23_0 : 24; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t prev_pn_23_0 : 24, + msdu_count : 8; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET 0x0000000c +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_entrance_ring.h b/hw/peach/v2/reo_entrance_ring.h new file mode 100644 index 000000000000..4813df49ed1a --- /dev/null +++ b/hw/peach/v2/reo_entrance_ring.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ + +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid : 1, + sw_exception_destination_ring : 5, + mpdu_sequence_number : 12, + reserved_6a : 1; + uint32_t phy_ppdu_id : 16, + src_link_id : 3, + reserved_7a : 1, + ring_id : 8, + looping_count : 4; +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_5a : 4, + frameless_bar : 1, + reo_destination_indication : 5, + rounded_mpdu_byte_count : 14, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_6a : 1, + mpdu_sequence_number : 12, + sw_exception_destination_ring : 5, + sw_exception_destination_ring_valid : 1, + sw_exception_mpdu_delink : 1, + sw_exception : 1, + mpdu_fragment_number : 4, + rxdma_error_code : 5, + rxdma_push_reason : 2; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 1, + src_link_id : 3, + phy_ppdu_id : 16; +#endif +}; + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 + +#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 + +#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 + +#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff + +#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 + +#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 + +#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_RING_ID_MSB 27 +#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 + +#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_flush_cache.h b/hw/peach/v2/reo_flush_cache.h new file mode 100644 index 000000000000..6967a7f38728 --- /dev/null +++ b/hw/peach/v2/reo_flush_cache.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 + +struct reo_flush_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + flush_queue_1k_desc : 1, + reserved_2b : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t reserved_2b : 16, + flush_queue_1k_desc : 1, + flush_entire_cache : 1, + block_cache_usage_after_flush : 1, + flush_without_invalidate : 1, + cache_block_resource_index : 2, + release_cache_block_index : 1, + forward_all_mpdus_in_queue : 1, + flush_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 31 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 + +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 + +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 + +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 + +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 + +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x00004000 + +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x00008000 + +#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 +#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0xffff0000 + +#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_3A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_5A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_7A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/reo_flush_cache_status.h b/hw/peach/v2/reo_flush_cache_status.h new file mode 100644 index 000000000000..2cd6bf2ea9d0 --- /dev/null +++ b/hw/peach/v2/reo_flush_cache_status.h @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 27 + +struct reo_flush_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit : 1, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_error : 2, + cache_controller_flush_count : 8, + flush_queue_1k_desc : 1, + reserved_2b : 5; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2b : 5, + flush_queue_1k_desc : 1, + cache_controller_flush_count : 8, + cache_controller_flush_status_error : 2, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_hit : 1, + reserved_2a : 5, + block_error_details : 2, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x00000006 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x000000f8 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 + +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x04000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0xf8000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_flush_queue.h b/hw/peach/v2/reo_flush_queue.h new file mode 100644 index 000000000000..a480a08ddc2c --- /dev/null +++ b/hw/peach/v2/reo_flush_queue.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 + +struct reo_flush_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush : 1, + block_resource_index : 2, + reserved_2a : 21; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t reserved_2a : 21, + block_resource_index : 2, + block_desc_addr_usage_after_flush : 1, + flush_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 31 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 + +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x00000600 + +#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 +#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0xfffff800 + +#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/reo_flush_queue_status.h b/hw/peach/v2/reo_flush_queue_status.h new file mode 100644 index 000000000000..9ed72297e6cc --- /dev/null +++ b/hw/peach/v2/reo_flush_queue_status.h @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 27 + +struct reo_flush_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 31, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0xfffffffe + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_flush_timeout_list.h b/hw/peach/v2/reo_flush_timeout_list.h new file mode 100644 index 000000000000..a5c36a698650 --- /dev/null +++ b/hw/peach/v2/reo_flush_timeout_list.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9 + +struct reo_flush_timeout_list { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1 : 30, + ac_timout_list : 2; + uint32_t minimum_forward_buf_count : 16, + minimum_release_desc_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x00000003 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/reo_flush_timeout_list_status.h b/hw/peach/v2/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..c05740bbf19c --- /dev/null +++ b/hw/peach/v2/reo_flush_timeout_list_status.h @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 27 + +struct reo_flush_timeout_list_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + timout_list_empty : 1, + error_detected : 1; + uint32_t forward_buf_count : 16, + release_desc_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x00000002 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_get_queue_stats.h b/hw/peach/v2/reo_get_queue_stats.h new file mode 100644 index 000000000000..d494d0fd9f4d --- /dev/null +++ b/hw/peach/v2/reo_get_queue_stats.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 23, + clear_stats : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x00000100 + +#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0xfffffe00 + +#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/reo_get_queue_stats_status.h b/hw/peach/v2/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..1f302122e551 --- /dev/null +++ b/hw/peach/v2/reo_get_queue_stats_status.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 27 + +struct reo_get_queue_stats_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 10, + reserved_2 : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t window_jump_2k : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + hole_count : 16, + get_queue_1k_stats_status_to_follow : 1, + reserved_24a : 3; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_25a : 4, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 10, + current_index : 10, + ssn : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + window_jump_2k : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t reserved_24a : 3, + get_queue_1k_stats_status_to_follow : 1, + hole_count : 16, + late_receive_mpdu_count : 12; + uint32_t looping_count : 4, + reserved_25a : 4, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; +#endif +}; + +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x003ff000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0xffc00000 + +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 3 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f + +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 9 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f0 + +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x0ffff000 + +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x10000000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0xe0000000 + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f000000 + +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_unblock_cache.h b/hw/peach/v2/reo_unblock_cache.h new file mode 100644 index 000000000000..56056a941b58 --- /dev/null +++ b/hw/peach/v2/reo_unblock_cache.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9 + +struct reo_unblock_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1a : 29, + cache_block_resource_index : 2, + unblock_type : 1; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 0 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 0 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 1 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 2 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006 + +#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 3 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff8 + +#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/reo_unblock_cache_status.h b/hw/peach/v2/reo_unblock_cache_status.h new file mode 100644 index 000000000000..d6c1af738a33 --- /dev/null +++ b/hw/peach/v2/reo_unblock_cache_status.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 27 + +struct reo_unblock_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + unblock_type : 1, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x00000002 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0xfffffffc + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/reo_update_rx_reo_queue.h b/hw/peach/v2/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..595960157651 --- /dev/null +++ b/hw/peach/v2/reo_update_rx_reo_queue.h @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 + +struct reo_update_rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter : 1, + update_disable_duplicate_detection : 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag : 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 10, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 3; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t clear_stat_counters : 1, + update_pn : 1, + update_pn_valid : 1, + update_pn_error_detected_flag : 1, + update_seq_2k_error_detected_flag : 1, + update_ssn : 1, + update_svld : 1, + update_ignore_ampdu_flag : 1, + update_pn_size : 1, + update_pn_handling_enable : 1, + update_pn_shall_be_uneven : 1, + update_pn_shall_be_even : 1, + update_pn_check_needed : 1, + update_ba_window_size : 1, + update_oor_mode : 1, + update_chk_2k_mode : 1, + update_rty : 1, + update_bar : 1, + update_ac : 1, + update_soft_reorder_enable : 1, + update_disable_duplicate_detection : 1, + update_associated_link_descriptor_counter : 1, + update_vld : 1, + update_receive_queue_number : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t ignore_ampdu_flag : 1, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1, + receive_queue_number : 16; + uint32_t reserved_4a : 3, + flush_from_cache : 1, + pn_valid : 1, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + ssn : 12, + svld : 1, + pn_size : 2, + ba_window_size : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x00000200 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x00002000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x00004000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x00008000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x00020000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 + +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x00600000 + +#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x000003ff + +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x00000c00 + +#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x01ffe000 + +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0xe0000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/reo_update_rx_reo_queue_status.h b/hw/peach/v2/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..5684d23ab211 --- /dev/null +++ b/hw/peach/v2/reo_update_rx_reo_queue_status.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 27 + +struct reo_update_rx_reo_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/response_end_status.h b/hw/peach/v2/response_end_status.h new file mode 100644 index 000000000000..5c46e9a20fc4 --- /dev/null +++ b/hw/peach/v2/response_end_status.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_tx : 1, + global_data_underflow_warning : 1, + response_transmit_status : 4, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + generated_response : 3, + mba_user_count : 7, + mba_fake_bitmap_count : 7, + coex_based_tx_bw : 3, + trig_response_related : 1, + reserved_0a : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8; + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + reserved_2b : 10, + only_null_delim_sent : 1, + brp_info_valid : 1, + coex_uwb_tx_while_wlan_tx : 1, + coex_lte_tx_while_wlan_tx : 1, + reserved_2a : 7; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t mu_response_bitmap_36_32 : 5, + reserved_4a : 27; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + __reserved_g_0005 : 1, + secure : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 13; +#else + uint32_t reserved_0a : 1, + trig_response_related : 1, + coex_based_tx_bw : 3, + mba_fake_bitmap_count : 7, + mba_user_count : 7, + generated_response : 3, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + response_transmit_status : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_tx : 1; + uint32_t cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 7, + coex_lte_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_tx : 1, + brp_info_valid : 1, + only_null_delim_sent : 1, + reserved_2b : 10, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t reserved_4a : 27, + mu_response_bitmap_36_32 : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t reserved_20a : 13, + __reserved_g_0005_ftm_frame_sent : 1, + secure : 1, + __reserved_g_0005 : 1, + addr3_47_32 : 16; +#endif +}; + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001 + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000002 + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000004 + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00000008 + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x000000f0 + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x00000100 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000200 + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x00001c00 + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x000fe000 + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x07f00000 + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x38000000 + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x40000000 + +#define RESPONSE_END_STATUS_RESERVED_0A_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_RESERVED_0A_LSB 31 +#define RESPONSE_END_STATUS_RESERVED_0A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_0A_MASK 0x80000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 16 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 23 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff0000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 24 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 31 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff000000 + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x00000600 + +#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 +#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 +#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x001ff800 + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x00200000 + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x00400000 + +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_LSB 23 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MSB 23 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00800000 + +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_LSB 24 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MSB 24 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x01000000 + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 25 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0xfe000000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000c +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 31 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x00000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x0000001f + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x00000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0xffffffe0 + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x00000014 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x00000018 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x00000018 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff0000 + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000001c +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x00000020 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x00020000 + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x00040000 + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff80000 + +#endif diff --git a/hw/peach/v2/response_start_status.h b/hw/peach/v2/response_start_status.h new file mode 100644 index 000000000000..2f01116e170d --- /dev/null +++ b/hw/peach/v2/response_start_status.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, + __reserved_g_0012 : 2, + trig_response_related : 1, + response_sta_count : 7, + reserved : 19; + uint32_t phy_ppdu_id : 16, + sw_peer_id : 16; +#else + uint32_t reserved : 19, + response_sta_count : 7, + trig_response_related : 1, + __reserved_g_0012 : 2, + generated_response : 3; + uint32_t sw_peer_id : 16, + phy_ppdu_id : 16; +#endif +}; + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x00000007 + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x00000020 + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x00001fc0 + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0xffffe000 + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 0 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 15 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x00000004 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 16 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 31 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/ru_allocation_160_info.h b/hw/peach/v2/ru_allocation_160_info.h new file mode 100644 index 000000000000..23cb0e5bf09c --- /dev/null +++ b/hw/peach/v2/ru_allocation_160_info.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, + ru_allocation_band0_1 : 9, + reserved_0a : 6, + ru_allocations_01_subband80_mask : 4, + ru_allocations_23_subband80_mask : 4; + uint32_t ru_allocation_band0_2 : 9, + ru_allocation_band0_3 : 9, + reserved_1a : 14; + uint32_t ru_allocation_band1_0 : 9, + ru_allocation_band1_1 : 9, + reserved_2a : 14; + uint32_t ru_allocation_band1_2 : 9, + ru_allocation_band1_3 : 9, + reserved_3a : 14; +#else + uint32_t ru_allocations_23_subband80_mask : 4, + ru_allocations_01_subband80_mask : 4, + reserved_0a : 6, + ru_allocation_band0_1 : 9, + ru_allocation_band0_0 : 9; + uint32_t reserved_1a : 14, + ru_allocation_band0_3 : 9, + ru_allocation_band0_2 : 9; + uint32_t reserved_2a : 14, + ru_allocation_band1_1 : 9, + ru_allocation_band1_0 : 9; + uint32_t reserved_3a : 14, + ru_allocation_band1_3 : 9, + ru_allocation_band1_2 : 9; +#endif +}; + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/hw/peach/v2/rx_attention.h b/hw/peach/v2/rx_attention.h new file mode 100644 index 000000000000..b2e743ca1681 --- /dev/null +++ b/hw/peach/v2/rx_attention.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + reserved_1b : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + cce_match : 1, + order : 1, + fragment_flag : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_1a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_2 : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + sa_is_valid : 1, + da_is_mcbc : 1, + da_is_valid : 1, + msdu_limit_error : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + amsdu_parser_error : 1, + wifi_parser_error : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1; +#endif +}; + +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_ATTENTION_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_RESERVED_0_LSB 9 +#define RX_ATTENTION_RESERVED_0_MSB 15 +#define RX_ATTENTION_RESERVED_0_MASK 0x0000fe00 + +#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 +#define RX_ATTENTION_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_FIRST_MPDU_MSB 0 +#define RX_ATTENTION_FIRST_MPDU_MASK 0x00000001 + +#define RX_ATTENTION_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_RESERVED_1A_LSB 1 +#define RX_ATTENTION_RESERVED_1A_MSB 1 +#define RX_ATTENTION_RESERVED_1A_MASK 0x00000002 + +#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_MCAST_BCAST_MSB 2 +#define RX_ATTENTION_MCAST_BCAST_MASK 0x00000004 + +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 4 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_POWER_MGMT_LSB 5 +#define RX_ATTENTION_POWER_MGMT_MSB 5 +#define RX_ATTENTION_POWER_MGMT_MASK 0x00000020 + +#define RX_ATTENTION_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_NON_QOS_LSB 6 +#define RX_ATTENTION_NON_QOS_MSB 6 +#define RX_ATTENTION_NON_QOS_MASK 0x00000040 + +#define RX_ATTENTION_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_NULL_DATA_LSB 7 +#define RX_ATTENTION_NULL_DATA_MSB 7 +#define RX_ATTENTION_NULL_DATA_MASK 0x00000080 + +#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_MGMT_TYPE_MSB 8 +#define RX_ATTENTION_MGMT_TYPE_MASK 0x00000100 + +#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_CTRL_TYPE_MSB 9 +#define RX_ATTENTION_CTRL_TYPE_MASK 0x00000200 + +#define RX_ATTENTION_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_MORE_DATA_LSB 10 +#define RX_ATTENTION_MORE_DATA_MSB 10 +#define RX_ATTENTION_MORE_DATA_MASK 0x00000400 + +#define RX_ATTENTION_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_EOSP_LSB 11 +#define RX_ATTENTION_EOSP_MSB 11 +#define RX_ATTENTION_EOSP_MASK 0x00000800 + +#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_A_MSDU_ERROR_MSB 12 +#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_FRAGMENT_FLAG_MSB 13 +#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x00002000 + +#define RX_ATTENTION_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_ORDER_LSB 14 +#define RX_ATTENTION_ORDER_MSB 14 +#define RX_ATTENTION_ORDER_MASK 0x00004000 + +#define RX_ATTENTION_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_CCE_MATCH_LSB 15 +#define RX_ATTENTION_CCE_MATCH_MSB 15 +#define RX_ATTENTION_CCE_MATCH_MASK 0x00008000 + +#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_OVERFLOW_ERR_MSB 16 +#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 17 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 19 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_SA_IDX_INVALID_MSB 20 +#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_DA_IDX_INVALID_MSB 21 +#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_ATTENTION_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_RESERVED_1B_LSB 22 +#define RX_ATTENTION_RESERVED_1B_MSB 22 +#define RX_ATTENTION_RESERVED_1B_MASK 0x00400000 + +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 24 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_ATTENTION_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_DIRECTED_LSB 25 +#define RX_ATTENTION_DIRECTED_MSB 25 +#define RX_ATTENTION_DIRECTED_MASK 0x02000000 + +#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 26 +#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 27 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_TKIP_MIC_ERR_MSB 28 +#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_DECRYPT_ERR_MSB 29 +#define RX_ATTENTION_DECRYPT_ERR_MASK 0x20000000 + +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_ATTENTION_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_FCS_ERR_LSB 31 +#define RX_ATTENTION_FCS_ERR_MSB 31 +#define RX_ATTENTION_FCS_ERR_MASK 0x80000000 + +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x00000002 + +#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x00000004 + +#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x00000008 + +#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x00000020 + +#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x00000040 + +#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_DA_IS_VALID_MSB 7 +#define RX_ATTENTION_DA_IS_VALID_MASK 0x00000080 + +#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MASK 0x00000100 + +#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_SA_IS_VALID_MSB 9 +#define RX_ATTENTION_SA_IS_VALID_MASK 0x00000200 + +#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_ATTENTION_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_RESERVED_2_LSB 14 +#define RX_ATTENTION_RESERVED_2_MSB 30 +#define RX_ATTENTION_RESERVED_2_MASK 0x7fffc000 + +#define RX_ATTENTION_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_MSDU_DONE_LSB 31 +#define RX_ATTENTION_MSDU_DONE_MSB 31 +#define RX_ATTENTION_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/rx_flow_search_entry.h b/hw/peach/v2/rx_flow_search_entry.h new file mode 100644 index 000000000000..7d128ee9101a --- /dev/null +++ b/hw/peach/v2/rx_flow_search_entry.h @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 4, + service_code : 9, + priority_valid : 1, + use_ppe : 1, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length_pmac1 : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +#else + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t dest_port : 16, + src_port : 16; + uint32_t reo_destination_handler : 2, + msdu_drop : 1, + reo_destination_indication : 5, + use_ppe : 1, + priority_valid : 1, + service_code : 9, + reserved_9 : 4, + valid : 1, + l4_protocol : 8; + uint32_t metadata : 32; + uint32_t msdu_count : 24, + lro_eligible : 1, + aggregation_count : 7; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length : 16, + cumulative_ip_length_pmac1 : 16; + uint32_t tcp_sequence_number : 32; +#endif +}; + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff + +#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 + +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 + +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 + +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 + +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f + +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_frame_1k_bitmap_ack.h b/hw/peach/v2/rx_frame_1k_bitmap_ack.h new file mode 100644 index 000000000000..2f8c702ebf02 --- /dev/null +++ b/hw/peach/v2/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 37 + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, + ba_bitmap_size : 2, + reserved_0b : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0c : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; +#else + uint32_t reserved_0c : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0b : 3, + ba_bitmap_size : 2, + reserved_0a : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; +#endif +}; + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x0000001f + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x00000380 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x00003c00 + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0xf8000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x00000034 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x00000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000003c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x00000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x00000044 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x00000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000004c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x00000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x00000054 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x00000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000005c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x00000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x00000064 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x00000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000006c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x00000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x00000074 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x00000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000007c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x00000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x00000084 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x00000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000008c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x00000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_frame_bitmap_ack.h b/hw/peach/v2/rx_frame_bitmap_ack.h new file mode 100644 index 000000000000..a651568cd1e3 --- /dev/null +++ b/hw/peach/v2/rx_frame_bitmap_ack.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 13 + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, + explicit_ack : 1, + explict_ack_type : 3, + ba_bitmap_size : 2, + reserved_0a : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0b : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0a : 3, + ba_bitmap_size : 2, + explict_ack_type : 3, + explicit_ack : 1, + no_bitmap_available : 1; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; +#endif +}; + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x00000001 + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x00000002 + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x0000001c + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x00000380 + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x00003c00 + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0xf8000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000 + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_frame_bitmap_req.h b/hw/peach/v2/rx_frame_bitmap_req.h new file mode 100644 index 000000000000..81f90becb3f7 --- /dev/null +++ b/hw/peach/v2/rx_frame_bitmap_req.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 1 + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, + user_request_type : 1, + user_number : 6, + sw_peer_id : 16, + tid_specific_request : 1, + requested_tid : 4, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + requested_tid : 4, + tid_specific_request : 1, + sw_peer_id : 16, + user_number : 6, + user_request_type : 1, + explicit_user_request : 1; +#endif +}; + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x00000001 + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x00000002 + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x000000fc + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x00ffff00 + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x01000000 + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x1e000000 + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/rx_location_info.h b/hw/peach/v2/rx_location_info.h new file mode 100644 index 000000000000..716eb17ca753 --- /dev/null +++ b/hw/peach/v2/rx_location_info.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 + +struct rx_location_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_location_info_valid : 1, + rtt_hw_ifft_mode : 1, + rtt_11az_mode : 2, + reserved_0 : 4, + rtt_num_fac : 8, + rtt_rx_chain_mask : 8, + rtt_num_streams : 8; + uint32_t rtt_first_selected_chain : 8, + rtt_second_selected_chain : 8, + rtt_cfr_status : 8, + rtt_cir_status : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_che_buffer_pointer_high8 : 8, + reserved_3 : 8, + rtt_pkt_bw_vht : 4, + rtt_pkt_bw_leg : 4, + rtt_mcs_rate : 8; + uint32_t rtt_cfo_measurement : 16, + rtt_preamble_type : 8, + rtt_gi_type : 8; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain0 : 16, + gain_chain1 : 16; + uint32_t gain_chain2 : 16, + gain_chain3 : 16; + uint32_t gain_report_status : 8, + rtt_timing_backoff_sel : 8, + rtt_fac_combined : 16; + uint32_t rtt_fac_0 : 16, + rtt_fac_1 : 16; + uint32_t rtt_fac_2 : 16, + rtt_fac_3 : 16; + uint32_t rtt_fac_4 : 16, + rtt_fac_5 : 16; + uint32_t rtt_fac_6 : 16, + rtt_fac_7 : 16; + uint32_t rtt_fac_8 : 16, + rtt_fac_9 : 16; + uint32_t rtt_fac_10 : 16, + rtt_fac_11 : 16; + uint32_t rtt_fac_12 : 16, + rtt_fac_13 : 16; + uint32_t rtt_fac_14 : 16, + rtt_fac_15 : 16; + uint32_t rtt_fac_16 : 16, + rtt_fac_17 : 16; + uint32_t rtt_fac_18 : 16, + rtt_fac_19 : 16; + uint32_t rtt_fac_20 : 16, + rtt_fac_21 : 16; + uint32_t rtt_fac_22 : 16, + rtt_fac_23 : 16; + uint32_t rtt_fac_24 : 16, + rtt_fac_25 : 16; + uint32_t rtt_fac_26 : 16, + rtt_fac_27 : 16; + uint32_t rtt_fac_28 : 16, + rtt_fac_29 : 16; + uint32_t rtt_fac_30 : 16, + rtt_fac_31 : 16; + uint32_t reserved_27a : 32; +#else + uint32_t rtt_num_streams : 8, + rtt_rx_chain_mask : 8, + rtt_num_fac : 8, + reserved_0 : 4, + rtt_11az_mode : 2, + rtt_hw_ifft_mode : 1, + rx_location_info_valid : 1; + uint32_t rtt_cir_status : 8, + rtt_cfr_status : 8, + rtt_second_selected_chain : 8, + rtt_first_selected_chain : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_mcs_rate : 8, + rtt_pkt_bw_leg : 4, + rtt_pkt_bw_vht : 4, + reserved_3 : 8, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_gi_type : 8, + rtt_preamble_type : 8, + rtt_cfo_measurement : 16; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain1 : 16, + gain_chain0 : 16; + uint32_t gain_chain3 : 16, + gain_chain2 : 16; + uint32_t rtt_fac_combined : 16, + rtt_timing_backoff_sel : 8, + gain_report_status : 8; + uint32_t rtt_fac_1 : 16, + rtt_fac_0 : 16; + uint32_t rtt_fac_3 : 16, + rtt_fac_2 : 16; + uint32_t rtt_fac_5 : 16, + rtt_fac_4 : 16; + uint32_t rtt_fac_7 : 16, + rtt_fac_6 : 16; + uint32_t rtt_fac_9 : 16, + rtt_fac_8 : 16; + uint32_t rtt_fac_11 : 16, + rtt_fac_10 : 16; + uint32_t rtt_fac_13 : 16, + rtt_fac_12 : 16; + uint32_t rtt_fac_15 : 16, + rtt_fac_14 : 16; + uint32_t rtt_fac_17 : 16, + rtt_fac_16 : 16; + uint32_t rtt_fac_19 : 16, + rtt_fac_18 : 16; + uint32_t rtt_fac_21 : 16, + rtt_fac_20 : 16; + uint32_t rtt_fac_23 : 16, + rtt_fac_22 : 16; + uint32_t rtt_fac_25 : 16, + rtt_fac_24 : 16; + uint32_t rtt_fac_27 : 16, + rtt_fac_26 : 16; + uint32_t rtt_fac_29 : 16, + rtt_fac_28 : 16; + uint32_t rtt_fac_31 : 16, + rtt_fac_30 : 16; + uint32_t reserved_27a : 32; +#endif +}; + +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 + +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 + +#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c + +#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RESERVED_0_LSB 4 +#define RX_LOCATION_INFO_RESERVED_0_MSB 7 +#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 + +#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + +#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RESERVED_3_LSB 8 +#define RX_LOCATION_INFO_RESERVED_3_MSB 15 +#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 + +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 + +#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c +#define RX_LOCATION_INFO_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_RX_END_TS_MSB 31 +#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 +#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 +#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_mpdu_desc_info.h b/hw/peach/v2/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..9893b3e53d90 --- /dev/null +++ b/hw/peach/v2/rx_mpdu_desc_info.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_count : 8, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + raw_mpdu : 1, + more_fragment_flag : 1, + src_info : 12, + mpdu_qos_control_valid : 1, + tid : 4; + uint32_t peer_meta_data : 32; +#else + uint32_t tid : 4, + mpdu_qos_control_valid : 1, + src_info : 12, + more_fragment_flag : 1, + raw_mpdu : 1, + pn_fields_contain_valid_info : 1, + bar_frame : 1, + ampdu_flag : 1, + mpdu_retry_bit : 1, + fragment_flag : 1, + msdu_count : 8; + uint32_t peer_meta_data : 32; +#endif +}; + +#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 +#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 +#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_TID_LSB 28 +#define RX_MPDU_DESC_INFO_TID_MSB 31 +#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 + +#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_mpdu_details.h b/hw/peach/v2/rx_mpdu_details.h new file mode 100644 index 000000000000..3f99e1c97f5e --- /dev/null +++ b/hw/peach/v2/rx_mpdu_details.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ + +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#else + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#endif +}; + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_mpdu_end.h b/hw/peach/v2/rx_mpdu_end.h new file mode 100644 index 000000000000..926a032546dc --- /dev/null +++ b/hw/peach/v2/rx_mpdu_end.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ + +#define NUM_OF_DWORDS_RX_MPDU_END 4 + +struct rx_mpdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 3, + rxdma1_destination_ring : 3, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 1; + uint32_t reserved_2a : 15, + rxpcu_mgmt_sequence_nr_valid : 1, + rxpcu_mgmt_sequence_nr : 16; + uint32_t __reserved_g_0002 : 32; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1b : 1, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + rxdma1_destination_ring : 3, + rxdma0_destination_ring : 3, + msdu_length_err : 1, + fcs_err : 1, + pn_fields_contain_valid_info : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + overflow_err : 1, + rx_in_tx_decrypt_byp : 1, + unsup_ktype_short_frame : 1, + reserved_1a : 11; + uint32_t rxpcu_mgmt_sequence_nr : 16, + rxpcu_mgmt_sequence_nr_valid : 1, + reserved_2a : 15; + uint32_t __reserved_g_0002 : 32; +#endif +}; + +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_END_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_RESERVED_0_LSB 9 +#define RX_MPDU_END_RESERVED_0_MSB 15 +#define RX_MPDU_END_RESERVED_0_MASK 0x0000fe00 + +#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_END_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_END_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_RESERVED_1A_LSB 0 +#define RX_MPDU_END_RESERVED_1A_MSB 10 +#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff + +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 11 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 12 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_OVERFLOW_ERR_MSB 13 +#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x00002000 + +#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 14 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x00004000 + +#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_TKIP_MIC_ERR_MSB 15 +#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x00008000 + +#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_DECRYPT_ERR_MSB 16 +#define RX_MPDU_END_DECRYPT_ERR_MASK 0x00010000 + +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 17 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 18 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +#define RX_MPDU_END_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_FCS_ERR_LSB 19 +#define RX_MPDU_END_FCS_ERR_MSB 19 +#define RX_MPDU_END_FCS_ERR_MASK 0x00080000 + +#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 20 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x00100000 + +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 23 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e00000 + +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 24 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 26 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x07000000 + +#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 27 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 29 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x38000000 + +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 30 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 30 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x40000000 + +#define RX_MPDU_END_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_RESERVED_1B_LSB 31 +#define RX_MPDU_END_RESERVED_1B_MSB 31 +#define RX_MPDU_END_RESERVED_1B_MASK 0x80000000 + +#define RX_MPDU_END_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_END_RESERVED_2A_LSB 0 +#define RX_MPDU_END_RESERVED_2A_MSB 14 +#define RX_MPDU_END_RESERVED_2A_MASK 0x00007fff + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x00000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x00008000 + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x00000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/rx_mpdu_info.h b/hw/peach/v2/rx_mpdu_info.h new file mode 100644 index 000000000000..9b6b771bce96 --- /dev/null +++ b/hw/peach/v2/rx_mpdu_info.h @@ -0,0 +1,835 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ + +#include "rxpt_classify_info.h" +#define NUM_OF_DWORDS_RX_MPDU_INFO 30 + +struct rx_mpdu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + __reserved_g_0003 : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t peer_meta_data : 32; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + __reserved_g_0005 : 1, + reserved_9a : 1, + phy_ppdu_id : 16; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t vdev_id : 8, + service_code : 9, + priority_valid : 1, + src_info : 12, + reserved_23a : 1, + __reserved_g_0006 : 1; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t authorized_to_send_wds : 1, + reserved_27a : 31; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#else + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t reserved_7a : 13, + tid : 4, + bssid_number : 4, + bssid_hit : 1, + __reserved_g_0003 : 2, + wep_key_width_for_variable_key : 2, + encrypt_type : 4, + all_frames_shall_be_encrypted : 1, + epd_en : 1; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 6, + first_delim_err : 1, + pre_delim_err_warning : 1, + receive_queue_number : 16, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t mpdu_sequence_number : 12, + mpdu_retry : 1, + encrypted : 1, + to_ds : 1, + fr_ds : 1, + reserved_11a : 1, + more_fragment_flag : 1, + mpdu_fragment_number : 4, + frame_encryption_info_valid : 1, + mpdu_ht_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_sequence_control_valid : 1, + mac_addr_ad4_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad1_valid : 1, + mpdu_duration_valid : 1, + mpdu_frame_control_valid : 1; + uint32_t peer_meta_data : 32; + uint32_t sw_peer_id : 16, + ast_index : 16; + uint32_t phy_ppdu_id : 16, + reserved_9a : 1, + __reserved_g_0005 : 1, + ast_based_lookup_valid : 1, + protocol_version_err : 1, + phy_err_during_mpdu_header : 1, + phy_err : 1, + ndp_frame : 1, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_12 : 1, + raw_mpdu : 1, + bar_frame : 1, + ampdu_flag : 1, + pre_delim_count : 12, + strip_vlan_s_tag_decap : 1, + strip_vlan_c_tag_decap : 1, + rx_insert_vlan_s_tag_padding : 1, + rx_insert_vlan_c_tag_padding : 1, + decap_type : 2, + decrypt_needed : 1, + new_peer_entry : 1, + key_id_octet : 8; + uint32_t reserved_13 : 1, + amsdu_present : 1, + directed : 1, + encrypt_required : 1, + u_apsd_trigger : 1, + order : 1, + fragment_flag : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + first_mpdu : 1, + mpdu_length : 14; + uint32_t mpdu_duration_field : 16, + mpdu_frame_control_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad2_15_0 : 16, + mac_addr_ad1_47_32 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mpdu_sequence_control_field : 16, + mac_addr_ad3_47_32 : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mpdu_qos_control_field : 16, + mac_addr_ad4_47_32 : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t __reserved_g_0006 : 1, + reserved_23a : 1, + src_info : 12, + priority_valid : 1, + service_code : 9, + vdev_id : 8; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t reserved_27a : 31, + authorized_to_send_wds : 1; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#endif +}; + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 + +#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 +#define RX_MPDU_INFO_EPD_EN_LSB 0 +#define RX_MPDU_INFO_EPD_EN_MSB 0 +#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 +#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 +#define RX_MPDU_INFO_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 +#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 +#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_INFO_TID_OFFSET 0x00000004 +#define RX_MPDU_INFO_TID_LSB 15 +#define RX_MPDU_INFO_TID_MSB 18 +#define RX_MPDU_INFO_TID_MASK 0x00078000 + +#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 +#define RX_MPDU_INFO_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_RESERVED_7A_MSB 31 +#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c +#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c +#define RX_MPDU_INFO_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_RESERVED_2A_MSB 31 +#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_INFO_PN_31_0_LSB 0 +#define RX_MPDU_INFO_PN_31_0_MSB 31 +#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_INFO_PN_63_32_LSB 0 +#define RX_MPDU_INFO_PN_63_32_MSB 31 +#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_INFO_PN_95_64_LSB 0 +#define RX_MPDU_INFO_PN_95_64_MSB 31 +#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_INFO_PN_127_96_LSB 0 +#define RX_MPDU_INFO_PN_127_96_MSB 31 +#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x00000020 +#define RX_MPDU_INFO_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 +#define RX_MPDU_INFO_FR_DS_LSB 16 +#define RX_MPDU_INFO_FR_DS_MSB 16 +#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 + +#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 +#define RX_MPDU_INFO_TO_DS_LSB 17 +#define RX_MPDU_INFO_TO_DS_MSB 17 +#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 + +#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 +#define RX_MPDU_INFO_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 +#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_AST_INDEX_MSB 15 +#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 +#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c +#define RX_MPDU_INFO_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_PHY_ERR_MSB 10 +#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x0000002c +#define RX_MPDU_INFO_RESERVED_9A_LSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 + +#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 +#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_RESERVED_12_MSB 31 +#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 +#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_NON_QOS_LSB 19 +#define RX_MPDU_INFO_NON_QOS_MSB 19 +#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_NULL_DATA_MSB 20 +#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_MORE_DATA_MSB 23 +#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_EOSP_LSB 24 +#define RX_MPDU_INFO_EOSP_MSB 24 +#define RX_MPDU_INFO_EOSP_MASK 0x01000000 + +#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_ORDER_LSB 26 +#define RX_MPDU_INFO_ORDER_MSB 26 +#define RX_MPDU_INFO_ORDER_MASK 0x04000000 + +#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_DIRECTED_LSB 29 +#define RX_MPDU_INFO_DIRECTED_MSB 29 +#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_RESERVED_13_MSB 31 +#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_INFO_VDEV_ID_LSB 0 +#define RX_MPDU_INFO_VDEV_ID_MSB 7 +#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff + +#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 +#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 +#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 + +#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 + +#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_INFO_SRC_INFO_LSB 18 +#define RX_MPDU_INFO_SRC_INFO_MSB 29 +#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 + +#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_INFO_RESERVED_23A_LSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 + +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + +#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_INFO_RESERVED_27A_LSB 1 +#define RX_MPDU_INFO_RESERVED_27A_MSB 31 +#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe + +#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_INFO_RESERVED_28A_LSB 0 +#define RX_MPDU_INFO_RESERVED_28A_MSB 31 +#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff + +#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_INFO_RESERVED_29A_LSB 0 +#define RX_MPDU_INFO_RESERVED_29A_MSB 31 +#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_mpdu_link_ptr.h b/hw/peach/v2/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..6b0062a90d58 --- /dev/null +++ b/hw/peach/v2/rx_mpdu_link_ptr.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info mpdu_link_desc_addr_info; +#else + struct buffer_addr_info mpdu_link_desc_addr_info; +#endif +}; + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/rx_mpdu_start.h b/hw/peach/v2/rx_mpdu_start.h new file mode 100644 index 000000000000..8f6b7b650d39 --- /dev/null +++ b/hw/peach/v2/rx_mpdu_start.h @@ -0,0 +1,617 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ + +#include "rx_mpdu_info.h" +#define NUM_OF_DWORDS_RX_MPDU_START 30 + +struct rx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_info rx_mpdu_info_details; +#else + struct rx_mpdu_info rx_mpdu_info_details; +#endif +}; + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000024 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_msdu_desc_info.h b/hw/peach/v2/rx_msdu_desc_info.h new file mode 100644 index 000000000000..369c2574e374 --- /dev/null +++ b/hw/peach/v2/rx_msdu_desc_info.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 + +struct rx_msdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + msdu_drop : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + fr_ds : 1, + to_ds : 1, + intra_bss : 1, + dest_chip_id : 2, + decap_format : 2, + __reserved_g_0015 : 1; +#else + uint32_t __reserved_g_0015 : 1, + decap_format : 2, + dest_chip_id : 2, + intra_bss : 1, + to_ds : 1, + fr_ds : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + l3_header_padding_msb : 1, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + msdu_drop : 1, + msdu_length : 14, + msdu_continuation : 1, + last_msdu_in_mpdu_flag : 1, + first_msdu_in_mpdu_flag : 1; +#endif +}; + +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 + +#endif diff --git a/hw/peach/v2/rx_msdu_details.h b/hw/peach/v2/rx_msdu_details.h new file mode 100644 index 000000000000..45e67d58c104 --- /dev/null +++ b/hw/peach/v2/rx_msdu_details.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_msdu_ext_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#else + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#endif +}; + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/peach/v2/rx_msdu_end.h b/hw/peach/v2/rx_msdu_end.h new file mode 100644 index 000000000000..6cce25b808b1 --- /dev/null +++ b/hw/peach/v2/rx_msdu_end.h @@ -0,0 +1,1097 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ + +#define NUM_OF_DWORDS_RX_MSDU_END 32 + +struct rx_msdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t reserved_2a : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t sa_sw_peer_id : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + to_ds : 1, + tid : 4, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + fr_ds : 1, + ip_chksum_fail_copy : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + use_ppe : 1, + __reserved_g_0003 : 2, + vlan_ctag_stripped : 1, + vlan_stag_stripped : 1, + fragment_flag : 1; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + tcp_udp_chksum : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + tcp_udp_chksum_fail_copy : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + cce_match : 1, + amsdu_parser_error : 1, + cumulative_ip_length : 16; + uint32_t key_id_octet : 8, + reserved_16a : 24; + uint32_t reserved_17a : 6, + service_code : 9, + priority_valid : 1, + intra_bss : 1, + dest_chip_id : 2, + multicast_echo : 1, + wds_learning_event : 1, + wds_roaming_event : 1, + wds_keep_alive_event : 1, + __reserved_g_0015 : 1, + reserved_17b : 8; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 7, + msdu_done_copy : 1; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t reserved_28a : 16, + sa_15_0 : 16; + uint32_t sa_47_16 : 32; + uint32_t first_mpdu : 1, + reserved_30a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + reserved_30b : 1, + order : 1, + wifi_parser_error : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + amsdu_addr_mismatch : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t reserved_31a : 10, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_31b : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1a : 2, + reported_mpdu_length : 14, + ip_hdr_chksum : 16; + uint32_t cumulative_l3_checksum : 16, + cce_classify_not_done_cce_dis : 1, + cce_classify_not_done_truncate : 1, + cce_super_rule : 6, + reserved_2a : 8; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t l3_type : 16, + reserved_5a : 2, + sa_offset_valid : 1, + da_offset_valid : 1, + sa_offset : 6, + da_offset : 6; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t window_size : 16, + reserved_9a : 6, + lro_eligible : 1, + tcp_flag : 9; + uint32_t ip_chksum_fail_copy : 1, + fr_ds : 1, + last_msdu : 1, + first_msdu : 1, + l3_header_padding : 2, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + tid : 4, + to_ds : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + sa_sw_peer_id : 16; + uint32_t da_idx_or_sw_peer_id : 16, + sa_idx : 16; + uint32_t fragment_flag : 1, + vlan_stag_stripped : 1, + vlan_ctag_stripped : 1, + __reserved_g_0003 : 2, + use_ppe : 1, + flow_idx : 20, + reo_destination_indication : 5, + msdu_drop : 1; + uint32_t fse_metadata : 32; + uint32_t tcp_udp_chksum : 16, + cce_metadata : 16; + uint32_t cumulative_ip_length : 16, + amsdu_parser_error : 1, + cce_match : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1, + msdu_limit_error : 1, + tcp_udp_chksum_fail_copy : 1, + fisa_timeout : 1, + flow_aggregation_continuation : 1, + aggregation_count : 8; + uint32_t reserved_16a : 24, + key_id_octet : 8; + uint32_t reserved_17b : 8, + __reserved_g_0015 : 1, + wds_keep_alive_event : 1, + wds_roaming_event : 1, + wds_learning_event : 1, + multicast_echo : 1, + dest_chip_id : 2, + intra_bss : 1, + priority_valid : 1, + service_code : 9, + reserved_17a : 6; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t msdu_done_copy : 1, + mimo_ss_bitmap : 7, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t sa_15_0 : 16, + reserved_28a : 16; + uint32_t sa_47_16 : 32; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + amsdu_addr_mismatch : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + wifi_parser_error : 1, + order : 1, + reserved_30b : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_30a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_31b : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + reserved_31a : 10; +#endif +}; + +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_END_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_RESERVED_0_LSB 9 +#define RX_MSDU_END_RESERVED_0_MSB 15 +#define RX_MSDU_END_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_END_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 15 +#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 16 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 29 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 + +#define RX_MSDU_END_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_END_RESERVED_1A_LSB 30 +#define RX_MSDU_END_RESERVED_1A_MSB 31 +#define RX_MSDU_END_RESERVED_1A_MASK 0xc0000000 + +#define RX_MSDU_END_RESERVED_2A_OFFSET 0x00000008 +#define RX_MSDU_END_RESERVED_2A_LSB 0 +#define RX_MSDU_END_RESERVED_2A_MSB 7 +#define RX_MSDU_END_RESERVED_2A_MASK 0x000000ff + +#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 +#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x00003f00 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000c +#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff + +#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x00000010 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0xffffffff + +#define RX_MSDU_END_DA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_DA_OFFSET_LSB 0 +#define RX_MSDU_END_DA_OFFSET_MSB 5 +#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f + +#define RX_MSDU_END_SA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_SA_OFFSET_LSB 6 +#define RX_MSDU_END_SA_OFFSET_MSB 11 +#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc0 + +#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_DA_OFFSET_VALID_MSB 12 +#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x00001000 + +#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_SA_OFFSET_VALID_MSB 13 +#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x00002000 + +#define RX_MSDU_END_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_RESERVED_5A_LSB 14 +#define RX_MSDU_END_RESERVED_5A_MSB 15 +#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c000 + +#define RX_MSDU_END_L3_TYPE_OFFSET 0x00000014 +#define RX_MSDU_END_L3_TYPE_LSB 16 +#define RX_MSDU_END_L3_TYPE_MSB 31 +#define RX_MSDU_END_L3_TYPE_MASK 0xffff0000 + +#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x00000018 +#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0xffffffff + +#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_TCP_FLAG_LSB 0 +#define RX_MSDU_END_TCP_FLAG_MSB 8 +#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff + +#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_LRO_ELIGIBLE_MSB 9 +#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x00000200 + +#define RX_MSDU_END_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_RESERVED_9A_LSB 10 +#define RX_MSDU_END_RESERVED_9A_MSB 15 +#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc00 + +#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_WINDOW_SIZE_MSB 31 +#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff0000 + +#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 +#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 +#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x0000ffff + +#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x00010000 + +#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x00020000 + +#define RX_MSDU_END_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_END_TO_DS_LSB 18 +#define RX_MSDU_END_TO_DS_MSB 18 +#define RX_MSDU_END_TO_DS_MASK 0x00040000 + +#define RX_MSDU_END_TID_OFFSET 0x00000028 +#define RX_MSDU_END_TID_LSB 19 +#define RX_MSDU_END_TID_MSB 22 +#define RX_MSDU_END_TID_MASK 0x00780000 + +#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_SA_IS_VALID_MSB 23 +#define RX_MSDU_END_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_DA_IS_VALID_MSB 24 +#define RX_MSDU_END_DA_IS_VALID_MASK 0x01000000 + +#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MASK 0x02000000 + +#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x00000028 +#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 +#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x0c000000 + +#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_FIRST_MSDU_MSB 28 +#define RX_MSDU_END_FIRST_MSDU_MASK 0x10000000 + +#define RX_MSDU_END_LAST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_LAST_MSDU_LSB 29 +#define RX_MSDU_END_LAST_MSDU_MSB 29 +#define RX_MSDU_END_LAST_MSDU_MASK 0x20000000 + +#define RX_MSDU_END_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_END_FR_DS_LSB 30 +#define RX_MSDU_END_FR_DS_MSB 30 +#define RX_MSDU_END_FR_DS_MASK 0x40000000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x00000028 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x80000000 + +#define RX_MSDU_END_SA_IDX_OFFSET 0x0000002c +#define RX_MSDU_END_SA_IDX_LSB 0 +#define RX_MSDU_END_SA_IDX_MSB 15 +#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff + +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 31 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_MSDU_DROP_OFFSET 0x00000030 +#define RX_MSDU_END_MSDU_DROP_LSB 0 +#define RX_MSDU_END_MSDU_DROP_MSB 0 +#define RX_MSDU_END_MSDU_DROP_MASK 0x00000001 + +#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x00000030 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x0000003e + +#define RX_MSDU_END_FLOW_IDX_OFFSET 0x00000030 +#define RX_MSDU_END_FLOW_IDX_LSB 6 +#define RX_MSDU_END_FLOW_IDX_MSB 25 +#define RX_MSDU_END_FLOW_IDX_MASK 0x03ffffc0 + +#define RX_MSDU_END_USE_PPE_OFFSET 0x00000030 +#define RX_MSDU_END_USE_PPE_LSB 26 +#define RX_MSDU_END_USE_PPE_MSB 26 +#define RX_MSDU_END_USE_PPE_MASK 0x04000000 + +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x00000030 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x20000000 + +#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x00000030 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x40000000 + +#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x00000030 +#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MSDU_END_FSE_METADATA_OFFSET 0x00000034 +#define RX_MSDU_END_FSE_METADATA_LSB 0 +#define RX_MSDU_END_FSE_METADATA_MSB 31 +#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff + +#define RX_MSDU_END_CCE_METADATA_OFFSET 0x00000038 +#define RX_MSDU_END_CCE_METADATA_LSB 0 +#define RX_MSDU_END_CCE_METADATA_MSB 15 +#define RX_MSDU_END_CCE_METADATA_MASK 0x0000ffff + +#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x00000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000003c +#define RX_MSDU_END_AGGREGATION_COUNT_LSB 0 +#define RX_MSDU_END_AGGREGATION_COUNT_MSB 7 +#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff + +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 8 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 8 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 + +#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_FISA_TIMEOUT_LSB 9 +#define RX_MSDU_END_FISA_TIMEOUT_MSB 9 +#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x00000200 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000003c +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 10 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 10 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x00000400 + +#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000003c +#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 11 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 11 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x00000800 + +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 12 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 12 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x00001000 + +#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 13 +#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 13 +#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x00002000 + +#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000003c +#define RX_MSDU_END_CCE_MATCH_LSB 14 +#define RX_MSDU_END_CCE_MATCH_MSB 14 +#define RX_MSDU_END_CCE_MATCH_MASK 0x00004000 + +#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000003c +#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x00008000 + +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000003c +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x00000040 +#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 +#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MSDU_END_RESERVED_16A_OFFSET 0x00000040 +#define RX_MSDU_END_RESERVED_16A_LSB 8 +#define RX_MSDU_END_RESERVED_16A_MSB 31 +#define RX_MSDU_END_RESERVED_16A_MASK 0xffffff00 + +#define RX_MSDU_END_RESERVED_17A_OFFSET 0x00000044 +#define RX_MSDU_END_RESERVED_17A_LSB 0 +#define RX_MSDU_END_RESERVED_17A_MSB 5 +#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f + +#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x00000044 +#define RX_MSDU_END_SERVICE_CODE_LSB 6 +#define RX_MSDU_END_SERVICE_CODE_MSB 14 +#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc0 + +#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x00000044 +#define RX_MSDU_END_PRIORITY_VALID_LSB 15 +#define RX_MSDU_END_PRIORITY_VALID_MSB 15 +#define RX_MSDU_END_PRIORITY_VALID_MASK 0x00008000 + +#define RX_MSDU_END_INTRA_BSS_OFFSET 0x00000044 +#define RX_MSDU_END_INTRA_BSS_LSB 16 +#define RX_MSDU_END_INTRA_BSS_MSB 16 +#define RX_MSDU_END_INTRA_BSS_MASK 0x00010000 + +#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x00000044 +#define RX_MSDU_END_DEST_CHIP_ID_LSB 17 +#define RX_MSDU_END_DEST_CHIP_ID_MSB 18 +#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x00060000 + +#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x00000044 +#define RX_MSDU_END_MULTICAST_ECHO_LSB 19 +#define RX_MSDU_END_MULTICAST_ECHO_MSB 19 +#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x00080000 + +#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 20 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 20 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x00100000 + +#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 21 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 21 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x00200000 + +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 22 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 22 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x00400000 + +#define RX_MSDU_END_RESERVED_17B_OFFSET 0x00000044 +#define RX_MSDU_END_RESERVED_17B_LSB 24 +#define RX_MSDU_END_RESERVED_17B_MSB 31 +#define RX_MSDU_END_RESERVED_17B_MASK 0xff000000 + +#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_END_MSDU_LENGTH_LSB 0 +#define RX_MSDU_END_MSDU_LENGTH_MSB 13 +#define RX_MSDU_END_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_END_STBC_OFFSET 0x00000048 +#define RX_MSDU_END_STBC_LSB 14 +#define RX_MSDU_END_STBC_MSB 14 +#define RX_MSDU_END_STBC_MASK 0x00004000 + +#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x00000048 +#define RX_MSDU_END_IPSEC_ESP_LSB 15 +#define RX_MSDU_END_IPSEC_ESP_MSB 15 +#define RX_MSDU_END_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_END_L3_OFFSET_OFFSET 0x00000048 +#define RX_MSDU_END_L3_OFFSET_LSB 16 +#define RX_MSDU_END_L3_OFFSET_MSB 22 +#define RX_MSDU_END_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_END_IPSEC_AH_OFFSET 0x00000048 +#define RX_MSDU_END_IPSEC_AH_LSB 23 +#define RX_MSDU_END_IPSEC_AH_MSB 23 +#define RX_MSDU_END_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_END_L4_OFFSET_OFFSET 0x00000048 +#define RX_MSDU_END_L4_OFFSET_LSB 24 +#define RX_MSDU_END_L4_OFFSET_MSB 31 +#define RX_MSDU_END_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000004c +#define RX_MSDU_END_MSDU_NUMBER_LSB 0 +#define RX_MSDU_END_MSDU_NUMBER_MSB 7 +#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000004c +#define RX_MSDU_END_DECAP_FORMAT_LSB 8 +#define RX_MSDU_END_DECAP_FORMAT_MSB 9 +#define RX_MSDU_END_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_IPV4_PROTO_LSB 10 +#define RX_MSDU_END_IPV4_PROTO_MSB 10 +#define RX_MSDU_END_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_IPV6_PROTO_LSB 11 +#define RX_MSDU_END_IPV6_PROTO_MSB 11 +#define RX_MSDU_END_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_PROTO_LSB 12 +#define RX_MSDU_END_TCP_PROTO_MSB 12 +#define RX_MSDU_END_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_UDP_PROTO_LSB 13 +#define RX_MSDU_END_UDP_PROTO_MSB 13 +#define RX_MSDU_END_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000004c +#define RX_MSDU_END_IP_FRAG_LSB 14 +#define RX_MSDU_END_IP_FRAG_MSB 14 +#define RX_MSDU_END_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_END_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000004c +#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000004c +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000004c +#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_END_LDPC_OFFSET 0x0000004c +#define RX_MSDU_END_LDPC_LSB 23 +#define RX_MSDU_END_LDPC_MSB 23 +#define RX_MSDU_END_LDPC_MASK 0x00800000 + +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000004c +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x00000050 +#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x00000050 +#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_END_VLAN_STAG_CI_MASK 0xffff0000 + +#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x00000054 +#define RX_MSDU_END_PEER_META_DATA_LSB 0 +#define RX_MSDU_END_PEER_META_DATA_MSB 31 +#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff + +#define RX_MSDU_END_USER_RSSI_OFFSET 0x00000058 +#define RX_MSDU_END_USER_RSSI_LSB 0 +#define RX_MSDU_END_USER_RSSI_MSB 7 +#define RX_MSDU_END_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_END_PKT_TYPE_OFFSET 0x00000058 +#define RX_MSDU_END_PKT_TYPE_LSB 8 +#define RX_MSDU_END_PKT_TYPE_MSB 11 +#define RX_MSDU_END_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_END_SGI_OFFSET 0x00000058 +#define RX_MSDU_END_SGI_LSB 12 +#define RX_MSDU_END_SGI_MSB 13 +#define RX_MSDU_END_SGI_MASK 0x00003000 + +#define RX_MSDU_END_RATE_MCS_OFFSET 0x00000058 +#define RX_MSDU_END_RATE_MCS_LSB 14 +#define RX_MSDU_END_RATE_MCS_MSB 17 +#define RX_MSDU_END_RATE_MCS_MASK 0x0003c000 + +#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x00000058 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x001c0000 + +#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x00000058 +#define RX_MSDU_END_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_END_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x00000058 +#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 +#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x7f000000 + +#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x00000058 +#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x80000000 + +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000005c +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000060 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x00000064 +#define RX_MSDU_END_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_END_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000068 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000006c +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 31 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_END_RESERVED_28A_OFFSET 0x00000070 +#define RX_MSDU_END_RESERVED_28A_LSB 0 +#define RX_MSDU_END_RESERVED_28A_MSB 15 +#define RX_MSDU_END_RESERVED_28A_MASK 0x0000ffff + +#define RX_MSDU_END_SA_15_0_OFFSET 0x00000070 +#define RX_MSDU_END_SA_15_0_LSB 16 +#define RX_MSDU_END_SA_15_0_MSB 31 +#define RX_MSDU_END_SA_15_0_MASK 0xffff0000 + +#define RX_MSDU_END_SA_47_16_OFFSET 0x00000074 +#define RX_MSDU_END_SA_47_16_LSB 0 +#define RX_MSDU_END_SA_47_16_MSB 31 +#define RX_MSDU_END_SA_47_16_MASK 0xffffffff + +#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x00000078 +#define RX_MSDU_END_FIRST_MPDU_LSB 0 +#define RX_MSDU_END_FIRST_MPDU_MSB 0 +#define RX_MSDU_END_FIRST_MPDU_MASK 0x00000001 + +#define RX_MSDU_END_RESERVED_30A_OFFSET 0x00000078 +#define RX_MSDU_END_RESERVED_30A_LSB 1 +#define RX_MSDU_END_RESERVED_30A_MSB 1 +#define RX_MSDU_END_RESERVED_30A_MASK 0x00000002 + +#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x00000078 +#define RX_MSDU_END_MCAST_BCAST_LSB 2 +#define RX_MSDU_END_MCAST_BCAST_MSB 2 +#define RX_MSDU_END_MCAST_BCAST_MASK 0x00000004 + +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x00000078 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_MSDU_END_POWER_MGMT_OFFSET 0x00000078 +#define RX_MSDU_END_POWER_MGMT_LSB 5 +#define RX_MSDU_END_POWER_MGMT_MSB 5 +#define RX_MSDU_END_POWER_MGMT_MASK 0x00000020 + +#define RX_MSDU_END_NON_QOS_OFFSET 0x00000078 +#define RX_MSDU_END_NON_QOS_LSB 6 +#define RX_MSDU_END_NON_QOS_MSB 6 +#define RX_MSDU_END_NON_QOS_MASK 0x00000040 + +#define RX_MSDU_END_NULL_DATA_OFFSET 0x00000078 +#define RX_MSDU_END_NULL_DATA_LSB 7 +#define RX_MSDU_END_NULL_DATA_MSB 7 +#define RX_MSDU_END_NULL_DATA_MASK 0x00000080 + +#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x00000078 +#define RX_MSDU_END_MGMT_TYPE_LSB 8 +#define RX_MSDU_END_MGMT_TYPE_MSB 8 +#define RX_MSDU_END_MGMT_TYPE_MASK 0x00000100 + +#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x00000078 +#define RX_MSDU_END_CTRL_TYPE_LSB 9 +#define RX_MSDU_END_CTRL_TYPE_MSB 9 +#define RX_MSDU_END_CTRL_TYPE_MASK 0x00000200 + +#define RX_MSDU_END_MORE_DATA_OFFSET 0x00000078 +#define RX_MSDU_END_MORE_DATA_LSB 10 +#define RX_MSDU_END_MORE_DATA_MSB 10 +#define RX_MSDU_END_MORE_DATA_MASK 0x00000400 + +#define RX_MSDU_END_EOSP_OFFSET 0x00000078 +#define RX_MSDU_END_EOSP_LSB 11 +#define RX_MSDU_END_EOSP_MSB 11 +#define RX_MSDU_END_EOSP_MASK 0x00000800 + +#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x00000078 +#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_MSDU_END_RESERVED_30B_OFFSET 0x00000078 +#define RX_MSDU_END_RESERVED_30B_LSB 13 +#define RX_MSDU_END_RESERVED_30B_MSB 13 +#define RX_MSDU_END_RESERVED_30B_MASK 0x00002000 + +#define RX_MSDU_END_ORDER_OFFSET 0x00000078 +#define RX_MSDU_END_ORDER_LSB 14 +#define RX_MSDU_END_ORDER_MSB 14 +#define RX_MSDU_END_ORDER_MASK 0x00004000 + +#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x00000078 +#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x00008000 + +#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x00000078 +#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x00000078 +#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x00000078 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x00400000 + +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000078 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x00000078 +#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_MSDU_END_DIRECTED_OFFSET 0x00000078 +#define RX_MSDU_END_DIRECTED_LSB 25 +#define RX_MSDU_END_DIRECTED_MSB 25 +#define RX_MSDU_END_DIRECTED_MASK 0x02000000 + +#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x00000078 +#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_DECRYPT_ERR_LSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MASK 0x20000000 + +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_MSDU_END_FCS_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_FCS_ERR_LSB 31 +#define RX_MSDU_END_FCS_ERR_MSB 31 +#define RX_MSDU_END_FCS_ERR_MASK 0x80000000 + +#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000007c +#define RX_MSDU_END_RESERVED_31A_LSB 0 +#define RX_MSDU_END_RESERVED_31A_MSB 9 +#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff + +#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000007c +#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 10 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 12 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000007c +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000007c +#define RX_MSDU_END_RESERVED_31B_LSB 14 +#define RX_MSDU_END_RESERVED_31B_MSB 30 +#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc000 + +#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000007c +#define RX_MSDU_END_MSDU_DONE_LSB 31 +#define RX_MSDU_END_MSDU_DONE_MSB 31 +#define RX_MSDU_END_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/rx_msdu_ext_desc_info.h b/hw/peach/v2/rx_msdu_ext_desc_info.h new file mode 100644 index 000000000000..07e36cfbf1d9 --- /dev/null +++ b/hw/peach/v2/rx_msdu_ext_desc_info.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_EXT_DESC_INFO_H_ +#define _RX_MSDU_EXT_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 + +struct rx_msdu_ext_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + service_code : 9, + priority_valid : 1, + data_offset : 12, + src_link_id : 3, + reserved_0a : 2; +#else + uint32_t reserved_0a : 2, + src_link_id : 3, + data_offset : 12, + priority_valid : 1, + service_code : 9, + reo_destination_indication : 5; +#endif +}; + +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/peach/v2/rx_msdu_link.h b/hw/peach/v2/rx_msdu_link.h new file mode 100644 index 000000000000..c387c35d07fa --- /dev/null +++ b/hw/peach/v2/rx_msdu_link.h @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#else + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t reserved_3a : 15, + first_rx_msdu_link_struct : 1, + receive_queue_number : 16; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#endif +}; + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_RESERVED_3A_MSB 31 +#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 + +#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_PN_31_0_LSB 0 +#define RX_MSDU_LINK_PN_31_0_MSB 31 +#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_PN_63_32_LSB 0 +#define RX_MSDU_LINK_PN_63_32_MSB 31 +#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_PN_95_64_LSB 0 +#define RX_MSDU_LINK_PN_95_64_MSB 31 +#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_PN_127_96_LSB 0 +#define RX_MSDU_LINK_PN_127_96_MSB 31 +#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/peach/v2/rx_msdu_start.h b/hw/peach/v2/rx_msdu_start.h new file mode 100644 index 000000000000..bce674364e24 --- /dev/null +++ b/hw/peach/v2/rx_msdu_start.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ + +#define NUM_OF_DWORDS_RX_MSDU_START 10 + +struct rx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t mimo_ss_bitmap : 8, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; +#endif +}; + +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_START_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_RESERVED_0_LSB 9 +#define RX_MSDU_START_RESERVED_0_MSB 15 +#define RX_MSDU_START_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_START_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_MSDU_LENGTH_MSB 13 +#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_START_STBC_OFFSET 0x00000004 +#define RX_MSDU_START_STBC_LSB 14 +#define RX_MSDU_START_STBC_MSB 14 +#define RX_MSDU_START_STBC_MASK 0x00004000 + +#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_IPSEC_ESP_MSB 15 +#define RX_MSDU_START_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_START_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_L3_OFFSET_LSB 16 +#define RX_MSDU_START_L3_OFFSET_MSB 22 +#define RX_MSDU_START_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_START_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_IPSEC_AH_LSB 23 +#define RX_MSDU_START_IPSEC_AH_MSB 23 +#define RX_MSDU_START_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_START_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_L4_OFFSET_LSB 24 +#define RX_MSDU_START_L4_OFFSET_MSB 31 +#define RX_MSDU_START_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_MSDU_NUMBER_MSB 7 +#define RX_MSDU_START_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_START_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_DECAP_FORMAT_MSB 9 +#define RX_MSDU_START_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_IPV4_PROTO_MSB 10 +#define RX_MSDU_START_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_IPV6_PROTO_MSB 11 +#define RX_MSDU_START_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_START_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_PROTO_LSB 12 +#define RX_MSDU_START_TCP_PROTO_MSB 12 +#define RX_MSDU_START_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_START_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_UDP_PROTO_LSB 13 +#define RX_MSDU_START_UDP_PROTO_MSB 13 +#define RX_MSDU_START_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_START_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_IP_FRAG_LSB 14 +#define RX_MSDU_START_IP_FRAG_MSB 14 +#define RX_MSDU_START_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x00000008 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x00000008 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_START_LDPC_OFFSET 0x00000008 +#define RX_MSDU_START_LDPC_LSB 23 +#define RX_MSDU_START_LDPC_MSB 23 +#define RX_MSDU_START_LDPC_MASK 0x00800000 + +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 31 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_START_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_USER_RSSI_LSB 0 +#define RX_MSDU_START_USER_RSSI_MSB 7 +#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_START_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_PKT_TYPE_LSB 8 +#define RX_MSDU_START_PKT_TYPE_MSB 11 +#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_START_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_SGI_LSB 12 +#define RX_MSDU_START_SGI_MSB 13 +#define RX_MSDU_START_SGI_MASK 0x00003000 + +#define RX_MSDU_START_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_RATE_MCS_LSB 14 +#define RX_MSDU_START_RATE_MCS_MSB 17 +#define RX_MSDU_START_RATE_MCS_MASK 0x0003c000 + +#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c0000 + +#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x00000014 +#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 31 +#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff000000 + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000001c +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x00000020 +#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x00000024 +#define RX_MSDU_START_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_START_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x00000024 +#define RX_MSDU_START_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_START_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/rx_ppdu_ack_report.h b/hw/peach/v2/rx_ppdu_ack_report.h new file mode 100644 index 000000000000..c3fe3f04e921 --- /dev/null +++ b/hw/peach/v2/rx_ppdu_ack_report.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 1 + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; +#else + struct ack_report ack_report_details; +#endif +}; + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x00000100 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x0000fe00 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/rx_ppdu_end_user_stats.h b/hw/peach/v2/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..e4b4022cf0a8 --- /dev/null +++ b/hw/peach/v2/rx_ppdu_end_user_stats.h @@ -0,0 +1,703 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 + +struct rx_ppdu_end_user_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + expected_response_ack_or_ba : 1, + reserved_1a : 11; + uint32_t sw_peer_id : 16, + mpdu_cnt_fcs_err : 11, + sw2rxdma0_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + fw2rxdma_pmac1_buf_source_used : 1; + uint32_t mpdu_cnt_fcs_ok : 11, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_null_valid : 1, + rxdma2fw_pmac1_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma2reo_remote0_ring_used : 1, + rxdma2reo_remote1_ring_used : 1, + reserved_3b : 5; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap : 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + retried_msdu_count : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + frame_control_info_null_valid : 1, + frame_control_field_null : 16, + retried_mpdu_count : 11, + reserved_23a : 3; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_24a : 4, + frame_control_info_mgmt_ctrl_valid : 1, + mac_addr_ad2_valid : 1, + mcast_bcast : 1, + frame_control_field_mgmt_ctrl : 16; + uint32_t user_ppdu_len : 24, + reserved_25a : 8; + uint32_t mac_addr_ad2_31_0 : 32; + uint32_t mac_addr_ad2_47_32 : 16, + amsdu_msdu_count : 16; + uint32_t non_amsdu_msdu_count : 16, + ucast_msdu_count : 16; + uint32_t bcast_msdu_count : 16, + mcast_bcast_msdu_count : 16; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t reserved_1a : 11, + expected_response_ack_or_ba : 1, + nss : 3, + mcs : 4, + sta_full_aid : 13; + uint32_t fw2rxdma_pmac1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma0_buf_source_used : 1, + mpdu_cnt_fcs_err : 11, + sw_peer_id : 16; + uint32_t reserved_3b : 5, + rxdma2reo_remote1_ring_used : 1, + rxdma2reo_remote0_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma_release_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac1_ring_used : 1, + ht_control_info_null_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_valid : 1, + qos_control_info_valid : 1, + frame_control_info_valid : 1, + mpdu_cnt_fcs_ok : 11; + uint32_t frame_control_field : 16, + ast_index : 16; + uint32_t qos_control_field : 16, + first_data_seq_ctrl : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t tcp_msdu_count : 16, + udp_msdu_count : 16; + uint32_t tcp_ack_msdu_count : 16, + other_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_eosp_bitmap : 16, + received_qos_data_tid_bitmap : 16; + uint32_t qosctrl_15_8_tid3 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid0 : 8; + uint32_t qosctrl_15_8_tid7 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid4 : 8; + uint32_t qosctrl_15_8_tid11 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid8 : 8; + uint32_t qosctrl_15_8_tid15 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid12 : 8; + uint32_t ampdu_delim_ok_count_6_0 : 7, + mpdu_ok_byte_count : 25; + uint32_t ampdu_delim_ok_count_13_7 : 7, + ampdu_delim_err_count : 25; + uint32_t ampdu_delim_ok_count_20_14 : 7, + mpdu_err_byte_count : 25; + uint32_t retried_msdu_count : 16, + non_consecutive_delimiter_err : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t reserved_23a : 3, + retried_mpdu_count : 11, + frame_control_field_null : 16, + frame_control_info_null_valid : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t frame_control_field_mgmt_ctrl : 16, + mcast_bcast : 1, + mac_addr_ad2_valid : 1, + frame_control_info_mgmt_ctrl_valid : 1, + reserved_24a : 4, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_25a : 8, + user_ppdu_len : 24; + uint32_t mac_addr_ad2_31_0 : 32; + uint32_t amsdu_msdu_count : 16, + mac_addr_ad2_47_32 : 16; + uint32_t ucast_msdu_count : 16, + non_amsdu_msdu_count : 16; + uint32_t mcast_bcast_msdu_count : 16, + bcast_msdu_count : 16; +#endif +}; + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 0 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 12 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff + +#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_MCS_LSB 13 +#define RX_PPDU_END_USER_STATS_MCS_MSB 16 +#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e000 + +#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_NSS_LSB 17 +#define RX_PPDU_END_USER_STATS_NSS_MSB 19 +#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e0000 + +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 20 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 20 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 21 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe00000 + +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x07ff0000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x08000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x10000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x20000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x40000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x80000000 + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 10 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 11 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 11 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x00000800 + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 12 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 12 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x00001000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00004000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 15 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 15 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x00008000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 16 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 16 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x00010000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 17 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 17 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x00020000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 18 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 18 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x00040000 + +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 19 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 19 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x00080000 + +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 20 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 20 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 21 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 24 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e00000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 25 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 25 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x02000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 26 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 26 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x04000000 + +#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 27 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf8000000 + +#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 0 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 15 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 1 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 1 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 2 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 17 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc + +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 18 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 28 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc0000 + +#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 29 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe0000000 + +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x00001e00 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x00004000 + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x00008000 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x00000064 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 0 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 23 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff + +#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x00000064 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 24 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x00000068 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000006c +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 15 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000006c +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x00000070 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x00000070 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x00000074 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x00000074 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/rx_ppdu_end_user_stats_ext.h b/hw/peach/v2/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..2ec070a46402 --- /dev/null +++ b/hw/peach/v2/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 + +struct rx_ppdu_end_user_stats_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + reserved_7a : 31; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t reserved_7a : 31, + corrupted_due_to_fifo_delay : 1; +#endif +}; + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe + +#endif diff --git a/hw/peach/v2/rx_ppdu_no_ack_report.h b/hw/peach/v2/rx_ppdu_no_ack_report.h new file mode 100644 index 000000000000..2500e57ed794 --- /dev/null +++ b/hw/peach/v2/rx_ppdu_no_ack_report.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 29 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0xff000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/rx_ppdu_start.h b/hw/peach/v2/rx_ppdu_start.h new file mode 100644 index 000000000000..00fea7caebfa --- /dev/null +++ b/hw/peach/v2/rx_ppdu_start.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ + +#define NUM_OF_DWORDS_RX_PPDU_START 5 + +struct rx_ppdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + preamble_time_to_rxframe : 8, + reserved_0a : 8; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; +#else + uint32_t reserved_0a : 8, + preamble_time_to_rxframe : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; +#endif +}; + +#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x00000000 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x00ff0000 + +#define RX_PPDU_START_RESERVED_0A_OFFSET 0x00000000 +#define RX_PPDU_START_RESERVED_0A_LSB 24 +#define RX_PPDU_START_RESERVED_0A_MSB 31 +#define RX_PPDU_START_RESERVED_0A_MASK 0xff000000 + +#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x00000004 +#define RX_PPDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_PPDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000c +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x00000010 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_ppdu_start_user_info.h b/hw/peach/v2/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..cb10b5dcc8ae --- /dev/null +++ b/hw/peach/v2/rx_ppdu_start_user_info.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 + +struct rx_ppdu_start_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_preamble.h b/hw/peach/v2/rx_preamble.h new file mode 100644 index 000000000000..d6bb337dc3e9 --- /dev/null +++ b/hw/peach/v2/rx_preamble.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ + +#define NUM_OF_DWORDS_RX_PREAMBLE 1 + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + pkt_type : 4, + direction : 1, + reserved_0a : 21; +#else + uint32_t reserved_0a : 21, + direction : 1, + pkt_type : 4, + num_users : 6; +#endif +}; + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x00000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x0000003f + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x00000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x000003c0 + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x00000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x00000400 + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x00000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0xfffff800 + +#endif diff --git a/hw/peach/v2/rx_reo_queue.h b/hw/peach/v2/rx_reo_queue.h new file mode 100644 index 000000000000..b0cfaff62c20 --- /dev/null +++ b/hw/peach/v2/rx_reo_queue.h @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 10, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 4; + uint32_t svld : 1, + ssn : 12, + current_index : 10, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 6, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t ptr_to_previous_aging_queue_39_32 : 8, + statistics_counter_index : 6, + reserved_13a : 18; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t last_sn_reg_index : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_30 : 8; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1b : 16, + receive_queue_number : 16; + uint32_t reserved_2b : 4, + ignore_ampdu_flag : 1, + pn_size : 2, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + ba_window_size : 10, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1; + uint32_t pn_valid : 1, + reserved_3a : 6, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + current_index : 10, + ssn : 12, + svld : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t reserved_11a : 24, + ptr_to_next_aging_queue_39_32 : 8; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t reserved_13a : 18, + statistics_counter_index : 6, + ptr_to_previous_aging_queue_39_32 : 8; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + last_sn_reg_index : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t hole_count : 16, + window_jump_2k : 4, + late_receive_mpdu_count : 12; + uint32_t reserved_30 : 8, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_RESERVED_1B_MSB 31 +#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 + +#define RX_REO_QUEUE_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_VLD_LSB 0 +#define RX_REO_QUEUE_VLD_MSB 0 +#define RX_REO_QUEUE_VLD_MASK 0x00000001 + +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 + +#define RX_REO_QUEUE_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_AC_LSB 5 +#define RX_REO_QUEUE_AC_MSB 6 +#define RX_REO_QUEUE_AC_MASK 0x00000060 + +#define RX_REO_QUEUE_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_BAR_LSB 7 +#define RX_REO_QUEUE_BAR_MSB 7 +#define RX_REO_QUEUE_BAR_MASK 0x00000080 + +#define RX_REO_QUEUE_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_RTY_LSB 8 +#define RX_REO_QUEUE_RTY_MSB 8 +#define RX_REO_QUEUE_RTY_MASK 0x00000100 + +#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 + +#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_OOR_MODE_MSB 10 +#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 + +#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 + +#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 + +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 + +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 + +#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SIZE_LSB 25 +#define RX_REO_QUEUE_PN_SIZE_MSB 26 +#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 + +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 + +#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_RESERVED_2B_LSB 28 +#define RX_REO_QUEUE_RESERVED_2B_MSB 31 +#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 + +#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_SVLD_LSB 0 +#define RX_REO_QUEUE_SVLD_MSB 0 +#define RX_REO_QUEUE_SVLD_MASK 0x00000001 + +#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_SSN_LSB 1 +#define RX_REO_QUEUE_SSN_MSB 12 +#define RX_REO_QUEUE_SSN_MASK 0x00001ffe + +#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 +#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 + +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_RESERVED_3A_LSB 25 +#define RX_REO_QUEUE_RESERVED_3A_MSB 30 +#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 + +#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_VALID_LSB 31 +#define RX_REO_QUEUE_PN_VALID_MSB 31 +#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 + +#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_PN_31_0_LSB 0 +#define RX_REO_QUEUE_PN_31_0_MSB 31 +#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_PN_63_32_LSB 0 +#define RX_REO_QUEUE_PN_63_32_MSB 31 +#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_PN_95_64_LSB 0 +#define RX_REO_QUEUE_PN_95_64_MSB 31 +#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_PN_127_96_LSB 0 +#define RX_REO_QUEUE_PN_127_96_MSB 31 +#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_RESERVED_11A_MSB 31 +#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 + +#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_RESERVED_13A_LSB 14 +#define RX_REO_QUEUE_RESERVED_13A_MSB 31 +#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 + +#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 +#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff + +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f + +#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 + +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_HOLE_COUNT_MSB 31 +#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 + +#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_RESERVED_30_LSB 24 +#define RX_REO_QUEUE_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 + +#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_reo_queue_1k.h b/hw/peach/v2/rx_reo_queue_1k.h new file mode 100644 index 000000000000..de62f7fa68ef --- /dev/null +++ b/hw/peach/v2/rx_reo_queue_1k.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_1K_H_ +#define _RX_REO_QUEUE_1K_H_ + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 + +struct rx_reo_queue_1k { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 +#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 +#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 +#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c +#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 +#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rx_reo_queue_ext.h b/hw/peach/v2/rx_reo_queue_ext.h new file mode 100644 index 000000000000..24a656c317d0 --- /dev/null +++ b/hw/peach/v2/rx_reo_queue_ext.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ + +#include "rx_mpdu_link_ptr.h" +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#endif +}; + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/rx_response_required_info.h b/hw/peach/v2/rx_response_required_info.h new file mode 100644 index 000000000000..46aececf3c93 --- /dev/null +++ b/hw/peach/v2/rx_response_required_info.h @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 15 + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + su_or_uplink_mu_reception : 1, + trigger_frame_received : 1, + __reserved_g_0012 : 2, + tb___reserved_g_0005_response_required : 2, + mac_security : 1, + filter_pass_monitor_ovrd : 1, + ast_search_incomplete : 1, + r2r_end_status_to_follow : 1, + __reserved_g_0016_listen_cca_check_at_phy_desc : 1, + __reserved_g_0016_listen_indication : 1, + three_or_more_type_subtypes : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2; + uint32_t general_frame_control : 16, + second_frame_control : 16; + uint32_t duration : 16, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + sgi : 2, + stbc : 1, + ldpc : 1, + ampdu : 1, + vht_ack : 1, + rts_ta_grp_bit : 1; + uint32_t ctrl_frame_soliciting_resp : 1, + ast_fail_for_dot11ax_su_ext : 1, + service_dynamic : 1, + m_pkt : 1, + sta_partial_aid : 12, + group_id : 6, + ctrl_resp_pwr_mgmt : 1, + response_indication : 2, + ndp_indication : 1, + ndp_frame_type : 3, + second_frame_control_valid : 1, + ack_ba_resp_more_data : 1, + reserved_3a : 1; + uint32_t ack_id : 16, + ack_id_ext : 10, + agc_cbw : 3, + service_cbw : 3; + uint32_t response_sta_count : 7, + reserved : 4, + ht_vht_sig_cbw : 3, + cts_cbw : 3, + response_ack_count : 7, + response_assoc_ack_count : 7, + txop_duration_all_ones : 1; + uint32_t response_ba32_count : 7, + response_ba64_count : 7, + response_ba128_count : 7, + response_ba256_count : 7, + multi_tid : 1, + sw_response_tlv_from_crypto : 1, + dot11ax_dl_ul_flag : 1, + emlsr_main_tlv_if : 1; + uint32_t sw_response_frame_length : 16, + response_ba512_count : 7, + response_ba1024_count : 7, + reserved_7a : 2; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + ftm_fields_valid : 1, + ftm_pe_nss : 3, + ftm_pe_ltf_size : 2, + ftm_pe_content : 1, + ftm_chain_csd_en : 1, + ftm_pe_chain_csd_en : 1; + uint32_t dot11ax_response_rate_source : 8, + dot11ax_ext_response_rate_source : 8, + sw_peer_id : 16; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + eht_duplicate_mode : 2, + force_extra_symbol : 1, + reserved_13a : 5, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, + reserved_after_struct16 : 4; +#else + uint32_t wait_sifs : 2, + wait_sifs_config_valid : 1, + three_or_more_type_subtypes : 1, + __reserved_g_0016_listen_indication : 1, + __reserved_g_0016_listen_cca_check_at_phy_desc : 1, + r2r_end_status_to_follow : 1, + ast_search_incomplete : 1, + filter_pass_monitor_ovrd : 1, + mac_security : 1, + tb___reserved_g_0005_response_required : 2, + __reserved_g_0012 : 2, + trigger_frame_received : 1, + su_or_uplink_mu_reception : 1, + phy_ppdu_id : 16; + uint32_t second_frame_control : 16, + general_frame_control : 16; + uint32_t rts_ta_grp_bit : 1, + vht_ack : 1, + ampdu : 1, + ldpc : 1, + stbc : 1, + sgi : 2, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + duration : 16; + uint32_t reserved_3a : 1, + ack_ba_resp_more_data : 1, + second_frame_control_valid : 1, + ndp_frame_type : 3, + ndp_indication : 1, + response_indication : 2, + ctrl_resp_pwr_mgmt : 1, + group_id : 6, + sta_partial_aid : 12, + m_pkt : 1, + service_dynamic : 1, + ast_fail_for_dot11ax_su_ext : 1, + ctrl_frame_soliciting_resp : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + ack_id_ext : 10, + ack_id : 16; + uint32_t txop_duration_all_ones : 1, + response_assoc_ack_count : 7, + response_ack_count : 7, + cts_cbw : 3, + ht_vht_sig_cbw : 3, + reserved : 4, + response_sta_count : 7; + uint32_t emlsr_main_tlv_if : 1, + dot11ax_dl_ul_flag : 1, + sw_response_tlv_from_crypto : 1, + multi_tid : 1, + response_ba256_count : 7, + response_ba128_count : 7, + response_ba64_count : 7, + response_ba32_count : 7; + uint32_t reserved_7a : 2, + response_ba1024_count : 7, + response_ba512_count : 7, + sw_response_frame_length : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ftm_pe_chain_csd_en : 1, + ftm_chain_csd_en : 1, + ftm_pe_content : 1, + ftm_pe_ltf_size : 2, + ftm_pe_nss : 3, + ftm_fields_valid : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t sw_peer_id : 16, + dot11ax_ext_response_rate_source : 8, + dot11ax_response_rate_source : 8; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_13a : 5, + force_extra_symbol : 1, + eht_duplicate_mode : 2, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_after_struct16 : 4, + he_a_control_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00300000 + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x00400000 + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x00800000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x01000000 + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x02000000 + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0xc0000000 + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x00000004 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x00000004 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x000f0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x00100000 + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x01e00000 + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x06000000 + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x08000000 + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 0 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x00000001 + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 1 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 1 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x00000002 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 2 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 2 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x00000004 + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 3 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 3 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x00000008 + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 4 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff0 + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f0000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x00400000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x01800000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x02000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x03ff0000 + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x1c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0xe0000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x00000780 + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x00003800 + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f000000 + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x0000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x00003f80 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x001fc000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x0fe00000 + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f800000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc0000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x00000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0xffffffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x00000024 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x00000024 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x00000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0xffffffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x00800000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x07000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x18000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x000000ff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x0000ff00 + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c0000 + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x00100000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e00000 + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x0fff0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/rx_rxpcu_classification_overview.h b/hw/peach/v2/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..d7904b0f0368 --- /dev/null +++ b/hw/peach/v2/rx_rxpcu_classification_overview.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + filter_pass_monitor_ovrd_mpdus : 1, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + reserved_0 : 7, + phy_ppdu_id : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + filter_pass_monitor_ovrd_mpdus : 1, + phyrx_abort_received : 1, + monitor_other_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + filter_pass_mpdus : 1; +#endif +}; + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/rx_start_param.h b/hw/peach/v2/rx_start_param.h new file mode 100644 index 000000000000..1902703b02d1 --- /dev/null +++ b/hw/peach/v2/rx_start_param.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ + +#define NUM_OF_DWORDS_RX_START_PARAM 1 + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + reserved_0a : 12, + remaining_rx_time : 16; +#else + uint32_t remaining_rx_time : 16, + reserved_0a : 12, + pkt_type : 4; +#endif +}; + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x00000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x0000000f + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x00000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x0000fff0 + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x00000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/rx_timing_info.h b/hw/peach/v2/rx_timing_info.h new file mode 100644 index 000000000000..5023cc43e3b7 --- /dev/null +++ b/hw/peach/v2/rx_timing_info.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_TIMING_INFO_H_ +#define _RX_TIMING_INFO_H_ + +#define NUM_OF_DWORDS_RX_TIMING_INFO 5 + +struct rx_timing_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + uint32_t residual_phase_offset : 12, + reserved : 20; +#else + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + uint32_t reserved : 20, + residual_phase_offset : 12; +#endif +}; + +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 +#define RX_TIMING_INFO_RESERVED_LSB 12 +#define RX_TIMING_INFO_RESERVED_MSB 31 +#define RX_TIMING_INFO_RESERVED_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/rx_trig_info.h b/hw/peach/v2/rx_trig_info.h new file mode 100644 index 000000000000..e0cf6a676556 --- /dev/null +++ b/hw/peach/v2/rx_trig_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, + trigger_resp_type : 3, + reserved_0 : 27; + uint32_t ppdu_duration : 16, + unique_destination_id : 16; +#else + uint32_t reserved_0 : 27, + trigger_resp_type : 3, + rx_trigger_frame_type : 2; + uint32_t unique_destination_id : 16, + ppdu_duration : 16; +#endif +}; + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x00000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x00000003 + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x00000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x0000001c + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0xffffffe0 + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x00000004 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 0 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 15 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x00000004 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 16 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 31 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/rxpcu_early_rx_indication.h b/hw/peach/v2/rxpcu_early_rx_indication.h new file mode 100644 index 000000000000..97f712b5f51d --- /dev/null +++ b/hw/peach/v2/rxpcu_early_rx_indication.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 1 + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + dot11ax_received_ext_ru_size : 4, + reserved_0a : 19; +#else + uint32_t reserved_0a : 19, + dot11ax_received_ext_ru_size : 4, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4; +#endif +}; + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x0000000f + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x00000010 + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x000001e0 + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00001e00 + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0xffffe000 + +#endif diff --git a/hw/peach/v2/rxpcu_ppdu_end_info.h b/hw/peach/v2/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..d167d56b3a2f --- /dev/null +++ b/hw/peach/v2/rxpcu_ppdu_end_info.h @@ -0,0 +1,861 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" +#include "rxpcu_ppdu_end_layout_info.h" +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 31 + +struct rxpcu_ppdu_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + __reserved_g_0012 : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + coex_uwb_tx_after_start_of_rx : 1, + coex_uwb_tx_from_start_of_rx : 1; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details : 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details : 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t non_qos_sn_info_valid : 1, + rts_or_trig_protected_ppdu : 1, + rts_or_trig_prot_type : 2, + reserved_13a : 2, + non_qos_sn_highest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_lowest_retry_setting : 1; + uint32_t qos_sn_1_info_valid : 1, + reserved_14a : 1, + qos_sn_1_tid : 4, + qos_sn_1_highest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_lowest_retry_setting : 1; + uint32_t qos_sn_2_info_valid : 1, + reserved_15a : 1, + qos_sn_2_tid : 4, + qos_sn_2_highest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_lowest_retry_setting : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t corrupted_due_to_fifo_delay : 1, + qos_sn_1_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_2_frag_num_state : 4, + rts_or_trig_prot_non_11a : 1, + rts_or_trig_prot_rate_mcs : 4, + rts_or_trig_prot_peer_addr_15_0 : 16; + uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; + uint32_t rts_or_trig_rx_count : 32; + uint32_t cts_or_null_tx_count : 32; + uint32_t rx_ppdu_end_marker : 32; +#else + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t reserved : 2, + macrx_abort_request_info_valid : 1, + phyrx_abort_request_info_valid : 1, + previous_tlv_corrupted : 1, + otp_txbf_disable : 1, + unsupported_mu_nc : 1, + tx_ht_vht_ack : 1, + rx_antenna : 24; + uint32_t coex_uwb_tx_from_start_of_rx : 1, + coex_uwb_tx_after_start_of_rx : 1, + bb_captured_timeout : 1, + bb_captured_reason : 3, + bb_captured_channel : 1, + follow_up_dialog_token : 8, + dialog_token : 8, + __reserved_g_0012 : 2, + mpdu_delimiter_errors_seen : 1, + coex_wlan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_bt_tx_from_start_of_rx : 1; + uint32_t reserved_4 : 2, + after_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + before_mpdu_count_passing_fcs : 10; + uint32_t reserved_5 : 22, + after_mpdu_count_failing_fcs : 10; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t first_bt_broadcast_status_details : 12, + reserved_8 : 3, + bb_data : 1, + bb_length : 16; + uint32_t reserved_9 : 8, + rx_ppdu_duration : 24; + uint32_t second_bt_broadcast_status_details : 12, + reserved_10 : 3, + ast_index_valid : 1, + ast_index : 16; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + uint32_t reserved_12a : 4, + pre_bt_broadcast_status_details : 12; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint32_t non_qos_sn_lowest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_highest : 12, + reserved_13a : 2, + rts_or_trig_prot_type : 2, + rts_or_trig_protected_ppdu : 1, + non_qos_sn_info_valid : 1; + uint32_t qos_sn_1_lowest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_highest : 12, + qos_sn_1_tid : 4, + reserved_14a : 1, + qos_sn_1_info_valid : 1; + uint32_t qos_sn_2_lowest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_highest : 12, + qos_sn_2_tid : 4, + reserved_15a : 1, + qos_sn_2_info_valid : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, + rts_or_trig_prot_rate_mcs : 4, + rts_or_trig_prot_non_11a : 1, + qos_sn_2_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_1_more_frag_state : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; + uint32_t rts_or_trig_rx_count : 32; + uint32_t cts_or_null_tx_count : 32; + uint32_t rx_ppdu_end_marker : 32; +#endif +}; + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x04000000 + +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 0 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 0 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 1 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 2 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 3 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 4 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 5 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 + +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 6 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 9 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 16 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe00 + +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 17 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 24 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 25 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 25 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 26 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 28 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 29 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 29 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_LSB 30 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MSB 30 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MASK 0x40000000 + +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_LSB 31 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MSB 31 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 + +#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 10 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc00 + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 24 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 8 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 9 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 10 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 10 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 11 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 11 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x00000800 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 12 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 12 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x00001000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 13 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 13 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x00002000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 14 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 14 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x00004000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 15 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x00008000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 31 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0fff0000 + +#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 1 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 1 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 2 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 3 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c + +#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 4 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 5 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x00000030 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x00000003 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x000000fc + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x00003f00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x000fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x03f00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0xe0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x00000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x00000064 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x00000780 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x00000800 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x0000f000 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000006c +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 0 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x00000070 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x00000074 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 0 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 31 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x00000078 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 31 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rxpcu_ppdu_end_layout_info.h b/hw/peach/v2/rxpcu_ppdu_end_layout_info.h new file mode 100644 index 000000000000..64f78df7c011 --- /dev/null +++ b/hw/peach/v2/rxpcu_ppdu_end_layout_info.h @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 + +struct rxpcu_ppdu_end_layout_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_legacy_offset : 2, + l_sig_a_offset : 6, + l_sig_b_offset : 6, + ht_sig_offset : 6, + vht_sig_a_offset : 6, + repeat_l_sig_a_offset : 6; + uint32_t he_sig_a_su_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_mu_ul_offset : 6, + generic_u_sig_offset : 6, + rssi_ht_offset : 7, + reserved_1a : 1; + uint32_t vht_sig_b_su20_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su160_offset : 7, + reserved_2a : 4; + uint32_t vht_sig_b_mu20_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu160_offset : 7, + reserved_3a : 4; + uint32_t he_sig_b1_mu_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b2_ofdma_offset : 7, + first_generic_eht_sig_offset : 7, + multiple_generic_eht_sig_included : 1, + reserved_4a : 3; + uint32_t common_user_info_offset : 7, + first_debug_info_offset : 8, + multiple_debug_info_included : 1, + first_other_receive_info_offset : 8, + multiple_other_receive_info_included : 1, + reserved_5a : 7; + uint32_t data_done_offset : 8, + generated_cbf_details_offset : 8, + pkt_end_part1_offset : 8, + location_offset : 8; + uint32_t __reserved_g_0011 : 8, + pkt_end_offset : 8, + abort_request_ack_offset : 8, + reserved_7a : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#else + uint32_t repeat_l_sig_a_offset : 6, + vht_sig_a_offset : 6, + ht_sig_offset : 6, + l_sig_b_offset : 6, + l_sig_a_offset : 6, + rssi_legacy_offset : 2; + uint32_t reserved_1a : 1, + rssi_ht_offset : 7, + generic_u_sig_offset : 6, + he_sig_a_mu_ul_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_su_offset : 6; + uint32_t reserved_2a : 4, + vht_sig_b_su160_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su20_offset : 7; + uint32_t reserved_3a : 4, + vht_sig_b_mu160_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu20_offset : 7; + uint32_t reserved_4a : 3, + multiple_generic_eht_sig_included : 1, + first_generic_eht_sig_offset : 7, + he_sig_b2_ofdma_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b1_mu_offset : 7; + uint32_t reserved_5a : 7, + multiple_other_receive_info_included : 1, + first_other_receive_info_offset : 8, + multiple_debug_info_included : 1, + first_debug_info_offset : 8, + common_user_info_offset : 7; + uint32_t location_offset : 8, + pkt_end_part1_offset : 8, + generated_cbf_details_offset : 8, + data_done_offset : 8; + uint32_t reserved_7a : 8, + abort_request_ack_offset : 8, + pkt_end_offset : 8, + __reserved_g_0011 : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#endif +}; + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/rxpt_classify_info.h b/hw/peach/v2/rxpt_classify_info.h new file mode 100644 index 000000000000..9a6631c3ea68 --- /dev/null +++ b/hw/peach/v2/rxpt_classify_info.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 3, + rxdma0_destination_ring_selection : 3, + mcast_echo_drop_enable : 1, + wds_learning_detect_en : 1, + intrabss_check_en : 1, + use_ppe : 1, + ppe_routing_enable : 1, + cce_source_sel_en : 1, + reserved_0b : 9; +#else + uint32_t reserved_0b : 9, + cce_source_sel_en : 1, + ppe_routing_enable : 1, + use_ppe : 1, + intrabss_check_en : 1, + wds_learning_detect_en : 1, + mcast_echo_drop_enable : 1, + rxdma0_destination_ring_selection : 3, + rxdma0_source_ring_selection : 3, + pkt_selection_fp_1000 : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_ucast_data : 1, + use_flow_id_toeplitz_clfy : 1, + lmac_peer_id_msb : 2, + reo_destination_indication : 5; +#endif +}; + +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 + +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 + +#endif diff --git a/hw/peach/v2/seq_hwio.h b/hw/peach/v2/seq_hwio.h new file mode 100644 index 000000000000..f9adaf4f3a5a --- /dev/null +++ b/hw/peach/v2/seq_hwio.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif + diff --git a/hw/peach/v2/soc_ce_seq_hwioreg.h b/hw/peach/v2/soc_ce_seq_hwioreg.h new file mode 100644 index 000000000000..53963ad78e24 --- /dev/null +++ b/hw/peach/v2/soc_ce_seq_hwioreg.h @@ -0,0 +1,13194 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __SOC_CE_SEQ_HWIOREG_H__ +#define __SOC_CE_SEQ_HWIOREG_H__ + +#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) +#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00000000) +#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00000000 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) +#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00001000) +#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS 0x00001000 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) +#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00002000) +#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00002000 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) +#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00003000) +#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS 0x00003000 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00004000) +#define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00004000) +#define SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00004000 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_2_SRC_WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00005000) +#define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00005000) +#define SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS 0x00005000 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_2_DST_WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_2_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00006000) +#define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00006000) +#define SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00006000 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_3_SRC_WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00007000) +#define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00007000) +#define SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS 0x00007000 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_3_DST_WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_3_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00008000) +#define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00008000) +#define SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00008000 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_4_SRC_WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00009000) +#define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00009000) +#define SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS 0x00009000 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_4_DST_WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_4_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000a000) +#define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000a000) +#define SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000a000 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_5_SRC_WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000b000) +#define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000b000) +#define SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000b000 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_5_DST_WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_5_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000c000) +#define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000c000) +#define SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000c000 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_6_SRC_WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000d000) +#define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000d000) +#define SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000d000 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_6_DST_WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_6_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000e000) +#define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000e000) +#define SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000e000 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_7_SRC_WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000f000) +#define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000f000) +#define SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000f000 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_7_DST_WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_7_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00010000) +#define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00010000) +#define SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00010000 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_8_SRC_WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00011000) +#define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00011000) +#define SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS 0x00011000 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_8_DST_WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_8_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00012000) +#define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00012000) +#define SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00012000 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_9_SRC_WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00013000) +#define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00013000) +#define SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS 0x00013000 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_9_DST_WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_9_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00014000) +#define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00014000) +#define SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00014000 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_10_SRC_WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00015000) +#define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00015000) +#define SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS 0x00015000 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_10_DST_WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_10_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00016000) +#define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00016000) +#define SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00016000 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (SOC_CE_11_SRC_WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00017000) +#define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00017000) +#define SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS 0x00017000 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (SOC_CE_11_DST_WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_11_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +#define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00018000) +#define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00018000) +#define SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS 0x00018000 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000000) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000000) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000004) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000004) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0xff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0xff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000008) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000008) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000008) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000000c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000010) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000010) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000010) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x800 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000014) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000014) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000014) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x1010101 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x1000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x100 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000018) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000018) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000018) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x3f3f3f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x3f0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x3f00 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x3f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000001c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000001c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000001c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000020) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000020) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000020) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000024) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000024) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000024) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0xfffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x8000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x4000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x2000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x1000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x800000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x700000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0xe0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1fe00 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1fe +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000028) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000028) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000028) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000002c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0xffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0xffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000030) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000030) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000030) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000034) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000034) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000034) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000038) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000038) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000038) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000003c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000040) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000040) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000040) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000044) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000044) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000044) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000048) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000048) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000048) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000004c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x1ffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x1000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0xfff000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000050) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000050) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000050) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000054) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000054) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000054) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0xffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0xfff000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000058) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000058) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000058) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x1ffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x1000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0xfff000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000005c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000060) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000060) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000060) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000064) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000064) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000064) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000068) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000068) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000068) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000006c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000070) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000070) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000070) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000074) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000074) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000074) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000078) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000078) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000078) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000007c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000007c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000007c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000080) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000080) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000080) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000084) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000084) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000084) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000088) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000088) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000088) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK 0xfffdffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT 0x1f +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK 0x40000000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT 0x1e +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK 0x3ffc0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT 0x12 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK 0xf000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT 0xc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000008c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000008c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000008c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK 0xffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK 0xfff000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT 0xc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000090) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000090) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000090) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK 0x1fff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK 0x1000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT 0xc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000094) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000094) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000094) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000098) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000098) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000098) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000009c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000009c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000009c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000a0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK 0xf00ff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_BMSK 0xf0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc0 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_SHFT 0x6 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_BMSK 0x30 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_SHFT 0x4 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_SHFT 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_BMSK 0x3 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000a4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK 0x10fff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000a8) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK 0x10fff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_BMSK 0xfff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000ac) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK 0x300ff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_WR_DATA_FIFO_RD_DATA_SEL_BMSK 0x20000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_WR_DATA_FIFO_RD_DATA_SEL_SHFT 0x11 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_BMSK 0xe0 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_SHFT 0x5 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_BMSK 0x1c +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_SHFT 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_BMSK 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_SHFT 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000b0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000b4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000b8) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000bc) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000bc) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000bc) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000c0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000c0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000c0) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x000000c4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x000000c4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x000000c4) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK 0x3 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_BMSK 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_SHFT 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000400) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000400) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x100ff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x10 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0xff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000404) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000404) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000404) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000408) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000408) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000040c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x0000040c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x0000040c) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000410) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000410) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000410) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0xff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0xff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000414) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000414) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000414) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000418) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_PHYS + 0x00000418) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OFFS (SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_OFFS + 0x00000418) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(m) \ + in_dword_masked(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, m) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(v) \ + out_dword(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,v) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,m,v,HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN) +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +#endif diff --git a/hw/peach/v2/tcl_data_cmd.h b/hw/peach/v2/tcl_data_cmd.h new file mode 100644 index 000000000000..b1c617a24982 --- /dev/null +++ b/hw/peach/v2/tcl_data_cmd.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_TCL_DATA_CMD 8 + +struct tcl_data_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; + uint32_t tcl_cmd_type : 1, + buf_or_ext_desc_type : 1, + bank_id : 6, + tx_notify_frame : 3, + header_length_read_sel : 1, + buffer_timestamp : 19, + buffer_timestamp_valid : 1; + uint32_t reserved_3a : 16, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_4a : 1, + packet_offset : 9; + uint32_t hlos_tid_overwrite : 1, + flow_override_enable : 1, + who_classify_info_sel : 2, + hlos_tid : 4, + flow_override : 1, + pmac_id : 2, + msdu_color : 2, + reserved_5a : 11, + vdev_id : 8; + uint32_t search_index : 20, + cache_set_num : 4, + index_lookup_override : 1, + reserved_6a : 7; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_addr_info; + uint32_t buffer_timestamp_valid : 1, + buffer_timestamp : 19, + header_length_read_sel : 1, + tx_notify_frame : 3, + bank_id : 6, + buf_or_ext_desc_type : 1, + tcl_cmd_type : 1; + uint32_t tcl_cmd_number : 16, + reserved_3a : 16; + uint32_t packet_offset : 9, + reserved_4a : 1, + to_fw : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + data_length : 16; + uint32_t vdev_id : 8, + reserved_5a : 11, + msdu_color : 2, + pmac_id : 2, + flow_override : 1, + hlos_tid : 4, + who_classify_info_sel : 2, + flow_override_enable : 1, + hlos_tid_overwrite : 1; + uint32_t reserved_6a : 7, + index_lookup_override : 1, + cache_set_num : 4, + search_index : 20; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 + +#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BANK_ID_LSB 2 +#define TCL_DATA_CMD_BANK_ID_MSB 7 +#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc + +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 + +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 + +#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_RESERVED_3A_LSB 0 +#define TCL_DATA_CMD_RESERVED_3A_MSB 15 +#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff + +#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c +#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 + +#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 +#define TCL_DATA_CMD_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_DATA_LENGTH_MSB 15 +#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff + +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 + +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 +#define TCL_DATA_CMD_TO_FW_LSB 21 +#define TCL_DATA_CMD_TO_FW_MSB 21 +#define TCL_DATA_CMD_TO_FW_MASK 0x00200000 + +#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_RESERVED_4A_LSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 + +#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 +#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 +#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 + +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 + +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c + +#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_LSB 4 +#define TCL_DATA_CMD_HLOS_TID_MSB 7 +#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 + +#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_PMAC_ID_LSB 9 +#define TCL_DATA_CMD_PMAC_ID_MSB 10 +#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 + +#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 +#define TCL_DATA_CMD_MSDU_COLOR_LSB 11 +#define TCL_DATA_CMD_MSDU_COLOR_MSB 12 +#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 + +#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_DATA_CMD_RESERVED_5A_LSB 13 +#define TCL_DATA_CMD_RESERVED_5A_MSB 23 +#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 + +#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_VDEV_ID_LSB 24 +#define TCL_DATA_CMD_VDEV_ID_MSB 31 +#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 + +#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 +#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 +#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 +#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff + +#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 +#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 +#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 +#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 + +#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_RESERVED_6A_LSB 25 +#define TCL_DATA_CMD_RESERVED_6A_MSB 31 +#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 + +#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_DATA_CMD_RESERVED_7A_LSB 0 +#define TCL_DATA_CMD_RESERVED_7A_MSB 19 +#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_DATA_CMD_RING_ID_LSB 20 +#define TCL_DATA_CMD_RING_ID_MSB 27 +#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 +#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/tcl_gse_cmd.h b/hw/peach/v2/tcl_gse_cmd.h new file mode 100644 index 000000000000..36161258fceb --- /dev/null +++ b/hw/peach/v2/tcl_gse_cmd.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ + +#define NUM_OF_DWORDS_TCL_GSE_CMD 8 + +struct tcl_gse_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t tcl_cmd_type : 1, + reserved_2a : 31; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t control_buffer_addr_31_0 : 32; + uint32_t reserved_1a : 12, + cache_set_num : 4, + index_search_en : 1, + swap : 1, + status_destination_ring_id : 1, + gse_sel : 1, + gse_ctrl : 4, + control_buffer_addr_39_32 : 8; + uint32_t reserved_2a : 31, + tcl_cmd_type : 1; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_GSE_CTRL_MSB 11 +#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 + +#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_GSE_SEL_MSB 12 +#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 + +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_SWAP_LSB 14 +#define TCL_GSE_CMD_SWAP_MSB 14 +#define TCL_GSE_CMD_SWAP_MASK 0x00004000 + +#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 + +#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 +#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 + +#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_RESERVED_1A_MSB 31 +#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 + +#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 +#define TCL_GSE_CMD_RESERVED_2A_LSB 1 +#define TCL_GSE_CMD_RESERVED_2A_MSB 31 +#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe + +#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_RESERVED_5A_MSB 31 +#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_RESERVED_6A_MSB 31 +#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_GSE_CMD_RESERVED_7A_LSB 0 +#define TCL_GSE_CMD_RESERVED_7A_MSB 19 +#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_GSE_CMD_RING_ID_LSB 20 +#define TCL_GSE_CMD_RING_ID_MSB 27 +#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 +#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/tcl_status_ring.h b/hw/peach/v2/tcl_status_ring.h new file mode 100644 index 000000000000..9b6ed3ebb947 --- /dev/null +++ b/hw/peach/v2/tcl_status_ring.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t msdu_cnt_n : 24, + index_search_en : 1, + cache_op_res : 2, + ase_fse_sel : 1, + gse_ctrl : 4; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 8, + cache_set_num : 4, + hash_indx_val : 20; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_GSE_CTRL_MSB 3 +#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f + +#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 + +#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 +#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 + +#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 + +#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 + +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff + +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 +#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff + +#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 +#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_RESERVED_5A_MSB 31 +#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 + +#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_RESERVED_6A_MSB 31 +#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff + +#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_RESERVED_7A_MSB 19 +#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff + +#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_RING_ID_LSB 20 +#define TCL_STATUS_RING_RING_ID_MSB 27 +#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 + +#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 +#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/tlv_hdr.h b/hw/peach/v2/tlv_hdr.h new file mode 100644 index 000000000000..493dc15da872 --- /dev/null +++ b/hw/peach/v2/tlv_hdr.h @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ + +#define _TLV_USERID_WIDTH_ 6 +#define _TLV_DATA_WIDTH_ 32 +#define _TLV_TAG_WIDTH_ 9 + +#define _TLV_MRV_EN_LEN_WIDTH_ 9 +#define _TLV_MRV_DIS_LEN_WIDTH_ 12 + +#define _TLV_16_DATA_WIDTH_ 16 +#define _TLV_16_TAG_WIDTH_ 5 +#define _TLV_16_LEN_WIDTH_ 4 +#define _TLV_CTAG_WIDTH_ 5 +#define _TLV_44_DATA_WIDTH_ 44 +#define _TLV_64_DATA_WIDTH_ 64 +#define _TLV_76_DATA_WIDTH_ 64 +#define _TLV_CDATA_WIDTH_ 32 +#define _TLV_CDATA_76_WIDTH_ 64 + +struct tlv_usr_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint16_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_reserved : 6; +#else + uint16_t tlv_reserved : 6, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mac_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mac_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mac_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_usr_c_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata : _TLV_CDATA_WIDTH_, + pad_44to64_bit : 20; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_52 : 52; + uint64_t tlv_cdata_upper_12 : 12, + pad_76to128_bit : 52; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + tlv_cdata_middle_32 : 32; + uint64_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12, + pad_96to128_bit : 32; +#endif +}; + +struct tlv_usr_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mlo_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_usr_c_44_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_upper_12 : 12, + pad_44to64_bit : 20; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t tlv_cdata_upper_12 : 12, + pad_76to96_bit : 20; + uint32_t pad_96to128_bit : 32; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12; + uint32_t pad_96to128_bit : 32; +#endif +}; + +#endif diff --git a/hw/peach/v2/tlv_tag_def.h b/hw/peach/v2/tlv_tag_def.h new file mode 100644 index 000000000000..52400a852b97 --- /dev/null +++ b/hw/peach/v2/tlv_tag_def.h @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum tlv_tag_def { + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIPHYRX_LMR_DATA_RESP_E = 8 , + WIFIRXPCU_TO_UCODE_START_E = 9 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , + WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , + WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , + WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , + WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , + WIFIRXPCU_TO_UCODE_END_E = 16 , + WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 28 , + WIFIPHYRX_NC_ABORT_REQUEST_E = 29 , + WIFIPHYRX_PKT_END_20MHZ_E = 30 , + WIFIPHYRX_NC_DATA_E = 31 , + WIFIMACRX_CBF_READ_REQUEST_E = 32 , + WIFIMACRX_CBF_DATA_REQUEST_E = 33 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 , + WIFIMACRX_NDP_TIMEOUT_E = 36 , + WIFIMACRX_ABORT_ACK_E = 37 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 38 , + WIFIMACRX_CHAIN_MASK_E = 39 , + WIFIMACRX_NAP_USER_E = 40 , + WIFIMACRX_ABORT_REQUEST_E = 41 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 , + WIFIPHYTX_ABORT_ACK_E = 43 , + WIFIPHYTX_ABORT_REQUEST_E = 44 , + WIFIPHYTX_PKT_END_E = 45 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 , + WIFIPHYTX_DATA_REQUEST_E = 48 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 , + WIFIPHYTX_NAP_ACK_E = 50 , + WIFIPHYTX_NAP_DONE_E = 51 , + WIFIPHYTX_OFF_ACK_E = 52 , + WIFIPHYTX_ON_ACK_E = 53 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 54 , + WIFIPHYTX_DEBUG16_E = 55 , + WIFIMACTX_ABORT_REQUEST_E = 56 , + WIFIMACTX_ABORT_ACK_E = 57 , + WIFIMACTX_PKT_END_E = 58 , + WIFIMACTX_PRE_PHY_DESC_E = 59 , + WIFIMACTX_BF_PARAMS_COMMON_E = 60 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 61 , + WIFIMACTX_PREFETCH_CV_E = 62 , + WIFIMACTX_USER_DESC_COMMON_E = 63 , + WIFIMACTX_USER_DESC_PER_USER_E = 64 , + WIFIEXAMPLE_USER_TLV_16_E = 65 , + WIFIEXAMPLE_TLV_16_E = 66 , + WIFIMACTX_PHY_OFF_E = 67 , + WIFIMACTX_PHY_ON_E = 68 , + WIFIMACTX_SYNTH_OFF_E = 69 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 70 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 , + WIFIMACTX_PHY_DESC_E = 72 , + WIFIMACTX_L_SIG_A_E = 73 , + WIFIMACTX_L_SIG_B_E = 74 , + WIFIMACTX_HT_SIG_E = 75 , + WIFIMACTX_VHT_SIG_A_E = 76 , + WIFIMACTX_VHT_SIG_B_SU20_E = 77 , + WIFIMACTX_VHT_SIG_B_SU40_E = 78 , + WIFIMACTX_VHT_SIG_B_SU80_E = 79 , + WIFIMACTX_VHT_SIG_B_SU160_E = 80 , + WIFIMACTX_VHT_SIG_B_MU20_E = 81 , + WIFIMACTX_VHT_SIG_B_MU40_E = 82 , + WIFIMACTX_VHT_SIG_B_MU80_E = 83 , + WIFIMACTX_VHT_SIG_B_MU160_E = 84 , + WIFIMACTX_SERVICE_E = 85 , + WIFIMACTX_HE_SIG_A_SU_E = 86 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 87 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 88 , + WIFIMACTX_HE_SIG_B1_MU_E = 89 , + WIFIMACTX_HE_SIG_B2_MU_E = 90 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 , + WIFIMACTX_DELETE_CV_E = 92 , + WIFIMACTX_MU_UPLINK_COMMON_E = 93 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 , + WIFIMACTX_PHY_NAP_E = 96 , + WIFIMACTX_DEBUG_E = 97 , + WIFIPHYRX_ABORT_ACK_E = 98 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 , + WIFIPHYRX_RSSI_LEGACY_E = 100 , + WIFIPHYRX_RSSI_HT_E = 101 , + WIFIPHYRX_USER_INFO_E = 102 , + WIFIPHYRX_PKT_END_E = 103 , + WIFIPHYRX_DEBUG_E = 104 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 , + WIFIPHYRX_L_SIG_A_E = 107 , + WIFIPHYRX_L_SIG_B_E = 108 , + WIFIPHYRX_HT_SIG_E = 109 , + WIFIPHYRX_VHT_SIG_A_E = 110 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 111 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 112 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 113 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 114 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 115 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 116 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 117 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 118 , + WIFIPHYRX_HE_SIG_A_SU_E = 119 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 , + WIFIPHYRX_HE_SIG_B1_MU_E = 122 , + WIFIPHYRX_HE_SIG_B2_MU_E = 123 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 , + WIFIPHYRX_COMMON_USER_INFO_E = 126 , + WIFIPHYRX_DATA_DONE_E = 127 , + WIFICOEX_TX_REQ_E = 128 , + WIFIDUMMY_E = 129 , + WIFIEXAMPLE_TLV_32_NAME_E = 130 , + WIFIMPDU_LIMIT_E = 131 , + WIFINA_LENGTH_END_E = 132 , + WIFIOLE_BUF_STATUS_E = 133 , + WIFIPCU_PPDU_SETUP_DONE_E = 134 , + WIFIPCU_PPDU_SETUP_END_E = 135 , + WIFIPCU_PPDU_SETUP_INIT_E = 136 , + WIFIPCU_PPDU_SETUP_START_E = 137 , + WIFIPDG_FES_SETUP_E = 138 , + WIFIPDG_RESPONSE_E = 139 , + WIFIPDG_TX_REQ_E = 140 , + WIFISCH_WAIT_INSTR_E = 141 , + WIFIMACTX_SWITCH_TO_MAIN_E = 142 , + WIFIPHYTX_LINK_STATE_E = 143 , + WIFIAUX_PPDU_END_E = 144 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 , + WIFITQM_GEN_MPDUS_E = 147 , + WIFITQM_GEN_MPDUS_STATUS_E = 148 , + WIFITQM_REMOVE_MPDU_E = 149 , + WIFITQM_REMOVE_MPDU_STATUS_E = 150 , + WIFITQM_REMOVE_MSDU_E = 151 , + WIFITQM_REMOVE_MSDU_STATUS_E = 152 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 , + WIFITQM_WRITE_CMD_E = 154 , + WIFIOFDMA_TRIGGER_DETAILS_E = 155 , + WIFITX_DATA_E = 156 , + WIFITX_FES_SETUP_E = 157 , + WIFIRX_PACKET_E = 158 , + WIFIEXPECTED_RESPONSE_E = 159 , + WIFITX_MPDU_END_E = 160 , + WIFITX_MPDU_START_E = 161 , + WIFITX_MSDU_END_E = 162 , + WIFITX_MSDU_START_E = 163 , + WIFITX_SW_MODE_SETUP_E = 164 , + WIFITXPCU_BUFFER_STATUS_E = 165 , + WIFITXPCU_USER_BUFFER_STATUS_E = 166 , + WIFIDATA_TO_TIME_CONFIG_E = 167 , + WIFIEXAMPLE_USER_TLV_32_E = 168 , + WIFIMPDU_INFO_E = 169 , + WIFIPDG_USER_SETUP_E = 170 , + WIFITX_11AH_SETUP_E = 171 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 , + WIFITX_PEER_ENTRY_E = 173 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 , + WIFIEXAMPLE_USER_TLV_44_E = 175 , + WIFITX_FLUSH_E = 176 , + WIFITX_FLUSH_REQ_E = 177 , + WIFITQM_WRITE_CMD_STATUS_E = 178 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 180 , + WIFIEXAMPLE_USER_CTLV_44_E = 181 , + WIFITX_FES_STATUS_START_E = 182 , + WIFITX_FES_STATUS_USER_PPDU_E = 183 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 184 , + WIFITX_FES_STATUS_END_E = 185 , + WIFIRX_TRIG_INFO_E = 186 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 187 , + WIFIRX_FRAME_BITMAP_REQ_E = 188 , + WIFIRX_FRAME_BITMAP_ACK_E = 189 , + WIFICOEX_RX_STATUS_E = 190 , + WIFIRX_START_PARAM_E = 191 , + WIFIRX_PPDU_START_E = 192 , + WIFIRX_PPDU_END_E = 193 , + WIFIRX_MPDU_START_E = 194 , + WIFIRX_MPDU_END_E = 195 , + WIFIRX_MSDU_START_E = 196 , + WIFIRX_MSDU_END_E = 197 , + WIFIRX_ATTENTION_E = 198 , + WIFIRECEIVED_RESPONSE_INFO_E = 199 , + WIFIRX_PHY_SLEEP_E = 200 , + WIFIRX_HEADER_E = 201 , + WIFIRX_PEER_ENTRY_E = 202 , + WIFIRX_FLUSH_E = 203 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 , + WIFITX_CBF_INFO_E = 208 , + WIFIPCU_PPDU_SETUP_USER_E = 209 , + WIFIRX_MPDU_PCU_START_E = 210 , + WIFIRX_PM_INFO_E = 211 , + WIFIRX_USER_PPDU_END_E = 212 , + WIFIRX_PRE_PPDU_START_E = 213 , + WIFIRX_PREAMBLE_E = 214 , + WIFITX_FES_SETUP_COMPLETE_E = 215 , + WIFITX_LAST_MPDU_FETCHED_E = 216 , + WIFITXDMA_STOP_REQUEST_E = 217 , + WIFIRXPCU_SETUP_E = 218 , + WIFIRXPCU_USER_SETUP_E = 219 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 220 , + WIFITQM_ACKED_MPDU_E = 221 , + WIFICOEX_TX_RESP_E = 222 , + WIFICOEX_TX_STATUS_E = 223 , + WIFIMACTX_COEX_PHY_CTRL_E = 224 , + WIFICOEX_STATUS_BROADCAST_E = 225 , + WIFIRESPONSE_START_STATUS_E = 226 , + WIFIRESPONSE_END_STATUS_E = 227 , + WIFICRYPTO_STATUS_E = 228 , + WIFIRECEIVED_TRIGGER_INFO_E = 229 , + WIFICOEX_TX_STOP_CTRL_E = 230 , + WIFIRX_PPDU_ACK_REPORT_E = 231 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 232 , + WIFISCH_COEX_STATUS_E = 233 , + WIFISCHEDULER_COMMAND_STATUS_E = 234 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 , + WIFITX_FES_STATUS_PROT_E = 236 , + WIFITX_FES_STATUS_START_PPDU_E = 237 , + WIFITX_FES_STATUS_START_PROT_E = 238 , + WIFITXPCU_PHYTX_DEBUG32_E = 239 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 , + WIFIWHO_ANCHOR_OFFSET_E = 242 , + WIFIWHO_ANCHOR_VALUE_E = 243 , + WIFIWHO_CCE_INFO_E = 244 , + WIFIWHO_COMMIT_E = 245 , + WIFIWHO_COMMIT_DONE_E = 246 , + WIFIWHO_FLUSH_E = 247 , + WIFIWHO_L2_LLC_E = 248 , + WIFIWHO_L2_PAYLOAD_E = 249 , + WIFIWHO_L3_CHECKSUM_E = 250 , + WIFIWHO_L3_INFO_E = 251 , + WIFIWHO_L4_CHECKSUM_E = 252 , + WIFIWHO_L4_INFO_E = 253 , + WIFIWHO_MSDU_E = 254 , + WIFIWHO_MSDU_MISC_E = 255 , + WIFIWHO_PACKET_DATA_E = 256 , + WIFIWHO_PACKET_HDR_E = 257 , + WIFIWHO_PPDU_END_E = 258 , + WIFIWHO_PPDU_START_E = 259 , + WIFIWHO_TSO_E = 260 , + WIFIWHO_WMAC_HEADER_PV0_E = 261 , + WIFIWHO_WMAC_HEADER_PV1_E = 262 , + WIFIWHO_WMAC_IV_E = 263 , + WIFIMPDU_INFO_END_E = 264 , + WIFIMPDU_INFO_BITMAP_E = 265 , + WIFITX_QUEUE_EXTENSION_E = 266 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 , + WIFITQM_ACKED_MPDU_STATUS_E = 269 , + WIFITQM_ADD_MSDU_STATUS_E = 270 , + WIFITQM_LIST_GEN_DONE_E = 271 , + WIFIWHO_TERMINATE_E = 272 , + WIFITX_LAST_MPDU_END_E = 273 , + WIFITX_CV_DATA_E = 274 , + WIFIPPDU_TX_END_E = 275 , + WIFIPROT_TX_END_E = 276 , + WIFIMPDU_INFO_GLOBAL_END_E = 277 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 , + WIFIRX_PPDU_END_USER_STATS_E = 279 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 , + WIFIREO_GET_QUEUE_STATS_E = 281 , + WIFIREO_FLUSH_QUEUE_E = 282 , + WIFIREO_FLUSH_CACHE_E = 283 , + WIFIREO_UNBLOCK_CACHE_E = 284 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 286 , + WIFIREO_FLUSH_CACHE_STATUS_E = 287 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 , + WIFITQM_FLUSH_CACHE_E = 289 , + WIFITQM_UNBLOCK_CACHE_E = 290 , + WIFITQM_FLUSH_CACHE_STATUS_E = 291 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 , + WIFIRX_PPDU_END_STATUS_DONE_E = 293 , + WIFIRX_STATUS_BUFFER_DONE_E = 294 , + WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 295 , + WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 296 , + WIFITX_DATA_SYNC_E = 297 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 299 , + WIFITQM_SYNC_CMD_E = 300 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 , + WIFITQM_SYNC_CMD_STATUS_E = 302 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 , + WIFIRX_PPDU_START_USER_INFO_E = 310 , + WIFIRX_RING_MASK_E = 311 , + WIFICOEX_MAC_NAP_E = 312 , + WIFIRXPCU_PPDU_END_INFO_E = 313 , + WIFIWHO_MESH_CONTROL_E = 314 , + WIFIPDG_SW_MODE_BW_START_E = 315 , + WIFIPDG_SW_MODE_BW_END_E = 316 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 , + WIFISCHEDULER_END_E = 319 , + WIFIRX_PPDU_START_DROPPED_E = 320 , + WIFIRX_PPDU_END_DROPPED_E = 321 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 , + WIFIRX_MPDU_START_DROPPED_E = 323 , + WIFIRX_MSDU_START_DROPPED_E = 324 , + WIFIRX_MSDU_END_DROPPED_E = 325 , + WIFIRX_MPDU_END_DROPPED_E = 326 , + WIFIRX_ATTENTION_DROPPED_E = 327 , + WIFITXPCU_USER_SETUP_E = 328 , + WIFIRXPCU_USER_SETUP_EXT_E = 329 , + WIFICMD_PART_0_END_E = 330 , + WIFIMACTX_SYNTH_ON_E = 331 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 , + WIFITQM_MPDU_GLOBAL_START_E = 333 , + WIFIEXAMPLE_TLV_32_E = 334 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 , + WIFIPDG_TRIG_RESPONSE_E = 342 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 343 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 344 , + WIFISCH_TQM_CMD_WRAPPER_E = 345 , + WIFIMPDUS_AVAILABLE_E = 346 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 , + WIFIPHYRX_TX_START_TIMING_E = 348 , + WIFITXPCU_PREAMBLE_DONE_E = 349 , + WIFINDP_PREAMBLE_DONE_E = 350 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 , + WIFITX_PUNCTURE_SETUP_E = 354 , + WIFIR2R_STATUS_END_E = 355 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 356 , + WIFIEND_OF_FLUSH_MARKER_E = 357 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 , + WIFITX_LOOPBACK_SETUP_E = 365 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 367 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 , + WIFITX_WUR_DATA_E = 371 , + WIFIRX_PPDU_END_START_E = 372 , + WIFIRX_PPDU_END_MIDDLE_E = 373 , + WIFIRX_PPDU_END_LAST_E = 374 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 , + WIFISRP_INFO_E = 377 , + WIFIOBSS_SR_INFO_E = 378 , + WIFISCHEDULER_SW_MSG_STATUS_E = 379 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 , + WIFIRXPCU_SETUP_COMPLETE_E = 381 , + WIFIMACTX_MCC_SWITCH_E = 382 , + WIFIMACTX_MCC_SWITCH_BACK_E = 383 , + WIFIPHYTX_MCC_SWITCH_ACK_E = 384 , + WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 385 , + WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 386 , + WIFILMR_TX_END_E = 389 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 , + WIFISCH_TLV_WRAPPER_E = 394 , + WIFISCHEDULER_STATUS_WRAPPER_E = 395 , + WIFIMPDU_INFO_6X_E = 396 , + WIFIMACTX___RESERVED_G_0013 = 397 , + WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 , + WIFIMACTX_U_SIG_EHT_TB_E = 399 , + WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 400 , + WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 401 , + WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 402 , + WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 , + WIFIPHYRX_U_SIG_EHT_TB_E = 404 , + WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 405 , + WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 406 , + WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 407 , + WIFIMACRX_LMR_READ_REQUEST_E = 408 , + WIFIMACRX_LMR_DATA_REQUEST_E = 409 , + WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 , + WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 , + WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 , + WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 , + WIFIPHYRX_USER_INFO_MU_UL_E = 414 , + WIFIMPDU_QUEUE_OVERVIEW_E = 415 , + WIFISCHEDULER_NAV_INFO_E = 416 , + WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 417 , + WIFILMR_PEER_ENTRY_E = 418 , + WIFILMR_MPDU_START_E = 419 , + WIFILMR_DATA_E = 420 , + WIFILMR_MPDU_END_E = 421 , + WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 , + WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 , + WIFITX_FES_STATUS_1K_BA_E = 424 , + WIFITQM_ACKED_1K_MPDU_E = 425 , + WIFIMACRX_INBSS_OBSS_IND_E = 426 , + WIFIPHYRX_LOCATION_E = 427 , + WIFIMLO_TX_NOTIFICATION_SU_E = 428 , + WIFIMLO_TX_NOTIFICATION_MU_E = 429 , + WIFIMLO_TX_REQ_SU_E = 430 , + WIFIMLO_TX_REQ_MU_E = 431 , + WIFIMLO_TX_RESP_E = 432 , + WIFIMLO_RX_NOTIFICATION_E = 433 , + WIFIMLO_BKOFF_TRUNC_REQ_E = 434 , + WIFIMLO_TBTT_NOTIFICATION_E = 435 , + WIFIMLO_MESSAGE_E = 436 , + WIFIMLO_TS_SYNC_MSG_E = 437 , + WIFIMLO_FES_SETUP_E = 438 , + WIFIMLO_PDG_FES_SETUP_SU_E = 439 , + WIFIMLO_PDG_FES_SETUP_MU_E = 440 , + WIFIMPDU_INFO_1K_BITMAP_E = 441 , + WIFIMON_BUFFER_ADDR_E = 442 , + WIFITX_FRAG_STATE_E = 443 , + WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 444 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 445 , + WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 , + WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 , + WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 , + WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 , + WIFIPHYRX_PKT_END_PART1_E = 456 , + WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 , + WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 , + WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 , + WIFIPHYRX___RESERVED_G_0014 = 461 , + WIFIPHYTX_LOCATION_E = 462 , + WIFIPHYTX___RESERVED_G_0014 = 463 , + WIFIMACTX_EHT_SIG_USR_SU_E = 466 , + WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 , + WIFIPHYRX_EHT_SIG_USR_SU_E = 468 , + WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 , + WIFIPHYRX_GENERIC_U_SIG_E = 470 , + WIFIPHYRX_GENERIC_EHT_SIG_E = 471 , + WIFIOVERWRITE_RESP_START_E = 472 , + WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 , + WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 , + WIFIOVERWRITE_RESP_END_E = 475 , + WIFIRXPCU_EARLY_RX_INDICATION_E = 476 , + WIFIMON_DROP_E = 477 , + WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 , + WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 , + WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 , + WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 , + WIFIMACTX_PREFETCH_CV_DMA_E = 482 , + WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 , + WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 , + WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 , + WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 , + WIFIRANGING_USER_DETAILS_E = 487 , + WIFIPHYTX_CV_CORR_STATUS_E = 488 , + WIFIPHYTX_CV_CORR_COMMON_E = 489 , + WIFIPHYTX_CV_CORR_USER_E = 490 , + WIFIMACTX_CV_CORR_COMMON_E = 491 , + WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 , + WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 , + WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 , + WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 , + WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 , + WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 , + WIFIFW2SW_MON_E = 499 , + WIFIWSI_DIRECT_MESSAGE_E = 500 , + WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 , + WIFIMACTX_EMLSR_SWITCH_E = 502 , + WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 , + WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 , + WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 , + WIFISPARE_REUSE_TAG_0_E = 506 , + WIFISPARE_REUSE_TAG_1_E = 507 , + WIFISPARE_REUSE_TAG_2_E = 508 , + WIFISPARE_REUSE_TAG_3_E = 509 +} tlv_tag_def__e; + +#endif diff --git a/hw/peach/v2/tx_cbf_info.h b/hw/peach/v2/tx_cbf_info.h new file mode 100644 index 000000000000..c3d0d82237e3 --- /dev/null +++ b/hw/peach/v2/tx_cbf_info.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ + +#define NUM_OF_DWORDS_TX_CBF_INFO 15 + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, + pre_cbf_duration : 16; + uint32_t brpoll_info_valid : 1, + trigger_brpoll_info_valid : 1, + npda_info_11ac_valid : 1, + npda_info_11ax_valid : 1, + dot11ax_su_extended : 1, + bandwidth : 3, + brpoll_info : 8, + cbf_response_table_base_index : 8, + peer_index : 3, + pkt_type : 4, + txop_duration_all_ones : 1; + uint32_t trigger_brpoll_common_info_15_0 : 16, + trigger_brpoll_common_info_31_16 : 16; + uint32_t trigger_brpoll_user_info_15_0 : 16, + trigger_brpoll_user_info_31_16 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + sta_partial_aid : 11, + reserved_8a : 4, + cbf_resp_pwr_mgmt : 1; + uint32_t group_id : 6, + rssi_comb : 8, + reserved_9a : 2, + vht_ndpa_sta_info : 16; + uint32_t he_eht_sta_info_15_0 : 16, + he_eht_sta_info_31_16 : 16; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_dl_ul_flag : 1, + reserved_11a : 8; + uint32_t sw_response_frame_length : 16, + sw_response_tlv_from_crypto : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2, + __reserved_g_0005 : 1, + secure : 1, + tb___reserved_g_0005_response_required : 2, + emlsr_main_tlv_if : 1, + reserved_12a : 1, + u_sig_puncture_pattern_encoding : 6; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + npda_info_11be_valid : 1, + eht_duplicate_mode : 2, + reserved_13a : 11; + uint32_t eht_sta_info_39_32 : 8, + reserved_14a : 24; +#else + uint32_t pre_cbf_duration : 16, + sw_peer_id : 16; + uint32_t txop_duration_all_ones : 1, + pkt_type : 4, + peer_index : 3, + cbf_response_table_base_index : 8, + brpoll_info : 8, + bandwidth : 3, + dot11ax_su_extended : 1, + npda_info_11ax_valid : 1, + npda_info_11ac_valid : 1, + trigger_brpoll_info_valid : 1, + brpoll_info_valid : 1; + uint32_t trigger_brpoll_common_info_31_16 : 16, + trigger_brpoll_common_info_15_0 : 16; + uint32_t trigger_brpoll_user_info_31_16 : 16, + trigger_brpoll_user_info_15_0 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t cbf_resp_pwr_mgmt : 1, + reserved_8a : 4, + sta_partial_aid : 11, + addr3_47_32 : 16; + uint32_t vht_ndpa_sta_info : 16, + reserved_9a : 2, + rssi_comb : 8, + group_id : 6; + uint32_t he_eht_sta_info_31_16 : 16, + he_eht_sta_info_15_0 : 16; + uint32_t reserved_11a : 8, + dot11ax_dl_ul_flag : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_12a : 1, + emlsr_main_tlv_if : 1, + tb___reserved_g_0005_response_required : 2, + secure : 1, + __reserved_g_0005 : 1, + wait_sifs : 2, + wait_sifs_config_valid : 1, + sw_response_tlv_from_crypto : 1, + sw_response_frame_length : 16; + uint32_t reserved_13a : 11, + eht_duplicate_mode : 2, + npda_info_11be_valid : 1, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_14a : 24, + eht_sta_info_39_32 : 8; +#endif +}; + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x00000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x0000ffff + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x00000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0xffff0000 + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 0 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 0 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x00000001 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 1 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 1 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x00000002 + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 2 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 2 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x00000004 + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 3 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 3 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x00000008 + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 4 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 4 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x00000010 + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x00000004 +#define TX_CBF_INFO_BANDWIDTH_LSB 5 +#define TX_CBF_INFO_BANDWIDTH_MSB 7 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e0 + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x00000004 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 8 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 15 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff00 + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x00000004 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 16 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 23 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff0000 + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x00000004 +#define TX_CBF_INFO_PEER_INDEX_LSB 24 +#define TX_CBF_INFO_PEER_INDEX_MSB 26 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x07000000 + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x00000004 +#define TX_CBF_INFO_PKT_TYPE_LSB 27 +#define TX_CBF_INFO_PKT_TYPE_MSB 30 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x78000000 + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000004 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 31 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 31 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x00000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x00000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000c +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000c +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x00000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x00000014 +#define TX_CBF_INFO_ADDR1_47_32_LSB 0 +#define TX_CBF_INFO_ADDR1_47_32_MSB 15 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x00000014 +#define TX_CBF_INFO_ADDR2_15_0_LSB 16 +#define TX_CBF_INFO_ADDR2_15_0_MSB 31 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff0000 + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x00000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000001c +#define TX_CBF_INFO_ADDR3_31_0_LSB 0 +#define TX_CBF_INFO_ADDR3_31_0_MSB 31 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x00000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x0000ffff + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x00000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x07ff0000 + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x00000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x78000000 + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x00000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x80000000 + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x00000024 +#define TX_CBF_INFO_GROUP_ID_LSB 0 +#define TX_CBF_INFO_GROUP_ID_MSB 5 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x00000024 +#define TX_CBF_INFO_RSSI_COMB_LSB 6 +#define TX_CBF_INFO_RSSI_COMB_MSB 13 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc0 + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x00000024 +#define TX_CBF_INFO_RESERVED_9A_LSB 14 +#define TX_CBF_INFO_RESERVED_9A_MSB 15 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c000 + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x00000024 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 16 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 31 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff0000 + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x00000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x00000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 16 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 16 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 17 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 17 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000 + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 23 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 23 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x00800000 + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000002c +#define TX_CBF_INFO_RESERVED_11A_LSB 24 +#define TX_CBF_INFO_RESERVED_11A_MSB 31 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff000000 + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x00000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x00010000 + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x00020000 + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x00000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x000c0000 + +#define TX_CBF_INFO_SECURE_OFFSET 0x00000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x00200000 + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00c00000 + +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000030 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x01000000 + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x00000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 25 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x02000000 + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 16 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 16 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x00010000 + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 17 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 17 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x00020000 + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x00000034 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 18 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 18 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x00040000 + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 19 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 20 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x00180000 + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x00000034 +#define TX_CBF_INFO_RESERVED_13A_LSB 21 +#define TX_CBF_INFO_RESERVED_13A_MSB 31 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe00000 + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x00000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x000000ff + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x00000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0xffffff00 + +#endif diff --git a/hw/peach/v2/tx_fes_setup.h b/hw/peach/v2/tx_fes_setup.h new file mode 100644 index 000000000000..a09ec546aac5 --- /dev/null +++ b/hw/peach/v2/tx_fes_setup.h @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t fes_in_11ax_trigger_response_config : 1, + bo_based_tid_aggregation_limit : 4, + __reserved_g_0005 : 1, + expect_i2r_lmr : 1, + transmit_start_reason : 3, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + puncture_from_all_allowed_modes : 1, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + number_of_users : 6, + mu_type : 1, + ofdma_triggered_response : 1, + response_to_response_cmd : 1; + uint32_t schedule_try : 4, + ndp_frame : 2, + txbf : 1, + allow_txop_exceed_in_1st_pkt : 1, + ignore_bw_available : 1, + ignore_tbtt : 1, + static_bandwidth : 3, + set_txop_duration_all_ones : 1, + transmission_contains_mu_rts : 1, + bw_restricted_frames_embedded : 1, + ast_index : 16; + uint32_t cv_id : 8, + trigger_resp_txpdu_ppdu_boundary : 2, + rxpcu_setup_complete_present : 1, + rbo_must_have_data_user_limit : 4, + mu_ndp : 1, + bf_type : 2, + cbf_nc_index_mask : 1, + cbf_nc_index : 3, + cbf_nr_index_mask : 1, + cbf_nr_index : 3, + secure___reserved_g_0005_ista : 1, + ndpa : 1, + wait_sifs : 2, + cbf_feedback_type_mask : 1, + cbf_feedback_type : 1; + uint32_t cbf_sounding_token : 6, + cbf_sounding_token_mask : 1, + cbf_bw_mask : 1, + cbf_bw : 3, + use_static_bw : 1, + coex_nack_count : 5, + sch_tx_burst_ongoing : 1, + gen_tqm_update_mpdu_count_tlv : 1, + rts_tx_over___reserved_g_0016 : 1, + reserved_4a : 3, + optimal_bw_retry_count : 4, + fes_continuation_ratio_threshold : 5; + uint32_t transmit_cca_bitmap : 32; + uint32_t tb___reserved_g_0005 : 1, + __reserved_g_0005_trigger_subtype : 4, + min_cts2self_count : 4, + max_cts2self_count : 4, + wifi_radar_enable : 1, + reserved_6a : 1, + wait_for_chksum_done : 1, + reserved_6b : 15, + enable_hw_qos_null : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t monitor_override_sta_36_32 : 5, + enable_qos_null_switch_for_eosp : 1, + reserved_8a : 26; + uint32_t fw2sw_info : 32; +#else + uint32_t schedule_id : 32; + uint32_t response_to_response_cmd : 1, + ofdma_triggered_response : 1, + mu_type : 1, + number_of_users : 6, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + puncture_from_all_allowed_modes : 1, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + transmit_start_reason : 3, + expect_i2r_lmr : 1, + __reserved_g_0005 : 1, + bo_based_tid_aggregation_limit : 4, + fes_in_11ax_trigger_response_config : 1; + uint32_t ast_index : 16, + bw_restricted_frames_embedded : 1, + transmission_contains_mu_rts : 1, + set_txop_duration_all_ones : 1, + static_bandwidth : 3, + ignore_tbtt : 1, + ignore_bw_available : 1, + allow_txop_exceed_in_1st_pkt : 1, + txbf : 1, + ndp_frame : 2, + schedule_try : 4; + uint32_t cbf_feedback_type : 1, + cbf_feedback_type_mask : 1, + wait_sifs : 2, + ndpa : 1, + secure___reserved_g_0005_ista : 1, + cbf_nr_index : 3, + cbf_nr_index_mask : 1, + cbf_nc_index : 3, + cbf_nc_index_mask : 1, + bf_type : 2, + mu_ndp : 1, + rbo_must_have_data_user_limit : 4, + rxpcu_setup_complete_present : 1, + trigger_resp_txpdu_ppdu_boundary : 2, + cv_id : 8; + uint32_t fes_continuation_ratio_threshold : 5, + optimal_bw_retry_count : 4, + reserved_4a : 3, + rts_tx_over___reserved_g_0016 : 1, + gen_tqm_update_mpdu_count_tlv : 1, + sch_tx_burst_ongoing : 1, + coex_nack_count : 5, + use_static_bw : 1, + cbf_bw : 3, + cbf_bw_mask : 1, + cbf_sounding_token_mask : 1, + cbf_sounding_token : 6; + uint32_t transmit_cca_bitmap : 32; + uint32_t enable_hw_qos_null : 1, + reserved_6b : 15, + wait_for_chksum_done : 1, + reserved_6a : 1, + wifi_radar_enable : 1, + max_cts2self_count : 4, + min_cts2self_count : 4, + __reserved_g_0005_trigger_subtype : 4, + tb___reserved_g_0005 : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t reserved_8a : 26, + enable_qos_null_switch_for_eosp : 1, + monitor_override_sta_36_32 : 5; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x00000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0xffffffff + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 0 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 0 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x00000001 + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x00000004 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 1 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 4 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x00000004 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 6 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 6 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x00000040 + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x00000004 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 7 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 9 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x00000380 + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x00000004 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 10 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 10 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x00000400 + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 11 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 11 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x00000800 + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 12 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 12 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00001000 + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 13 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 13 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x00002000 + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 14 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 14 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x00004000 + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x00000004 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 15 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 15 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x00008000 + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 16 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 20 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x00000004 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 21 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 22 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x00600000 + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x00000004 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 23 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 28 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f800000 + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x00000004 +#define TX_FES_SETUP_MU_TYPE_LSB 29 +#define TX_FES_SETUP_MU_TYPE_MSB 29 +#define TX_FES_SETUP_MU_TYPE_MASK 0x20000000 + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x00000004 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 30 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 30 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x40000000 + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x00000004 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 31 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 31 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x80000000 + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x00000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x0000000f + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x00000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x00000030 + +#define TX_FES_SETUP_TXBF_OFFSET 0x00000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x00000040 + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x00000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x00000080 + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x00000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x00000100 + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x00000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x00000200 + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x00000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x00001c00 + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x00000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x00002000 + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x00000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x00004000 + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x00000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x00008000 + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x00000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0xffff0000 + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000c +#define TX_FES_SETUP_CV_ID_LSB 0 +#define TX_FES_SETUP_CV_ID_MSB 7 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000c +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 8 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 9 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x00000300 + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000c +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 10 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 10 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x00000400 + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000c +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 11 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 14 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x00007800 + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000c +#define TX_FES_SETUP_MU_NDP_LSB 15 +#define TX_FES_SETUP_MU_NDP_MSB 15 +#define TX_FES_SETUP_MU_NDP_MASK 0x00008000 + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000c +#define TX_FES_SETUP_BF_TYPE_LSB 16 +#define TX_FES_SETUP_BF_TYPE_MSB 17 +#define TX_FES_SETUP_BF_TYPE_MASK 0x00030000 + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 18 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 18 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x00040000 + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 19 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 21 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x00380000 + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 22 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 22 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x00400000 + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 23 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 25 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x03800000 + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000c +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 26 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 26 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x04000000 + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000c +#define TX_FES_SETUP_NDPA_LSB 27 +#define TX_FES_SETUP_NDPA_MSB 27 +#define TX_FES_SETUP_NDPA_MASK 0x08000000 + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000c +#define TX_FES_SETUP_WAIT_SIFS_LSB 28 +#define TX_FES_SETUP_WAIT_SIFS_MSB 29 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x30000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 30 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 30 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x40000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 31 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 31 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x80000000 + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x0000003f + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x00000040 + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x00000080 + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x00000700 + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x00000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x00000800 + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x00000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x0001f000 + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x00000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x00020000 + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x00000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x00040000 + +#define TX_FES_SETUP_RESERVED_4A_OFFSET 0x00000010 +#define TX_FES_SETUP_RESERVED_4A_LSB 20 +#define TX_FES_SETUP_RESERVED_4A_MSB 22 +#define TX_FES_SETUP_RESERVED_4A_MASK 0x00700000 + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x00000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x07800000 + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x00000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0xf8000000 + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x00000014 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 0 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 31 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x0000001e + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x00000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x000001e0 + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x00000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x00001e00 + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x00000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x00002000 + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x00000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 14 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00004000 + +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x00000018 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x00008000 + +#define TX_FES_SETUP_RESERVED_6B_OFFSET 0x00000018 +#define TX_FES_SETUP_RESERVED_6B_LSB 16 +#define TX_FES_SETUP_RESERVED_6B_MSB 30 +#define TX_FES_SETUP_RESERVED_6B_MASK 0x7fff0000 + +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x00000018 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x80000000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000001c +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 31 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x00000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x0000001f + +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x00000020 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x00000020 + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x00000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 6 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0xffffffc0 + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x00000024 +#define TX_FES_SETUP_FW2SW_INFO_LSB 0 +#define TX_FES_SETUP_FW2SW_INFO_MSB 31 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/tx_fes_status_1k_ba.h b/hw/peach/v2/tx_fes_status_1k_ba.h new file mode 100644 index 000000000000..6ef74208cb04 --- /dev/null +++ b/hw/peach/v2/tx_fes_status_1k_ba.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#endif +}; + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001 + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x00000002 + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x0000003c + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040 + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x00000080 + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x0000ff00 + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x0fff0000 + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0xf0000000 + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 0 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 15 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 16 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff0000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x00000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x00000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x00000014 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x00000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000001c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x00000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x00000024 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x00000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000002c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x00000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x00000034 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x00000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000003c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x00000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x00000044 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x00000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000004c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x00000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x00000054 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x00000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000005c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x00000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x00000064 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x00000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000006c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x00000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x00000074 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x00000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000007c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x00000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x00000084 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/tx_fes_status_ack_or_ba.h b/hw/peach/v2/tx_fes_status_ack_or_ba.h new file mode 100644 index 000000000000..ed81167d3020 --- /dev/null +++ b/hw/peach/v2/tx_fes_status_ack_or_ba.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#endif +}; + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x00000002 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x0000003c + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040 + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x00000080 + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x0000ff00 + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x0fff0000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0xf0000000 + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff0000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x00000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000c +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x00000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x00000014 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x00000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000001c +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x00000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x00000024 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/tx_fes_status_end.h b/hw/peach/v2/tx_fes_status_end.h new file mode 100644 index 000000000000..038436483a2d --- /dev/null +++ b/hw/peach/v2/tx_fes_status_end.h @@ -0,0 +1,649 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 11 + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_rx : 1, + global_data_underflow_warning : 1, + global_fes_transmit_result : 4, + cbf_bw_received_valid : 1, + cbf_bw_received : 3, + actual_received_ack_type : 4, + sta_response_count : 6, + more_data_received : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, + brp_info_valid : 1, + qos_null_switch_done_for_eosp : 1, + reserved_1a : 5, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + fes_in_11ax_trigger_response_config : 1, + null_delim_inserted_before_mpdus : 1, + only_null_delim_sent : 1; + uint32_t terminate___reserved_g_0005_sequence : 1, + reserved_2b : 5, + response_type : 5, + r2r_end_status_to_follow : 1, + reserved_5a : 3, + prot_coex_lte_tx_while_wlan_tx : 1, + prot_coex_lte_tx_while_wlan_rx : 1, + reserved_2c : 15; + uint32_t beamform_masked_user_bitmap_15_0 : 16, + beamform_masked_user_bitmap_31_16 : 16; + uint32_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8, + highest_achieved_data_null_ratio : 5, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + beamform_masked_user_bitmap_36_32 : 5, + pdg_mpdu_ready : 1; + uint32_t pdg_mpdu_count : 16, + pdg_est_mpdu_tx_count : 16; + uint32_t pdg_overview_length : 24, + txop_duration : 7, + pdg_dropped_mpdu_warning : 1; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + fec_type : 1, + stbc : 1, + num_data_symbols : 16, + ru_size : 4, + reserved_17a : 4; + uint32_t num_ltf_symbols : 3, + ltf_size : 2, + cp_setting : 2, + reserved_18a : 5, + dcm : 1, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_18b : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8; + uint32_t __reserved_g_0005_active_user_map : 16, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + coex_uwb_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_rx : 1, + prot_coex_uwb_tx_while_wlan_tx : 1, + prot_coex_uwb_tx_while_wlan_rx : 1, + coex_lte_tx_while_wlan_tx : 1, + coex_lte_tx_while_wlan_rx : 1, + cv_corr_status : 8; + uint32_t current_tx_duration : 16, + reserved_21a : 4, + hw_qos_null_bitmap : 8, + hw_qos_null_setup_missing : 1, + reserved_21b : 3; +#else + uint32_t more_data_received : 1, + sta_response_count : 6, + actual_received_ack_type : 4, + cbf_bw_received : 3, + cbf_bw_received_valid : 1, + global_fes_transmit_result : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_bt_tx_while_wlan_tx : 1; + uint32_t only_null_delim_sent : 1, + null_delim_inserted_before_mpdus : 1, + fes_in_11ax_trigger_response_config : 1, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + reserved_1a : 5, + qos_null_switch_done_for_eosp : 1, + brp_info_valid : 1, + reserved_after_struct16 : 4; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2c : 15, + prot_coex_lte_tx_while_wlan_rx : 1, + prot_coex_lte_tx_while_wlan_tx : 1, + reserved_5a : 3, + r2r_end_status_to_follow : 1, + response_type : 5, + reserved_2b : 5, + terminate___reserved_g_0005_sequence : 1; + uint32_t beamform_masked_user_bitmap_31_16 : 16, + beamform_masked_user_bitmap_15_0 : 16; + uint32_t pdg_mpdu_ready : 1, + beamform_masked_user_bitmap_36_32 : 5, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + highest_achieved_data_null_ratio : 5, + cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + uint32_t pdg_est_mpdu_tx_count : 16, + pdg_mpdu_count : 16; + uint32_t pdg_dropped_mpdu_warning : 1, + txop_duration : 7, + pdg_overview_length : 24; + uint32_t reserved_17a : 4, + ru_size : 4, + num_data_symbols : 16, + stbc : 1, + fec_type : 1, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t tx_pwr_unshared : 8, + tx_pwr_shared : 8, + reserved_18b : 1, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + dcm : 1, + reserved_18a : 5, + cp_setting : 2, + ltf_size : 2, + num_ltf_symbols : 3; + uint32_t cv_corr_status : 8, + coex_lte_tx_while_wlan_rx : 1, + coex_lte_tx_while_wlan_tx : 1, + prot_coex_uwb_tx_while_wlan_rx : 1, + prot_coex_uwb_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_rx : 1, + coex_uwb_tx_while_wlan_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_active_user_map : 16; + uint32_t reserved_21b : 3, + hw_qos_null_setup_missing : 1, + hw_qos_null_bitmap : 8, + reserved_21a : 4, + current_tx_duration : 16; +#endif +}; + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001 + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000002 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000004 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000008 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000010 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000020 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000040 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000080 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000100 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000200 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000400 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000800 + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00001000 + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x00000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x0001e000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x00020000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x00000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x001c0000 + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x01e00000 + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x7e000000 + +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x00000000 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x80000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 16 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 19 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f0000 + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 20 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 20 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x00100000 + +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x00000004 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 21 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 21 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x00200000 + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 22 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 26 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c00000 + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 27 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 27 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x08000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 29 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 29 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x20000000 + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x00000004 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 30 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 30 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x40000000 + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x00000004 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 31 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 31 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x80000000 + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x00000008 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x00000001 + +#define TX_FES_STATUS_END_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_2B_LSB 1 +#define TX_FES_STATUS_END_RESERVED_2B_MSB 5 +#define TX_FES_STATUS_END_RESERVED_2B_MASK 0x0000003e + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x000007c0 + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000008 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x00000800 + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 12 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 14 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x00007000 + +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_LSB 15 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MSB 15 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00008000 + +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000008 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_LSB 16 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MSB 16 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00010000 + +#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_2C_LSB 17 +#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_END_RESERVED_2C_MASK 0xfffe0000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000c +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000c +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff0000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000010 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000010 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff00 + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x00000010 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f0000 + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x00000010 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x00200000 + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x00400000 + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00800000 + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x01000000 + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x02000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000010 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c000000 + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x00000010 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x80000000 + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x00000014 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x00000014 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff0000 + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x00000018 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x00000018 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f000000 + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x00000018 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x80000000 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x00000038 + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000001c +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x00000040 + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000001c +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x00000080 + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000001c +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff00 + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000001c +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f000000 + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000001c +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf0000000 + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x00000020 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x00000007 + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x00000020 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x00000018 + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x00000020 +#define TX_FES_STATUS_END_CP_SETTING_LSB 5 +#define TX_FES_STATUS_END_CP_SETTING_MSB 6 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x00000060 + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x00000020 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f80 + +#define TX_FES_STATUS_END_DCM_OFFSET 0x00000020 +#define TX_FES_STATUS_END_DCM_LSB 12 +#define TX_FES_STATUS_END_DCM_MSB 12 +#define TX_FES_STATUS_END_DCM_MASK 0x00001000 + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x00000020 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x00002000 + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x00000020 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x00004000 + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x00000020 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x00008000 + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x00000020 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff0000 + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x00000020 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff000000 + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x0000ffff + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x00010000 + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x00020000 + +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_LSB 18 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MSB 18 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_LSB 19 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MSB 19 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_LSB 20 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MSB 20 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00100000 + +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_LSB 21 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MSB 21 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00200000 + +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_LSB 22 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MSB 22 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00400000 + +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_LSB 23 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MSB 23 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00800000 + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x00000024 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff000000 + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x00000028 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x00000028 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x000f0000 + +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x00000028 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x0ff00000 + +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x00000028 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x10000000 + +#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x00000028 +#define TX_FES_STATUS_END_RESERVED_21B_LSB 29 +#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 +#define TX_FES_STATUS_END_RESERVED_21B_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/tx_fes_status_prot.h b/hw/peach/v2/tx_fes_status_prot.h new file mode 100644 index 000000000000..1188815204a3 --- /dev/null +++ b/hw/peach/v2/tx_fes_status_prot.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 3 + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + reserved_0 : 20, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4; + uint32_t frame_type : 2, + frame_subtype : 4, + rx_pwr_mgmt : 1, + status : 1, + duration_field : 16, + reserved_1a : 2, + agc_cbw : 3, + service_cbw : 3; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_2a : 16; +#else + uint32_t rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + reserved_0 : 20, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + success : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + reserved_1a : 2, + duration_field : 16, + status : 1, + rx_pwr_mgmt : 1, + frame_subtype : 4, + frame_type : 2; + uint32_t reserved_2a : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x00000001 + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x00000002 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000004 + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x007ffff8 + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x07800000 + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x08000000 + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0xf0000000 + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 0 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 1 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x00000003 + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 2 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 5 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 6 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 6 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x00000040 + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_STATUS_LSB 7 +#define TX_FES_STATUS_PROT_STATUS_MSB 7 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x00000080 + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 8 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 23 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff00 + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 24 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 25 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x03000000 + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 26 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 28 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c000000 + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 29 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 31 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe0000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 +#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 +#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/tx_fes_status_start.h b/hw/peach/v2/tx_fes_status_start.h new file mode 100644 index 000000000000..2bda42aeb3da --- /dev/null +++ b/hw/peach/v2/tx_fes_status_start.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t reserved_1a : 8, + transmit_start_reason : 3, + disabled_user_bitmap_36_32 : 5, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + schedule_try : 4, + medium_prot_type : 3, + reserved_1b : 2; + uint32_t optimal_bw_try_count : 4, + number_of_users : 7, + coex_nack_count : 5, + cca_ed0 : 16; + uint32_t disabled_user_bitmap_31_0 : 32; +#else + uint32_t schedule_id : 32; + uint32_t reserved_1b : 2, + medium_prot_type : 3, + schedule_try : 4, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + disabled_user_bitmap_36_32 : 5, + transmit_start_reason : 3, + reserved_1a : 8; + uint32_t cca_ed0 : 16, + coex_nack_count : 5, + number_of_users : 7, + optimal_bw_try_count : 4; + uint32_t disabled_user_bitmap_31_0 : 32; +#endif +}; + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x00000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0xffffffff + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 0 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 7 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 8 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 10 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x00000700 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 11 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 15 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f800 + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 16 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 20 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x00000004 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 21 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 22 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x00600000 + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x00000004 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 23 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 26 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x07800000 + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 27 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 29 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x38000000 + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x00000004 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 30 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 31 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc0000000 + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x00000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x0000000f + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x00000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x000007f0 + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x00000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x0000f800 + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x00000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0xffff0000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000c +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/tx_fes_status_start_ppdu.h b/hw/peach/v2/tx_fes_status_start_ppdu.h new file mode 100644 index 000000000000..ad43487ecb94 --- /dev/null +++ b/hw/peach/v2/tx_fes_status_start_ppdu.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + ndp_frame : 2, + reserved_2b : 2, + coex_based_tx_bw : 3, + coex_based_ant_mask : 8, + reserved_2c : 1; + uint32_t coex_based_tx_pwr_shared_ant : 8, + coex_based_tx_pwr_ant : 8, + concurrent_bt_tx : 1, + concurrent_wlan_tx : 1, + concurrent_wan_tx : 1, + concurrent_wan_rx : 1, + coex_pwr_reduction_bt : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_wan : 1, + coex_result_alt_based : 1, + request_packet_bw : 3, + response_type : 5; +#else + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t reserved_2c : 1, + coex_based_ant_mask : 8, + coex_based_tx_bw : 3, + reserved_2b : 2, + ndp_frame : 2, + subband_mask : 16; + uint32_t response_type : 5, + request_packet_bw : 3, + coex_result_alt_based : 1, + coex_pwr_reduction_wan : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_bt : 1, + concurrent_wan_rx : 1, + concurrent_wan_tx : 1, + concurrent_wlan_tx : 1, + concurrent_bt_tx : 1, + coex_based_tx_pwr_ant : 8, + coex_based_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x0000ffff + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x00030000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x000c0000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x00700000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x7f800000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x80000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 0 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 7 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 8 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 15 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff00 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 16 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 16 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x00010000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 17 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 17 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x00020000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 18 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 18 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 19 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 19 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x00100000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 21 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 21 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x00400000 + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x00800000 + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 24 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 26 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x07000000 + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 27 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v2/tx_fes_status_start_prot.h b/hw/peach/v2/tx_fes_status_start_prot.h new file mode 100644 index 000000000000..e2b31bff4527 --- /dev/null +++ b/hw/peach/v2/tx_fes_status_start_prot.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + reserved_2b : 4, + prot_coex_based_tx_bw : 3, + prot_coex_based_ant_mask : 8, + prot_coex_result_alt_based : 1; + uint32_t prot_coex_tx_pwr_shared_ant : 8, + prot_coex_tx_pwr_ant : 8, + prot_concurrent_bt_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wan_rx : 1, + prot_coex_pwr_reduction_bt : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_wan : 1, + prot_request_packet_bw : 3, + response_type : 5, + reserved_3a : 1; +#else + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t prot_coex_result_alt_based : 1, + prot_coex_based_ant_mask : 8, + prot_coex_based_tx_bw : 3, + reserved_2b : 4, + subband_mask : 16; + uint32_t reserved_3a : 1, + response_type : 5, + prot_request_packet_bw : 3, + prot_coex_pwr_reduction_wan : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_bt : 1, + prot_concurrent_wan_rx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_bt_tx : 1, + prot_coex_tx_pwr_ant : 8, + prot_coex_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x0000ffff + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x000f0000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x00700000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x7f800000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x80000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 7 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 8 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 15 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff00 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 16 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 16 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x00010000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 17 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 17 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x00020000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 18 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 18 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 19 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 19 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x00100000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 21 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 21 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x00400000 + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 25 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x03800000 + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 26 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 30 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c000000 + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 31 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 31 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/tx_fes_status_user_ppdu.h b/hw/peach/v2/tx_fes_status_user_ppdu.h new file mode 100644 index 000000000000..49b8e5f9e9f3 --- /dev/null +++ b/hw/peach/v2/tx_fes_status_user_ppdu.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + bw_drop_underflow_warning : 1, + qc_eosp_setting : 1, + fc_more_data_setting : 1, + fc_pwr_mgt_setting : 1, + mpdu_tx_count : 9, + user_blocked : 1, + pre_trig_response_delim_count : 7; + uint32_t underflow_byte_count : 16, + coex_abort_mpdu_count_valid : 1, + coex_abort_mpdu_count : 9, + transmitted_tid : 4, + txdma_dropped_mpdu_warning : 1, + reserved_1 : 1; + uint32_t duration : 16, + num_eof_delim_added : 16; + uint32_t psdu_octet : 24, + qos_buf_state : 8; + uint32_t num_null_delim_added : 22, + reserved_4a : 2, + cv_corr_user_valid_in_phy : 1, + nss : 3, + mcs : 4; + uint32_t ht_control : 32; +#else + uint32_t pre_trig_response_delim_count : 7, + user_blocked : 1, + mpdu_tx_count : 9, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 1, + qc_eosp_setting : 1, + bw_drop_underflow_warning : 1, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t reserved_1 : 1, + txdma_dropped_mpdu_warning : 1, + transmitted_tid : 4, + coex_abort_mpdu_count : 9, + coex_abort_mpdu_count_valid : 1, + underflow_byte_count : 16; + uint32_t num_eof_delim_added : 16, + duration : 16; + uint32_t qos_buf_state : 8, + psdu_octet : 24; + uint32_t mcs : 4, + nss : 3, + cv_corr_user_valid_in_phy : 1, + reserved_4a : 2, + num_null_delim_added : 22; + uint32_t ht_control : 32; +#endif +}; + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x00000600 + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x00000800 + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x00001000 + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x00002000 + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x00004000 + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x00ff8000 + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x01000000 + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0xfe000000 + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 15 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 16 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 16 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x00010000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 17 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 25 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe0000 + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 26 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 29 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c000000 + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 30 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 30 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x40000000 + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 31 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 31 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x80000000 + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x00000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x0000ffff + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x00000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0xffff0000 + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000c +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 0 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 23 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000c +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 24 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 31 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff000000 + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x003fffff + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x00c00000 + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x01000000 + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0e000000 + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0xf0000000 + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x00000014 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 0 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 31 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/tx_fes_status_user_response.h b/hw/peach/v2/tx_fes_status_user_response.h new file mode 100644 index 000000000000..0d45afbff135 --- /dev/null +++ b/hw/peach/v2/tx_fes_status_user_response.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, + reserved_0 : 28; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; +#else + uint32_t reserved_0 : 28, + fes_transmit_result : 4; + uint32_t reserved_after_struct16 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x0000000f + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0xfffffff0 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 16 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/tx_flush_req.h b/hw/peach/v2/tx_flush_req.h new file mode 100644 index 000000000000..8c141b9076a6 --- /dev/null +++ b/hw/peach/v2/tx_flush_req.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 1 + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, + phytx_abort_reason : 8, + flush_req_user_number_or_link_id : 6, + mlo_abort_reason : 5, + reserved_0a : 5; +#else + uint32_t reserved_0a : 5, + mlo_abort_reason : 5, + flush_req_user_number_or_link_id : 6, + phytx_abort_reason : 8, + flush_req_reason : 8; +#endif +}; + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x000000ff + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x0000ff00 + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x00000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x003f0000 + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x07c00000 + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x00000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v2/tx_mpdu_start.h b/hw/peach/v2/tx_mpdu_start.h new file mode 100644 index 000000000000..e7c273a2658a --- /dev/null +++ b/hw/peach/v2/tx_mpdu_start.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ + +#define NUM_OF_DWORDS_TX_MPDU_START 9 + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, + frame_not_from_tqm : 1, + vht_control_present : 1, + mpdu_header_length : 8, + retry_count : 7, + wds : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_47_32 : 16, + mpdu_sequence_number : 12, + raw_already_encrypted : 1, + frame_type : 2, + txdma_dropped_mpdu_warning : 1; + uint32_t iv_byte_0 : 8, + iv_byte_1 : 8, + iv_byte_2 : 8, + iv_byte_3 : 8; + uint32_t iv_byte_4 : 8, + iv_byte_5 : 8, + iv_byte_6 : 8, + iv_byte_7 : 8; + uint32_t iv_byte_8 : 8, + iv_byte_9 : 8, + iv_byte_10 : 8, + iv_byte_11 : 8; + uint32_t iv_byte_12 : 8, + iv_byte_13 : 8, + iv_byte_14 : 8, + iv_byte_15 : 8; + uint32_t iv_byte_16 : 8, + iv_byte_17 : 8, + iv_len : 5, + icv_len : 5, + vht_control_offset : 6; + uint32_t mpdu_type : 1, + transmit_bw_restriction : 1, + allowed_transmit_bw : 4, + tx_notify_frame : 3, + reserved_8a : 23; +#else + uint32_t wds : 1, + retry_count : 7, + mpdu_header_length : 8, + vht_control_present : 1, + frame_not_from_tqm : 1, + mpdu_length : 14; + uint32_t pn_31_0 : 32; + uint32_t txdma_dropped_mpdu_warning : 1, + frame_type : 2, + raw_already_encrypted : 1, + mpdu_sequence_number : 12, + pn_47_32 : 16; + uint32_t iv_byte_3 : 8, + iv_byte_2 : 8, + iv_byte_1 : 8, + iv_byte_0 : 8; + uint32_t iv_byte_7 : 8, + iv_byte_6 : 8, + iv_byte_5 : 8, + iv_byte_4 : 8; + uint32_t iv_byte_11 : 8, + iv_byte_10 : 8, + iv_byte_9 : 8, + iv_byte_8 : 8; + uint32_t iv_byte_15 : 8, + iv_byte_14 : 8, + iv_byte_13 : 8, + iv_byte_12 : 8; + uint32_t vht_control_offset : 6, + icv_len : 5, + iv_len : 5, + iv_byte_17 : 8, + iv_byte_16 : 8; + uint32_t reserved_8a : 23, + tx_notify_frame : 3, + allowed_transmit_bw : 4, + transmit_bw_restriction : 1, + mpdu_type : 1; +#endif +}; + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x00000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x00003fff + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x00000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x00004000 + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x00000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x00008000 + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x00000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x00ff0000 + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x00000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x7f000000 + +#define TX_MPDU_START_WDS_OFFSET 0x00000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x80000000 + +#define TX_MPDU_START_PN_31_0_OFFSET 0x00000004 +#define TX_MPDU_START_PN_31_0_LSB 0 +#define TX_MPDU_START_PN_31_0_MSB 31 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff + +#define TX_MPDU_START_PN_47_32_OFFSET 0x00000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x0000ffff + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x0fff0000 + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x00000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x10000000 + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x00000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x60000000 + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x80000000 + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_0_LSB 0 +#define TX_MPDU_START_IV_BYTE_0_MSB 7 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_1_LSB 8 +#define TX_MPDU_START_IV_BYTE_1_MSB 15 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_2_LSB 16 +#define TX_MPDU_START_IV_BYTE_2_MSB 23 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_3_LSB 24 +#define TX_MPDU_START_IV_BYTE_3_MSB 31 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_8_LSB 0 +#define TX_MPDU_START_IV_BYTE_8_MSB 7 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_9_LSB 8 +#define TX_MPDU_START_IV_BYTE_9_MSB 15 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_10_LSB 16 +#define TX_MPDU_START_IV_BYTE_10_MSB 23 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_11_LSB 24 +#define TX_MPDU_START_IV_BYTE_11_MSB 31 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000001c +#define TX_MPDU_START_IV_BYTE_16_LSB 0 +#define TX_MPDU_START_IV_BYTE_16_MSB 7 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000001c +#define TX_MPDU_START_IV_BYTE_17_LSB 8 +#define TX_MPDU_START_IV_BYTE_17_MSB 15 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000001c +#define TX_MPDU_START_IV_LEN_LSB 16 +#define TX_MPDU_START_IV_LEN_MSB 20 +#define TX_MPDU_START_IV_LEN_MASK 0x001f0000 + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000001c +#define TX_MPDU_START_ICV_LEN_LSB 21 +#define TX_MPDU_START_ICV_LEN_MSB 25 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e00000 + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000001c +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 26 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 31 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc000000 + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x00000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x00000001 + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x00000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x00000002 + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x00000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x0000003c + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x00000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x000001c0 + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x00000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0xfffffe00 + +#endif diff --git a/hw/peach/v2/tx_msdu_extension.h b/hw/peach/v2/tx_msdu_extension.h new file mode 100644 index 000000000000..b6842c375263 --- /dev/null +++ b/hw/peach/v2/tx_msdu_extension.h @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + extn_override : 1, + encap_type : 2, + encrypt_type : 4, + tqm_no_drop : 1, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + epd : 1, + mesh_enable : 2, + reserved_9a : 5, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + dscp_tid_table_num : 6, + reserved_11a : 2, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +#else + uint32_t reserved_0b : 7, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_0a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t udp_length : 16, + ip_identification : 16; + uint32_t reserved_4b : 2, + payload_start_offset : 14, + reserved_4a : 1, + partial_checksum_en : 1, + checksum_offset : 14; + uint32_t reserved_5b : 15, + wds : 1, + reserved_5a : 2, + payload_end_offset : 14; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_len : 16, + tqm_no_drop : 1, + encrypt_type : 4, + encap_type : 2, + extn_override : 1, + buf0_ptr_39_32 : 8; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_len : 16, + reserved_9a : 5, + mesh_enable : 2, + epd : 1, + buf1_ptr_39_32 : 8; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_len : 16, + reserved_11a : 2, + dscp_tid_table_num : 6, + buf2_ptr_39_32 : 8; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_len : 16, + reserved_13a : 8, + buf3_ptr_39_32 : 8; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_len : 16, + reserved_15a : 8, + buf4_ptr_39_32 : 8; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_len : 16, + reserved_17a : 8, + buf5_ptr_39_32 : 8; +#endif +}; + +#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 +#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e + +#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 + +#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 +#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 + +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_WDS_LSB 16 +#define TX_MSDU_EXTENSION_WDS_MSB 16 +#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 + +#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 + +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 + +#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_EPD_LSB 8 +#define TX_MSDU_EXTENSION_EPD_MSB 8 +#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 +#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 + +#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 + +#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/tx_msdu_start.h b/hw/peach/v2/tx_msdu_start.h new file mode 100644 index 000000000000..1c231bfb685a --- /dev/null +++ b/hw/peach/v2/tx_msdu_start.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ + +#define NUM_OF_DWORDS_TX_MSDU_START 7 + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, + first_msdu : 1, + last_msdu : 1, + encap_type : 2, + epd_en : 1, + da_sa_present : 2, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + dummy_msdu_delimitation : 1, + reserved_0a : 5; + uint32_t tso_enable : 1, + reserved_1a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + mesh_enable : 1, + reserved_1b : 6; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + checksum_offset : 13, + partial_checksum_en : 1, + reserved_4 : 2; + uint32_t payload_start_offset : 14, + reserved_5a : 2, + payload_end_offset : 14, + reserved_5b : 2; + uint32_t udp_length : 16, + reserved_6 : 16; +#else + uint32_t reserved_0a : 5, + dummy_msdu_delimitation : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + da_sa_present : 2, + epd_en : 1, + encap_type : 2, + last_msdu : 1, + first_msdu : 1, + msdu_len : 14; + uint32_t reserved_1b : 6, + mesh_enable : 1, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_1a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t reserved_4 : 2, + partial_checksum_en : 1, + checksum_offset : 13, + ip_identification : 16; + uint32_t reserved_5b : 2, + payload_end_offset : 14, + reserved_5a : 2, + payload_start_offset : 14; + uint32_t reserved_6 : 16, + udp_length : 16; +#endif +}; + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x00000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x00003fff + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x00000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x00004000 + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x00000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x00008000 + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x00000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x00030000 + +#define TX_MSDU_START_EPD_EN_OFFSET 0x00000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x00040000 + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x00000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x00180000 + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x00200000 + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00400000 + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00800000 + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x01000000 + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x02000000 + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x00000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x04000000 + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0xf8000000 + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x00000004 +#define TX_MSDU_START_TSO_ENABLE_LSB 0 +#define TX_MSDU_START_TSO_ENABLE_MSB 0 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x00000004 +#define TX_MSDU_START_RESERVED_1A_LSB 1 +#define TX_MSDU_START_RESERVED_1A_MSB 6 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x00000004 +#define TX_MSDU_START_TCP_FLAG_LSB 7 +#define TX_MSDU_START_TCP_FLAG_MSB 15 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x00000004 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x00000004 +#define TX_MSDU_START_MESH_ENABLE_LSB 25 +#define TX_MSDU_START_MESH_ENABLE_MSB 25 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x02000000 + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x00000004 +#define TX_MSDU_START_RESERVED_1B_LSB 26 +#define TX_MSDU_START_RESERVED_1B_MSB 31 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc000000 + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x00000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x00000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000c +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x00000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x1fff0000 + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x20000000 + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x00000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0xc0000000 + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 0 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 13 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_START_RESERVED_5A_LSB 14 +#define TX_MSDU_START_RESERVED_5A_MSB 15 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 16 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 29 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_START_RESERVED_5B_LSB 30 +#define TX_MSDU_START_RESERVED_5B_MSB 31 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc0000000 + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x00000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x00000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/tx_peer_entry.h b/hw/peach/v2/tx_peer_entry.h new file mode 100644 index 000000000000..c1557ccae516 --- /dev/null +++ b/hw/peach/v2/tx_peer_entry.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_a_47_32 : 16, + mac_addr_b_15_0 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t use_ad_b : 1, + strip_insert_vlan_inner : 1, + strip_insert_vlan_outer : 1, + vlan_llc_mode : 1, + key_type : 4, + a_msdu_wds_ad3_ad4 : 3, + ignore_hard_filters : 1, + ignore_soft_filters : 1, + epd_output : 1, + wds : 1, + insert_or_strip : 1, + sw_filter_id : 16; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t sta_partial_aid : 11, + transmit_vif : 4, + block_this_user : 1, + mesh_amsdu_mode : 2, + use_qos_alt_mute_mask : 1, + dl_ul_direction : 1, + reserved_12 : 12; + uint32_t insert_vlan_outer_tci : 16, + insert_vlan_inner_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t multi_link_addr_crypto_enable : 1, + reserved_17a : 15, + sw_peer_id : 16; +#else + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_b_15_0 : 16, + mac_addr_a_47_32 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t sw_filter_id : 16, + insert_or_strip : 1, + wds : 1, + epd_output : 1, + ignore_soft_filters : 1, + ignore_hard_filters : 1, + a_msdu_wds_ad3_ad4 : 3, + key_type : 4, + vlan_llc_mode : 1, + strip_insert_vlan_outer : 1, + strip_insert_vlan_inner : 1, + use_ad_b : 1; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t reserved_12 : 12, + dl_ul_direction : 1, + use_qos_alt_mute_mask : 1, + mesh_amsdu_mode : 2, + block_this_user : 1, + transmit_vif : 4, + sta_partial_aid : 11; + uint32_t insert_vlan_inner_tci : 16, + insert_vlan_outer_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t sw_peer_id : 16, + reserved_17a : 15, + multi_link_addr_crypto_enable : 1; +#endif +}; + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x00000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0xffffffff + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x00000004 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 15 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x00000004 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 16 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff0000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x00000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0xffffffff + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000c +#define TX_PEER_ENTRY_USE_AD_B_LSB 0 +#define TX_PEER_ENTRY_USE_AD_B_MSB 0 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x00000001 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000c +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 1 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 1 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x00000002 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000c +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 2 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 2 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x00000004 + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000c +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 3 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 3 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x00000008 + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000c +#define TX_PEER_ENTRY_KEY_TYPE_LSB 4 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 7 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f0 + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000c +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 8 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 10 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x00000700 + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 11 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 11 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x00000800 + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 12 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 12 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x00001000 + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000c +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 13 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 13 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x00002000 + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_WDS_LSB 14 +#define TX_PEER_ENTRY_WDS_MSB 14 +#define TX_PEER_ENTRY_WDS_MASK 0x00004000 + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000c +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 15 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 15 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x00008000 + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000c +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 16 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 31 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff0000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x00000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x00000014 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x00000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000001c +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x00000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x00000024 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x00000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000002c +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x00000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x000007ff + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x00000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x00007800 + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x00000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x00008000 + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x00000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x00030000 + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x00000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x00040000 + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x00000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x00080000 + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x00000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0xfff00000 + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x00000034 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 0 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 15 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x00000034 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 16 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 31 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff0000 + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x00000044 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x00000001 + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x00000044 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 1 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 15 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x00000044 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 16 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 31 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/tx_queue_extension.h b/hw/peach/v2/tx_queue_extension.h new file mode 100644 index 000000000000..364686c59c3b --- /dev/null +++ b/hw/peach/v2/tx_queue_extension.h @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, + qos_ctl : 16; + uint32_t ampdu_flag : 1, + tx_notify_no_htc_override : 1, + reserved_1a : 7, + checksum_tso_disable_for_frag : 1, + key_id : 8, + qos_buf_state_overwrite : 1, + buf_state_sta_id : 1, + buf_state_source : 1, + ht_control_overwrite_enable : 1, + ht_control_overwrite_source : 4, + reserved_1b : 6; + uint32_t ul_headroom_insertion_enable : 1, + ul_headroom_offset : 5, + bqrp_insertion_enable : 1, + bqrp_offset : 5, + ul_headroom_rsvd_7_6 : 2, + bqr_rsvd_9_8 : 2, + base_pn_63_48 : 16; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t cas_control_info : 8, + cas_offset : 5, + cas_insertion_enable : 1, + reserved_10a : 2, + ht_control_overwrite_source_for_srp : 4, + ht_control_overwrite_source_for_bsrp : 4, + reserved_10b : 6, + mpdu_hdr_len_override_en : 1, + bar_ssn_overwrite_enable : 1; + uint32_t bar_ssn_offset : 12, + mpdu_hdr_len_override_val : 9, + reserved_11a : 11; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#else + uint32_t qos_ctl : 16, + frame_ctl : 16; + uint32_t reserved_1b : 6, + ht_control_overwrite_source : 4, + ht_control_overwrite_enable : 1, + buf_state_source : 1, + buf_state_sta_id : 1, + qos_buf_state_overwrite : 1, + key_id : 8, + checksum_tso_disable_for_frag : 1, + reserved_1a : 7, + tx_notify_no_htc_override : 1, + ampdu_flag : 1; + uint32_t base_pn_63_48 : 16, + bqr_rsvd_9_8 : 2, + ul_headroom_rsvd_7_6 : 2, + bqrp_offset : 5, + bqrp_insertion_enable : 1, + ul_headroom_offset : 5, + ul_headroom_insertion_enable : 1; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t bar_ssn_overwrite_enable : 1, + mpdu_hdr_len_override_en : 1, + reserved_10b : 6, + ht_control_overwrite_source_for_bsrp : 4, + ht_control_overwrite_source_for_srp : 4, + reserved_10a : 2, + cas_insertion_enable : 1, + cas_offset : 5, + cas_control_info : 8; + uint32_t reserved_11a : 11, + mpdu_hdr_len_override_val : 9, + bar_ssn_offset : 12; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x00000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x0000ffff + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x00000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0xffff0000 + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 0 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 0 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x00000001 + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 1 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 1 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x00000002 + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 2 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 8 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 9 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 9 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x00000200 + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 10 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 17 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc00 + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 18 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 18 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x00040000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 19 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 19 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x00080000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 20 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 20 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x00100000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 21 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 21 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x00200000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 22 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 25 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c00000 + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 26 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 31 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc000000 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x00000001 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x0000003e + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x00000040 + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x00000f80 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x00003000 + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x0000c000 + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0xffff0000 + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000c +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x00000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x00000014 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x00000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000001c +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x00000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x00000024 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x000000ff + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x00001f00 + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x00002000 + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x0000c000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x000f0000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x00f00000 + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x3f000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x40000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x80000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 0 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 12 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 20 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff000 + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 21 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 31 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe00000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x00000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x00000034 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/tx_rate_stats_info.h b/hw/peach/v2/tx_rate_stats_info.h new file mode 100644 index 000000000000..24caaab83893 --- /dev/null +++ b/hw/peach/v2/tx_rate_stats_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 3, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + transmit_nss : 3; + uint32_t ppdu_transmission_tsf : 32; +#else + uint32_t transmit_nss : 3, + tones_in_ru : 12, + ofdma_transmission : 1, + transmit_mcs : 4, + transmit_sgi : 2, + transmit_ldpc : 1, + transmit_stbc : 1, + transmit_pkt_type : 4, + transmit_bw : 3, + tx_rate_stats_info_valid : 1; + uint32_t ppdu_transmission_tsf : 32; +#endif +}; + +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e + +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 + +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 + +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 + +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000 + +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000 + +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 + +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/tx_raw_or_native_frame_setup.h b/hw/peach/v2/tx_raw_or_native_frame_setup.h new file mode 100644 index 000000000000..47712f8766c5 --- /dev/null +++ b/hw/peach/v2/tx_raw_or_native_frame_setup.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, + fc_from_ds_mask : 1, + fc_more_frag_mask : 1, + fc_retry_mask : 1, + fc_pwr_mgt_mask : 1, + fc_more_data_mask : 1, + fc_prot_frame_mask : 1, + fc_order_mask : 1, + duration_field_mask : 1, + sequence_control_mask : 1, + qc_tid_mask : 1, + qc_eosp_mask : 1, + qc_ack_policy_mask : 1, + qc_amsdu_mask : 1, + reserved_0a : 1, + qc_15to8_mask : 1, + iv_mask : 1, + fc_to_ds_setting : 1, + fc_from_ds_setting : 1, + fc_more_frag_setting : 1, + fc_retry_setting : 2, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 2, + fc_prot_frame_setting : 2, + fc_order_setting : 1, + qc_tid_setting : 4; + uint32_t qc_eosp_setting : 2, + qc_ack_policy_setting : 2, + qc_amsdu_setting : 1, + qc_15to8_setting : 8, + mlo_addr_override : 1, + mlo_ignore_addr3_override : 1, + sequence_control_source : 1, + fragment_number : 4, + sequence_number : 12; +#else + uint32_t qc_tid_setting : 4, + fc_order_setting : 1, + fc_prot_frame_setting : 2, + fc_more_data_setting : 2, + fc_pwr_mgt_setting : 1, + fc_retry_setting : 2, + fc_more_frag_setting : 1, + fc_from_ds_setting : 1, + fc_to_ds_setting : 1, + iv_mask : 1, + qc_15to8_mask : 1, + reserved_0a : 1, + qc_amsdu_mask : 1, + qc_ack_policy_mask : 1, + qc_eosp_mask : 1, + qc_tid_mask : 1, + sequence_control_mask : 1, + duration_field_mask : 1, + fc_order_mask : 1, + fc_prot_frame_mask : 1, + fc_more_data_mask : 1, + fc_pwr_mgt_mask : 1, + fc_retry_mask : 1, + fc_more_frag_mask : 1, + fc_from_ds_mask : 1, + fc_to_ds_mask : 1; + uint32_t sequence_number : 12, + fragment_number : 4, + sequence_control_source : 1, + mlo_ignore_addr3_override : 1, + mlo_addr_override : 1, + qc_15to8_setting : 8, + qc_amsdu_setting : 1, + qc_ack_policy_setting : 2, + qc_eosp_setting : 2; +#endif +}; + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x00000001 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x00000002 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x00000004 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x00000008 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x00000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x00000020 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x00000040 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x00000080 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x00000100 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x00000200 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x00000400 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x00000800 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x00001000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x00002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x00004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x00008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x00010000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x00020000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x00040000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x00080000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x00300000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x00400000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x01800000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x06000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x08000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0xf0000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x00000003 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x00000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe0 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x00002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x00004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x00008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f0000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff00000 + +#endif diff --git a/hw/peach/v2/txpcu_buffer_basics.h b/hw/peach/v2/txpcu_buffer_basics.h new file mode 100644 index 000000000000..ff894c9b9faa --- /dev/null +++ b/hw/peach/v2/txpcu_buffer_basics.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, + partial_tx_data_tlv_count : 8, + tx_data_tlv_count : 16; +#else + uint32_t tx_data_tlv_count : 16, + partial_tx_data_tlv_count : 8, + available_memory : 8; +#endif +}; + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/txpcu_buffer_status.h b/hw/peach/v2/txpcu_buffer_status.h new file mode 100644 index 000000000000..551da7555a03 --- /dev/null +++ b/hw/peach/v2/txpcu_buffer_status.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved : 15; +#endif +}; + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 0 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 14 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 15 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 15 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x00008000 + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/txpcu_user_buffer_status.h b/hw/peach/v2/txpcu_user_buffer_status.h new file mode 100644 index 000000000000..feb231558caa --- /dev/null +++ b/hw/peach/v2/txpcu_user_buffer_status.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, + reserved_1a : 1, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved_1a : 1, + stored_word_count_user : 14; +#endif +}; + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 13 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 14 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 14 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x00004000 + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 15 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x00008000 + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v2/u_sig_eht_su_mu_info.h b/hw/peach/v2/u_sig_eht_su_mu_info.h new file mode 100644 index 000000000000..f5236058122e --- /dev/null +++ b/hw/peach/v2/u_sig_eht_su_mu_info.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 5, + validate_0b : 1, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + punctured_channel_information : 5, + validate_1b : 1, + mcs_of_eht_sig : 2, + num_eht_sig_symbols : 5, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + reserved_1d : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + validate_0b : 1, + disregard_0a : 5, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + reserved_1d : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + num_eht_sig_symbols : 5, + mcs_of_eht_sig : 2, + validate_1b : 1, + punctured_channel_information : 5, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/u_sig_eht_tb_info.h b/hw/peach/v2/u_sig_eht_tb_info.h new file mode 100644 index 000000000000..e7582e20b5dd --- /dev/null +++ b/hw/peach/v2/u_sig_eht_tb_info.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 6, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + spatial_reuse : 8, + disregard_1b : 5, + crc : 4, + tail : 6, + reserved_1c : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + disregard_0a : 6, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + reserved_1c : 5, + tail : 6, + crc : 4, + disregard_1b : 5, + spatial_reuse : 8, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/unallocated_ru_160_info.h b/hw/peach/v2/unallocated_ru_160_info.h new file mode 100644 index 000000000000..64d9f05e2e37 --- /dev/null +++ b/hw/peach/v2/unallocated_ru_160_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, + subband80_0_cc1 : 8, + subband80_1_cc0 : 8, + subband80_1_cc1 : 8; +#else + uint32_t subband80_1_cc1 : 8, + subband80_1_cc0 : 8, + subband80_0_cc1 : 8, + subband80_0_cc0 : 8; +#endif +}; + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + +#endif diff --git a/hw/peach/v2/uniform_descriptor_header.h b/hw/peach/v2/uniform_descriptor_header.h new file mode 100644 index 000000000000..9e60a8023b6f --- /dev/null +++ b/hw/peach/v2/uniform_descriptor_header.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t owner : 4, + buffer_type : 4, + tx_mpdu_queue_number : 20, + reserved_0a : 4; +#else + uint32_t reserved_0a : 4, + tx_mpdu_queue_number : 20, + buffer_type : 4, + owner : 4; +#endif +}; + +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/uniform_reo_cmd_header.h b/hw/peach/v2/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..8f46533746e4 --- /dev/null +++ b/hw/peach/v2/uniform_reo_cmd_header.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +#else + uint32_t reserved_0a : 15, + reo_status_required : 1, + reo_cmd_number : 16; +#endif +}; + +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#endif diff --git a/hw/peach/v2/uniform_reo_status_header.h b/hw/peach/v2/uniform_reo_status_header.h new file mode 100644 index 000000000000..aadf1598bb90 --- /dev/null +++ b/hw/peach/v2/uniform_reo_status_header.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +#else + uint32_t reserved_0a : 4, + reo_cmd_execution_status : 2, + cmd_execution_time : 10, + reo_status_number : 16; + uint32_t timestamp : 32; +#endif +}; + +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/hw/peach/v2/vht_sig_a_info.h b/hw/peach/v2/vht_sig_a_info.h new file mode 100644 index 000000000000..a4698df5e028 --- /dev/null +++ b/hw/peach/v2/vht_sig_a_info.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + vhta_reserved_0b : 1, + txop_ps_not_allowed : 1, + n_sts : 12, + group_id : 6, + stbc : 1, + vhta_reserved_0 : 1, + bandwidth : 2; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + tail : 6, + crc : 8, + vhta_reserved_1 : 1, + beamformed : 1, + mcs : 4, + ldpc_extra_symbol : 1, + su_mu_coding : 1, + gi_setting : 2; +#endif +}; + +#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 +#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 + +#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_STBC_LSB 3 +#define VHT_SIG_A_INFO_STBC_MSB 3 +#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 + +#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 +#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 + +#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_N_STS_LSB 10 +#define VHT_SIG_A_INFO_N_STS_MSB 21 +#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 + +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 + +#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 + +#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 +#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 + +#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 + +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_MCS_LSB 4 +#define VHT_SIG_A_INFO_MCS_MSB 7 +#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 + +#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 + +#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_CRC_LSB 10 +#define VHT_SIG_A_INFO_CRC_MSB 17 +#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 + +#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_TAIL_LSB 18 +#define VHT_SIG_A_INFO_TAIL_MSB 23 +#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 + +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_mu160_info.h b/hw/peach/v2/vht_sig_b_mu160_info.h new file mode 100644 index 000000000000..83aea9e93772 --- /dev/null +++ b/hw/peach/v2/vht_sig_b_mu160_info.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + reserved_2 : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; + uint32_t length_copy_d : 19, + mcs_copy_d : 4, + tail_copy_d : 6, + reserved_4 : 3; + uint32_t length_copy_e : 19, + mcs_copy_e : 4, + tail_copy_e : 6, + reserved_5 : 3; + uint32_t length_copy_f : 19, + mcs_copy_f : 4, + tail_copy_f : 6, + mu_user_number : 3; + uint32_t length_copy_g : 19, + mcs_copy_g : 4, + tail_copy_g : 6, + reserved_7 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t reserved_2 : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; + uint32_t reserved_4 : 3, + tail_copy_d : 6, + mcs_copy_d : 4, + length_copy_d : 19; + uint32_t reserved_5 : 3, + tail_copy_e : 6, + mcs_copy_e : 4, + length_copy_e : 19; + uint32_t mu_user_number : 3, + tail_copy_f : 6, + mcs_copy_f : 4, + length_copy_f : 19; + uint32_t reserved_7 : 3, + tail_copy_g : 6, + mcs_copy_g : 4, + length_copy_g : 19; +#endif +}; + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_mu20_info.h b/hw/peach/v2/vht_sig_b_mu20_info.h new file mode 100644 index 000000000000..7a886644462f --- /dev/null +++ b/hw/peach/v2/vht_sig_b_mu20_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, + mcs : 4, + tail : 6, + mu_user_number : 3, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + mu_user_number : 3, + tail : 6, + mcs : 4, + length : 16; +#endif +}; + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_mu40_info.h b/hw/peach/v2/vht_sig_b_mu40_info.h new file mode 100644 index 000000000000..cf8f2a8ab6c3 --- /dev/null +++ b/hw/peach/v2/vht_sig_b_mu40_info.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + mcs : 4, + tail : 6, + reserved_0 : 2, + mu_user_number : 3; + uint32_t length_copy : 17, + mcs_copy : 4, + tail_copy : 6, + reserved_1 : 5; +#else + uint32_t mu_user_number : 3, + reserved_0 : 2, + tail : 6, + mcs : 4, + length : 17; + uint32_t reserved_1 : 5, + tail_copy : 6, + mcs_copy : 4, + length_copy : 17; +#endif +}; + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_mu80_info.h b/hw/peach/v2/vht_sig_b_mu80_info.h new file mode 100644 index 000000000000..89c78af42d6e --- /dev/null +++ b/hw/peach/v2/vht_sig_b_mu80_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + mu_user_number : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t mu_user_number : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; +#endif +}; + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_su160_info.h b/hw/peach/v2/vht_sig_b_su160_info.h new file mode 100644 index 000000000000..b48c64d189e8 --- /dev/null +++ b/hw/peach/v2/vht_sig_b_su160_info.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; + uint32_t length_copy_d : 21, + vhtb_reserved_copy_d : 2, + tail_copy_d : 6, + reserved_4 : 2, + rx_ndp_copy_d : 1; + uint32_t length_copy_e : 21, + vhtb_reserved_copy_e : 2, + tail_copy_e : 6, + reserved_5 : 2, + rx_ndp_copy_e : 1; + uint32_t length_copy_f : 21, + vhtb_reserved_copy_f : 2, + tail_copy_f : 6, + reserved_6 : 2, + rx_ndp_copy_f : 1; + uint32_t length_copy_g : 21, + vhtb_reserved_copy_g : 2, + tail_copy_g : 6, + reserved_7 : 2, + rx_ndp_copy_g : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; + uint32_t rx_ndp_copy_d : 1, + reserved_4 : 2, + tail_copy_d : 6, + vhtb_reserved_copy_d : 2, + length_copy_d : 21; + uint32_t rx_ndp_copy_e : 1, + reserved_5 : 2, + tail_copy_e : 6, + vhtb_reserved_copy_e : 2, + length_copy_e : 21; + uint32_t rx_ndp_copy_f : 1, + reserved_6 : 2, + tail_copy_f : 6, + vhtb_reserved_copy_f : 2, + length_copy_f : 21; + uint32_t rx_ndp_copy_g : 1, + reserved_7 : 2, + tail_copy_g : 6, + vhtb_reserved_copy_g : 2, + length_copy_g : 21; +#endif +}; + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_su20_info.h b/hw/peach/v2/vht_sig_b_su20_info.h new file mode 100644 index 000000000000..d61a57cf8dc7 --- /dev/null +++ b/hw/peach/v2/vht_sig_b_su20_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + vhtb_reserved : 3, + tail : 6, + reserved : 5, + rx_ndp : 1; +#else + uint32_t rx_ndp : 1, + reserved : 5, + tail : 6, + vhtb_reserved : 3, + length : 17; +#endif +}; + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_su40_info.h b/hw/peach/v2/vht_sig_b_su40_info.h new file mode 100644 index 000000000000..f00e156e15f1 --- /dev/null +++ b/hw/peach/v2/vht_sig_b_su40_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + vhtb_reserved : 2, + tail : 6, + reserved : 4, + rx_ndp : 1; + uint32_t length_copy : 19, + vhtb_reserved_copy : 2, + tail_copy : 6, + reserved_copy : 4, + rx_ndp_copy : 1; +#else + uint32_t rx_ndp : 1, + reserved : 4, + tail : 6, + vhtb_reserved : 2, + length : 19; + uint32_t rx_ndp_copy : 1, + reserved_copy : 4, + tail_copy : 6, + vhtb_reserved_copy : 2, + length_copy : 19; +#endif +}; + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/vht_sig_b_su80_info.h b/hw/peach/v2/vht_sig_b_su80_info.h new file mode 100644 index 000000000000..71d2448a2d3f --- /dev/null +++ b/hw/peach/v2/vht_sig_b_su80_info.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; +#endif +}; + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/hw/peach/v2/wbm2sw_completion_ring_rx.h b/hw/peach/v2/wbm2sw_completion_ring_rx.h new file mode 100644 index 000000000000..4666a3a056e8 --- /dev/null +++ b/hw/peach/v2/wbm2sw_completion_ring_rx.h @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM2SW_COMPLETION_RING_RX_H_ +#define _WBM2SW_COMPLETION_RING_RX_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 + +struct wbm2sw_completion_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t buffer_phys_addr_39_32 : 8, + sw_buffer_cookie : 20, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t looping_count : 4, + sw_buffer_cookie : 20, + buffer_phys_addr_39_32 : 8; +#endif +}; + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 + +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/wbm2sw_completion_ring_tx.h b/hw/peach/v2/wbm2sw_completion_ring_tx.h new file mode 100644 index 000000000000..5cdd5fb408ed --- /dev/null +++ b/hw/peach/v2/wbm2sw_completion_ring_tx.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM2SW_COMPLETION_RING_TX_H_ +#define _WBM2SW_COMPLETION_RING_TX_H_ + +#include "tx_rate_stats_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 + +struct wbm2sw_completion_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + cache_id : 1, + reserved_2a : 2, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + sw_buffer_cookie_11_0 : 12, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + sw_buffer_cookie_19_12 : 8, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + sw_buffer_cookie_11_0 : 12, + rbm_override_valid : 1, + tqm_release_reason : 4, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + reserved_2a : 2, + cache_id : 1, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + sw_buffer_cookie_19_12 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 + +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 + +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 +#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 + +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/wbm_buffer_ring.h b/hw/peach/v2/wbm_buffer_ring.h new file mode 100644 index 000000000000..0c80ee2b25f1 --- /dev/null +++ b/hw/peach/v2/wbm_buffer_ring.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; +#else + struct buffer_addr_info buf_addr_info; +#endif +}; + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/wbm_link_descriptor_ring.h b/hw/peach/v2/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..6c1f85cc37f8 --- /dev/null +++ b/hw/peach/v2/wbm_link_descriptor_ring.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info desc_addr_info; +#else + struct buffer_addr_info desc_addr_info; +#endif +}; + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v2/wbm_release_ring.h b/hw/peach/v2/wbm_release_ring.h new file mode 100644 index 000000000000..1b75a6f592dd --- /dev/null +++ b/hw/peach/v2/wbm_release_ring.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + reserved_2a : 3, + buffer_or_desc_type : 3, + reserved_2b : 22, + wbm_internal_error : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 28, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reserved_2b : 22, + buffer_or_desc_type : 3, + reserved_2a : 3, + release_source_module : 3; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + reserved_7a : 28; +#endif +}; + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 +#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 +#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 + +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 +#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 +#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 + +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 +#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff + +#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/wbm_release_ring_rx.h b/hw/peach/v2/wbm_release_ring_rx.h new file mode 100644 index 000000000000..08af9fe3f31c --- /dev/null +++ b/hw/peach/v2/wbm_release_ring_rx.h @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_RX_H_ +#define _WBM_RELEASE_RING_RX_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 + +struct wbm_release_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff + +#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RING_ID_LSB 20 +#define WBM_RELEASE_RING_RX_RING_ID_MSB 27 +#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/wbm_release_ring_tx.h b/hw/peach/v2/wbm_release_ring_tx.h new file mode 100644 index 000000000000..d9a91b248dfd --- /dev/null +++ b/hw/peach/v2/wbm_release_ring_tx.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_TX_H_ +#define _WBM_RELEASE_RING_TX_H_ + +#include "tx_rate_stats_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 + +struct wbm_release_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + rbm_override : 4, + reserved_2a : 7, + cache_id : 1, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + tqm_status_number_31_24 : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 7, + rbm_override : 4, + rbm_override_valid : 1, + tqm_release_reason : 4, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + tqm_status_number_31_24 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 + +#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 + +#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 + +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TID_LSB 16 +#define WBM_RELEASE_RING_TX_TID_MSB 19 +#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v2/wcss_seq_hwiobase.h b/hw/peach/v2/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..41736a1e7ee3 --- /dev/null +++ b/hw/peach/v2/wcss_seq_hwiobase.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOBASE_H__ +#define __WCSS_SEQ_HWIOBASE_H__ + +#define WCSS_CFGBUS_BASE 0x00008000 +#define WCSS_CFGBUS_BASE_SIZE 0x00008000 +#define WCSS_CFGBUS_BASE_PHYS 0x00008000 + +#define UMAC_NOC_BASE 0x00140000 +#define UMAC_NOC_BASE_SIZE 0x00004400 +#define UMAC_NOC_BASE_PHYS 0x00140000 + +#define PHYA0_BASE 0x00300000 +#define PHYA0_BASE_SIZE 0x00300000 +#define PHYA0_BASE_PHYS 0x00300000 + +#define PHYA1_BASE 0x00600000 +#define PHYA1_BASE_SIZE 0x00300000 +#define PHYA1_BASE_PHYS 0x00600000 + +#define DMAC_BASE 0x00900000 +#define DMAC_BASE_SIZE 0x00080000 +#define DMAC_BASE_PHYS 0x00900000 + +#define UMAC_BASE 0x00a00000 +#define UMAC_BASE_SIZE 0x0004d000 +#define UMAC_BASE_PHYS 0x00a00000 + +#define PMAC0_BASE 0x00a80000 +#define PMAC0_BASE_SIZE 0x00040000 +#define PMAC0_BASE_PHYS 0x00a80000 + +#define PMAC1_BASE 0x00ac0000 +#define PMAC1_BASE_SIZE 0x00040000 +#define PMAC1_BASE_PHYS 0x00ac0000 + +#define WFSS_AMCSS_BASE 0x00b00000 +#define WFSS_AMCSS_BASE_SIZE 0x00040000 +#define WFSS_AMCSS_BASE_PHYS 0x00b00000 + +#define CXC_BASE 0x00b40000 +#define CXC_BASE_SIZE 0x00010000 +#define CXC_BASE_PHYS 0x00b40000 + +#define WFSS_PMM_BASE 0x00b50000 +#define WFSS_PMM_BASE_SIZE 0x00002401 +#define WFSS_PMM_BASE_PHYS 0x00b50000 + +#define WFSS_CC_BASE 0x00b60000 +#define WFSS_CC_BASE_SIZE 0x00008000 +#define WFSS_CC_BASE_PHYS 0x00b60000 + +#define WCMN_CORE_BASE 0x00b68000 +#define WCMN_CORE_BASE_SIZE 0x000008a9 +#define WCMN_CORE_BASE_PHYS 0x00b68000 + +#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000 +#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 + +#define WFSS_CFGBUS_BASE 0x00b6c000 +#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 +#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 + +#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 + +#define UMAC_ACMT_BASE 0x00b6e000 +#define UMAC_ACMT_BASE_SIZE 0x00001000 +#define UMAC_ACMT_BASE_PHYS 0x00b6e000 + +#define WCSS_CC_BASE 0x00b80000 +#define WCSS_CC_BASE_SIZE 0x00010000 +#define WCSS_CC_BASE_PHYS 0x00b80000 + +#define PMM_TOP_BASE 0x00b90000 +#define PMM_TOP_BASE_SIZE 0x00010000 +#define PMM_TOP_BASE_PHYS 0x00b90000 + +#define WCSS_TOP_CMN_BASE 0x00ba0000 +#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 +#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 + +#define MSIP_BASE 0x00bb0000 +#define MSIP_BASE_SIZE 0x00010000 +#define MSIP_BASE_PHYS 0x00bb0000 + +#define DBG_BASE 0x01000000 +#define DBG_BASE_SIZE 0x00100000 +#define DBG_BASE_PHYS 0x01000000 + +#define Q6SS_WLAN_BASE 0x01100000 +#define Q6SS_WLAN_BASE_SIZE 0x00100000 +#define Q6SS_WLAN_BASE_PHYS 0x01100000 + +#endif diff --git a/hw/peach/v2/wcss_seq_hwioreg_umac.h b/hw/peach/v2/wcss_seq_hwioreg_umac.h new file mode 100644 index 000000000000..a4e3d3bf3738 --- /dev/null +++ b/hw/peach/v2/wcss_seq_hwioreg_umac.h @@ -0,0 +1,2264 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ +#define __WCSS_SEQ_HWIOREG_UMAC_H__ + +#include "seq_hwio.h" +#include "wcss_seq_hwiobase.h" +#ifdef SCALE_INCLUDES +#include "HALhwio.h" +#else +#include "msmhwio.h" +#endif + +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x7c) +#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90) +#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x4b +#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040 +#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3 +#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x)) +#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m) +#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v) +#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x)) +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x27c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 + +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) +#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x66666a98 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ + in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 + +#define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x68) +#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x518) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x524) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x578) +#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0xb24) +#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0xb24) +#define HWIO_REO_R0_MISC_CFG_OFFS (0xb24) +#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 +#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 +#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 +#define HWIO_REO_R0_MISC_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) +#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) +#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) +#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) +#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 +#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 + +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb38) +#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xba0) +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0xd88) +#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0xd88) +#define HWIO_REO_R0_CREDIT_OFFS (0xd88) +#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_POR 0x00000000 +#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_ATTR 0x3 +#define HWIO_REO_R0_CREDIT_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) +#define HWIO_REO_R0_CREDIT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_OUT(x, v) \ + out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) +#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) +#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 + +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ + out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 + +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 +#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 +#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 + +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 + +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ + in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ + out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 + +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8) +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 +#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf +#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ + in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 +#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ + in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 + +#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 + +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f +#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) +#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff +#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 +#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) +#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 + +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 + +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ + in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 + +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ + in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ + out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 + +#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 27 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x10 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 4 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 + +#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 +#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x928) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x934) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x938) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x964) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x968) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff +#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_SHFT 17 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#endif diff --git a/hw/peach/v2/wcss_version.h b/hw/peach/v2/wcss_version.h new file mode 100644 index 000000000000..a8f986a7d7fd --- /dev/null +++ b/hw/peach/v2/wcss_version.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#define WCSS_VERSION V1_7 From c068c23f01bc2332955375641f4cc670fa983fe3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 19 Dec 2023 18:01:17 -0800 Subject: [PATCH 36/74] fw-api: CL 25652231 - update fw common interface files add WMI_ROAM_PARAM_CRYPTO_EHT_CONFIG def Change-Id: Ib4cca9841703640c42bca83fcb32dde6e66b4d01 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 43 +++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ac9342cd35e7..55c0a4e15088 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -40795,9 +40795,52 @@ typedef enum { */ WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE = 9, + /* + * crypto params to allow EHT/MLO in WPA2/WPA3 security. + * BITMAP of wlan_crypto_roam_eht_config + */ + WMI_ROAM_PARAM_CRYPTO_EHT_CONFIG = 10, + + /*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/ } WMI_ROAM_PARAM; +typedef enum { + /* + * BIT 0 - WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT: + * Connect to non-MLO/MLO WPA2 EHT APs in EHT without MLO + * (PMF capable is not mandatory). + * + * BIT 1 - WLAN_CRYPTO_WPA2_ALLOW_MLO: + * Connect to MLO WPA2 EHT APs in MLO + * (PMF capable is not mandatory). + * If set along with WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT (BIT 0), + * this mode supercedes. + * + * BIT 2 - WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT_MFPC_SET: + * Connect to non-MLO/MLO WPA2 EHT APs in EHT without MLO + * (PMF capable is mandatory). + * + * BIT 3 - WLAN_CRYPTO_WPA2_ALLOW_MLO_MFPC_SET: + * Connect to MLO WPA2 EHT APs in MLO + * (PMF capable is mandatory). + * If set along with WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT_MFPC_SET + * (BIT 2), this mode supercedes. + * + * BIT 4 - 15 - reserved for future WPA2 security configs + * + * BIT 16 - WLAN_CRYPTO_WPA3_SAE_ALLOW_NON_MLO_EHT_HNP: + * Connect to non-MLO/MLO WPA3-SAE without support for H2E + * (or no RSNXE IE in beacon) in non-MLO EHT. + */ + WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT = 0x00000001, + WLAN_CRYPTO_WPA2_ALLOW_MLO = 0x00000002, + WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT_MFPC_SET = 0x00000004, + WLAN_CRYPTO_WPA2_ALLOW_MLO_MFPC_SET = 0x00000008, + + WLAN_CRYPTO_WPA3_SAE_ALLOW_NON_MLO_EHT_HNP = 0x00010000, +} wlan_crypto_roam_eht_config; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_big_data_cmd_fixed_param */ A_UINT32 vdev_id; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 3ba4c9227c65..977861676d3b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1431 +#define __WMI_REVISION_ 1432 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 8004f23eaf64e85724bfb53d8efc25b5bd18d0b2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 20 Dec 2023 18:01:20 -0800 Subject: [PATCH 37/74] fw-api: CL 25663374 - update fw common interface files Add OBSS interference info in DCS_INTERFERENCE_EVENT msg Change-Id: I157d83ca5083e5fa14ff978d73e943a046d19f9f CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 35 ++++++++++++++++++++++++++++++++--- fw/wmi_version.h | 2 +- 4 files changed, 37 insertions(+), 5 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 1890f9182450..a5d07510af2b 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -652,6 +652,7 @@ typedef enum { WMI_SERVICE_VDEV_DCS_STATS_SUPPORT = 399, /* FW supports VDEV level DCS stats reporting */ WMI_SERVICE_WIFI_RADAR_SUPPORT = 400, /* FW supports wifi radar */ WMI_SERVICE_P2P_DEVICE_UPDATE_MAC_ADDR_SUPPORT = 401, /* indicate FW support dynamic update mac address for P2P device */ + WMI_SERVICE_DCS_OBSS_INT_SUPPORT = 402, /* Indicates FW supports OBSS Interference detection */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index ba7225dd062d..e82fe38a5241 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1425,6 +1425,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_pdev_enable_wifi_radar_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_dma_buf_release_wifi_radar_meta_data, WMITLV_TAG_STRUC_wmi_mlo_link_info, + WMITLV_TAG_STRUC_wmi_dcs_obss_int_t, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -6059,7 +6060,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GTK_OFFLOAD_STATUS_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param, wmi_dcs_interference_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_cw_int, cw_int, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_im_tgt_stats_t, wlan_stat, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcs_awgn_int_t, awgn_int, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcs_awgn_int_t, awgn_int, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcs_obss_int_t, obss_int, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DCS_INTERFERENCE_EVENTID); /* Profile data Event */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 55c0a4e15088..35155da1c10f 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -21300,6 +21300,32 @@ typedef struct wlan_dcs_awgn_info { A_UINT32 chan_bw_interference_bitmap; } wmi_dcs_awgn_int_t; +typedef struct wlan_dcs_obss_info { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dcs_obss_int_t */ + A_UINT32 tlv_header; + /** Channel width (20, 40, 80, 80+80, 160, 320) enum wmi_channel_width */ + A_UINT32 channel_width; + /** Primary channel frequency (MHz) */ + A_UINT32 chan_freq; + /** center frequency (MHz) first segment */ + A_UINT32 center_freq0; + /** center frequency (MHz) second segment */ + A_UINT32 center_freq1; + /* chan_bw_interference_bitmap: + * Indicates which 20MHz segments contain interference + * 320 MHz: bits 0-15 + * 160 MHz: bits 0-7 + * 80 MHz: bits 0-3 + * Within the bitmap, Bit-0 represents lowest 20Mhz, Bit-1 represents + * second lowest 20Mhz and so on. + * Each bit position will indicate 20MHz in which interference is seen. + * (Valid 16 bits out of 32 bit integer) + * Note: for 11be, the interference present 20MHz can be punctured + * for better channel utilization. + */ + A_UINT32 chan_bw_interference_bitmap; +} wmi_dcs_obss_int_t; + /** * wmi_dcs_interference_event_t * @@ -21316,6 +21342,8 @@ typedef struct { * ATH_CAP_DCS_CWIM 0x01 * ATH_CAP_DCS_WLANIM 0x02 * ATH_CAP_DCS_AGWNIM 0x04 + * reserved (AFC) 0x08 + * ATH_CAP_DCS_OBSSIM 0x10 */ A_UINT32 interference_type; /* type of interference, wlan, cw, or AWGN */ /** pdev_id for identifying the MAC @@ -21336,7 +21364,8 @@ typedef struct { * * wlan_dcs_cw_int cw_int[]; <-- cw_interference event * wlan_dcs_im_tgt_stats_t wlan_stat[]; <-- wlan im interference stats - * wmi_dcs_awgn_int_t awgn_int[]; <-- Additive white Gaussian noise (awgn) interference + * wmi_dcs_awgn_int_t awgn_int[]; <-- Additive white Gaussian noise (AWGN) interference + * wmi_dcs_obss_int_t obss_int[]; <-- Overlapping Basic Service Set (OBSS) interference */ } wmi_dcs_interference_event_fixed_param; @@ -37699,8 +37728,8 @@ typedef struct { * This fixed_param TLV is followed by the following TLVs: * - wmi_regulatory_rule_ext reg_rule_array[] struct TLV array. * Within the reg rule ext TLV array, the 2G elements occur first, - * then the 5G elements, then the 6G elements (AP SG, AP LPI, AP VLP, - * client SP x4, client LPI x4, client vlp x4). + * then the 5G elements, then the 6G elements (AP LPI, AP SP, AP VLP, + * client LPI x4, client SP x4, client VLP x4). * - wmi_regulatory_chan_priority_struct reg_chan_priority[] * - wmi_regulatory_fcc_rule_struct reg_fcc_rule[] */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 977861676d3b..f01f099b6252 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1432 +#define __WMI_REVISION_ 1433 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 29898cf52694cfa3da18f10d941e9997086b3c90 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 21 Dec 2023 18:01:23 -0800 Subject: [PATCH 38/74] fw-api: CL 25672910 - update fw common interface files WMI: add PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENT msg def Change-Id: I08e6f2edb544a0fc336438c5386c619ac731fa27 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 7 +++++++ fw/wmi_unified.h | 51 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index e82fe38a5241..03cf0288cd53 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1426,6 +1426,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_dma_buf_release_wifi_radar_meta_data, WMITLV_TAG_STRUC_wmi_mlo_link_info, WMITLV_TAG_STRUC_wmi_dcs_obss_int_t, + WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cal_completion_status_event_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -2290,6 +2291,7 @@ typedef enum { OP(WMI_VDEV_SCHED_MODE_PROBE_RESP_EVENTID) \ OP(WMI_VDEV_OOB_CONNECTION_RESP_EVENTID) \ OP(WMI_AUDIO_TRANSPORT_SWITCH_TYPE_EVENTID) \ + OP(WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -7587,6 +7589,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SCHED_MODE_PROBE_RESP_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_oob_connection_resp_event_fixed_param, wmi_vdev_oob_connection_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_OOB_CONNECTION_RESP_EVENTID); +/* WiFi Radar calibration status event */ +#define WMITLV_TABLE_WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cal_completion_status_event_param, wmi_pdev_wifi_radar_cal_completion_status_event_param, cal_completion_status_event_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID); + #ifdef __cplusplus diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 35155da1c10f..ff2af76aa9ff 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1780,6 +1780,9 @@ typedef enum { /* Event to get AOA phasedelta values for all gain tables from HALPHY */ WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, + /* Event to indicate the status of WiFi Radar calibration */ + WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID, + /* VDEV specific events */ /** VDEV started event in response to VDEV_START request */ WMI_VDEV_START_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VDEV), @@ -47712,6 +47715,54 @@ typedef struct { A_UINT32 capture_interval_ms; } wmi_pdev_enable_wifi_radar_cmd_fixed_param; +#define WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_GET(cal_status_array, txchnIdx, rxchnIdx) WMI_GET_BITS(*(cal_status_array + txchnIdx), rxchnIdx, 1) +#define WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_SET(cal_status_array, txchnIdx, rxchnIdx, value) WMI_SET_BITS(*(cal_status_array + txchnIdx), rxchnIdx, 1, value) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_wifi_radar_cal_configuration + */ + A_UINT32 tlv_header; + /* ID of pdev for which the calibration is completed */ + A_UINT32 pdev_id; + /* Packet bandwidth of WiFi Radar packet used for calibration + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + */ + A_UINT32 wifi_radar_pkt_bw; + /* Channel bandwidth + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + */ + A_UINT32 channel_bw; + /* Channel Center frequency in MHz */ + A_UINT32 band_center_freq; + /* Number of LTF configured in the WiFi Radar Tx packet during calibration */ + A_UINT32 num_ltf_tx; + /* Number of LTF skipped during Rx of the calibration packet */ + A_UINT32 num_skip_ltf_rx; + /* Number of LTF accumulated during Rx of the calibration packet */ + A_UINT32 num_ltf_accumulation; + /* Calibration status for each chain combination + * Word 0: tx chain 0 cal statuses: + * Bit 0: rx chain 0 cal status + * Bit 1: rx chain 1 cal status + * etc. + * Word 1: tx chain 1 cal statuses: + * Bit 0: rx chain 0 cal status + * Bit 1: rx chain 1 cal status + * etc. + * etc. + * Cal status values: success = 1, Failure = 0 + */ + A_UINT32 per_chain_cal_status[WMI_MAX_CHAINS]; +} wmi_pdev_wifi_radar_cal_completion_status_event_param; /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index f01f099b6252..e0081d3c833a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1433 +#define __WMI_REVISION_ 1434 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 69a064644176735171c007f8ea4d6f155b173663 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 28 Dec 2023 18:01:32 -0800 Subject: [PATCH 39/74] fw-api: CL 25682638 - update fw common interface files WMI: add sbs_mid_band_end_freq field in dbs_or_sbs_cap_ext struct Change-Id: I4b2e48371ef302f9eb9fbb6953ab620eece02e89 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 ++++++- fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ff2af76aa9ff..861f94cbcd09 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -45984,9 +45984,14 @@ typedef struct { /* * If sbs_lower_band_end_freq is set to non-zero, it indicates * async SBS mode is supported, and lower-band/higher band to MAC - * mapping is switch-able. unit: mhz. examples 5180, 5320 + * mapping is switch-able. unit: MHz. examples 5180, 5320 + * If sbs_mid_band_end_freq is set to non-zero, it indicates + * async flexible SBS mode is supported, lower/higher band cutoff frequency + * can be selected from sbs_lower_band_end_freq or sbs_mid_band_end_freq. + * unit: MHz, examples 5900. */ A_UINT32 sbs_lower_band_end_freq; + A_UINT32 sbs_mid_band_end_freq; } wmi_dbs_or_sbs_cap_ext; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index e0081d3c833a..9ffa83cfc750 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1434 +#define __WMI_REVISION_ 1435 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From aad5323bf436fcbc8a6e5a846ed31a7acbe052c9 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 28 Dec 2023 18:02:36 -0800 Subject: [PATCH 40/74] fw-api: CL 25706687 - update fw common interface files WMI: add SAR flags in READY_EXT2_EVENT msg Change-Id: Icfa99bd0c4aa7b6751094f1b9c1ad7e381c7b131 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 13 +++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 03cf0288cd53..f45980d0c8a9 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1427,6 +1427,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mlo_link_info, WMITLV_TAG_STRUC_wmi_dcs_obss_int_t, WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cal_completion_status_event_param, + WMITLV_TAG_STRUC_wmi_sar_flags, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -5628,7 +5629,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sar_flags, wmi_sar_flag_tlv_param, sar_flags, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID); #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 861f94cbcd09..ce0604673203 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -36276,6 +36276,19 @@ typedef struct { **************************************************************************/ } WMI_SAR_CAPABILITIES; +typedef enum { + WMI_SAR_FLAG_NONE = 0, + WMI_SAR_SET_CTL_GROUPING_DISABLE, + WMI_SAR_DBS_WITH_BT_DISABLE, + WMI_SAR_FLAG_MAX, +} wmi_sar_flags; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sar_flags*/ + /* sar flags in bdf */ + A_UINT32 sar_flags; /* refer to enum wmi_sar_flags */ +} wmi_sar_flag_tlv_param; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_parameters_tlv */ /** global default adaptive dwell mode, used when WMI_SCAN_DWELL_MODE_DEFAULT */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9ffa83cfc750..8a5f73308da1 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1435 +#define __WMI_REVISION_ 1436 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 4dca93b098f887866efce2eff61da7729e26f7b4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 28 Dec 2023 18:03:43 -0800 Subject: [PATCH 41/74] fw-api: CL 25706940 - update fw common interface files HTT stats: add ofdma_seq_flush counter in tx_pdev_cmn TLV struct Change-Id: Id903d4d0e68fb259e55d65ad6b8b29437fc0e284 CRs-Fixed: 2262693 --- fw/htt_stats.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 821753e011d2..5018aa88b809 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -992,6 +992,8 @@ typedef struct { /** pdev uptime in microseconds **/ A_UINT32 pdev_up_time_us_low; A_UINT32 pdev_up_time_us_high; + /** count of ofdma sequences flushed */ + A_UINT32 ofdma_seq_flush; } htt_stats_tx_pdev_cmn_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv; From 67b196d1b5bfb6c813fa429474f5c48bf51d602b Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 2 Jan 2024 18:01:10 -0800 Subject: [PATCH 42/74] fw-api: CL 25722609 - update fw common interface files WMI: add mlo_bridge_link in wmi_mlo_flags struct Change-Id: I2aeb4ab1741599f197980ccb709508c7f7d4b493 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 5 +++-- fw/wmi_version.h | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ce0604673203..059b698ee0b2 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -16238,7 +16238,8 @@ typedef struct { */ nstr_bitmap_size:1, mlo_link_switch: 1, /* indicate the command is a part of link switch procedure */ - unused: 18; + mlo_bridge_link:1, /* indicate link is bridge link */ + unused: 17; }; A_UINT32 mlo_flags; }; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 8a5f73308da1..80803e3f2291 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1436 +#define __WMI_REVISION_ 1437 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 3e97faa4522f44e100a4080b79d2510831ae39bc Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 4 Jan 2024 12:02:39 -0800 Subject: [PATCH 43/74] fw-api: CL 25734374 - update fw common interface files HTT stats: modify latency_prof_cal_stats struct Change-Id: Id5df11299388b367101eb38bd52b2941c87fc348 CRs-Fixed: 2262693 --- fw/htt.h | 3 +- fw/htt_stats.h | 78 +++++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 76 insertions(+), 5 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 3aeba5a65602..96c8f1e7e603 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -790,7 +790,7 @@ typedef enum { HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, /* htt_pdev_sched_algo_ofdma_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_pdev_sched_algo_ofdma_stats */ HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, /* htt_odd_mandatory_mumimo_pdev_stats_tlv */ HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, /* htt_odd_mandatory_muofdma_pdev_stats_tlv */ - HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv */ + HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv - DEPRECATED */ HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v - DEPRECATED */ HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */ HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v, TOPIC=advanced */ @@ -815,6 +815,7 @@ typedef enum { HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */ HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */ HTT_STATS_WHAL_WSI_TAG = 192, /* htt_stats_whal_wsi_tlv */ + HTT_STATS_LATENCY_PROF_CAL_DATA_TAG = 193, /* htt_stats_latency_prof_cal_data_tlv */ HTT_STATS_MAX_TAG, diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 5018aa88b809..eda2748aa6fd 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -500,7 +500,7 @@ enum htt_dbg_ext_stats_type { * params: * None * Response MSG: - * htt_latency_prof_cal_stats_tlv + * htt_stats_latency_prof_cal_data_tlv */ HTT_DBG_EXT_PHY_PROF_CAL_STATS = 52, @@ -8726,7 +8726,7 @@ enum { }; #define HTT_STATS_MAX_CAL_IDX_CNT 8 -typedef struct { +typedef struct { /* DEPRECATED */ htt_tlv_hdr_t tlv_hdr; @@ -8781,9 +8781,77 @@ typedef struct { /** No of indices invoked per each cal profile */ A_UINT32 CalCnt[HTT_STATS_MAX_PROF_CAL]; -} htt_stats_latency_prof_cal_stats_tlv; +} htt_stats_latency_prof_cal_stats_tlv; /* DEPRECATED */ /* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_latency_prof_cal_stats_tlv htt_latency_prof_cal_stats_tlv; +typedef htt_stats_latency_prof_cal_stats_tlv htt_latency_prof_cal_stats_tlv; /* DEPRECATED */ + +typedef struct { + /** The cnt is incremented when each time the calindex takes place */ + A_UINT32 cnt; + + /** Minimum time taken to complete the calibration - in us */ + A_UINT32 min; + + /** Maximum time taken to complete the calibration -in us */ + A_UINT32 max; + + /** Time taken by the cal for its final time execution - in us */ + A_UINT32 last; + + /** Total time taken - in us */ + A_UINT32 tot; + + /** hist_intvl - in us, by default will be set to 2000 us */ + A_UINT32 hist_intvl; + + /** + * If last is less than hist_intvl, then hist[0]++, + * If last is less than hist_intvl << 1, then hist[1]++, + * otherwise hist[2]++. + */ + A_UINT32 hist[HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; + + /** pf_last will log the current no of page faults */ + A_UINT32 pf_last; + + /** Sum of all page faults happened */ + A_UINT32 pf_tot; + + /** If pf_last > pf_max then pf_max = pf_last */ + A_UINT32 pf_max; + + /** + * For each cal profile, only certain no of cal indices were invoked, + * this member will store what all the indices got invoked per each + * cal profile + */ + A_UINT32 enabled_cal_idx; + +/* + * NOTE: due to backwards-compatibility requirements, + * no fields can be added to this struct. + */ +} htt_stats_latency_prof_cal_data; + +typedef struct { + + htt_tlv_hdr_t tlv_hdr; + + /** To verify whether prof cal is enabled or not */ + A_UINT32 enable; + + /** current pdev_id */ + A_UINT32 pdev_id; + + /** No of indices invoked per each cal profile */ + A_UINT32 cal_cnt[HTT_STATS_MAX_PROF_CAL]; + + /** Latency Cal Profile name */ + A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_PROF_STATS_NAME_LEN]; + + /** Latency Cal data */ + htt_stats_latency_prof_cal_data latency_data[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; +} htt_stats_latency_prof_cal_data_tlv; #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M 0x0000003F #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S 0 @@ -10508,6 +10576,7 @@ typedef enum { HTT_CTRL_PATH_STATS_CAL_TYPE_PEF = 0x16, HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17, HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXSPUR = 0x19, /* add new cal types above this line */ HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF @@ -10556,6 +10625,7 @@ static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF); HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP); HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXSPUR); } return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN"; From dd915129e5a07c7c745e5b7509490540591832a2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 4 Jan 2024 12:03:49 -0800 Subject: [PATCH 44/74] fw-api: CL 25734378 - update fw common interface files add WLAN_CRYPTO_WPA3_SAE_ALLOW_MLO_HNP def Change-Id: I6ac612128a70ddd56f08fdae12c0959f3160daa6 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 18 +++++++++--------- fw/wmi_version.h | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 059b698ee0b2..d96feef59a2f 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -37316,6 +37316,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_COEX_MULTIPLE_CONFIG_CMDID); WMI_RETURN_STRING(WMI_PDEV_ENABLE_LED_BLINK_DOWNLOAD_TABLE_CMDID); WMI_RETURN_STRING(WMI_PDEV_ENABLE_WIFI_RADAR_CMDID); + WMI_RETURN_STRING(WMI_VDEV_GET_TWT_SESSION_STATS_INFO_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -40854,30 +40855,28 @@ typedef enum { typedef enum { /* * BIT 0 - WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT: - * Connect to non-MLO/MLO WPA2 EHT APs in EHT without MLO - * (PMF capable is not mandatory). + * Connect to non-MLO/MLO WPA2 EHT APs in EHT without PMF support. * * BIT 1 - WLAN_CRYPTO_WPA2_ALLOW_MLO: - * Connect to MLO WPA2 EHT APs in MLO - * (PMF capable is not mandatory). - * If set along with WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT (BIT 0), - * this mode supercedes. + * Connect to MLO WPA2 EHT APs in MLO without PMF support. * * BIT 2 - WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT_MFPC_SET: - * Connect to non-MLO/MLO WPA2 EHT APs in EHT without MLO + * Connect to non-MLO/MLO WPA2 EHT APs in EHT. * (PMF capable is mandatory). * * BIT 3 - WLAN_CRYPTO_WPA2_ALLOW_MLO_MFPC_SET: * Connect to MLO WPA2 EHT APs in MLO * (PMF capable is mandatory). - * If set along with WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT_MFPC_SET - * (BIT 2), this mode supercedes. * * BIT 4 - 15 - reserved for future WPA2 security configs * * BIT 16 - WLAN_CRYPTO_WPA3_SAE_ALLOW_NON_MLO_EHT_HNP: * Connect to non-MLO/MLO WPA3-SAE without support for H2E * (or no RSNXE IE in beacon) in non-MLO EHT. + * + * BIT 17 - WLAN_CRYPTO_WPA3_SAE_ALLOW_MLO_HNP: + * Connect to MLO WPA3-SAE without support for H2E + * (or no RSNXE IE in beacon). */ WLAN_CRYPTO_WPA2_ALLOW_NON_MLO_EHT = 0x00000001, WLAN_CRYPTO_WPA2_ALLOW_MLO = 0x00000002, @@ -40885,6 +40884,7 @@ typedef enum { WLAN_CRYPTO_WPA2_ALLOW_MLO_MFPC_SET = 0x00000008, WLAN_CRYPTO_WPA3_SAE_ALLOW_NON_MLO_EHT_HNP = 0x00010000, + WLAN_CRYPTO_WPA3_SAE_ALLOW_MLO_HNP = 0x00020000, } wlan_crypto_roam_eht_config; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 80803e3f2291..9f53a54e2b2e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1437 +#define __WMI_REVISION_ 1438 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From e0061fdcebb342dc50dc5659921b41da3f07f474 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 5 Jan 2024 06:01:29 -0800 Subject: [PATCH 45/74] fw-api: CL 25739385 - update fw common interface files WMI: change vdev_ch_power from dB units to 0.25 dB units Change-Id: I1892118dc734aa33d15286c0b4c4e82629ad5569 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 13 +++++++++++-- fw/wmi_version.h | 2 +- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d96feef59a2f..c13cdf7c0d07 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -41078,13 +41078,22 @@ typedef struct { typedef struct { A_UINT32 tlv_header; A_UINT32 chan_cfreq; /* Channel center frequency (MHz) of all BSS Sub-channel */ - A_INT32 psd_power; /* Unit: dBm/MHz, OOBE PSD power of sub-channel */ + /* psd_power: + * Unit: 0.25dBm/MHz, OOBE PSD power of sub-channel + * Example: a power spectral density of 1 dBm / MHz will be reported + * as the value 4. + */ + A_INT32 psd_power; } wmi_vdev_ch_power_psd_info; typedef struct { A_UINT32 tlv_header; A_UINT32 chan_cfreq; /* Channel center frequency (MHz) for all BWs (<= current channel BSS BW) */ - A_INT32 eirp_power; /* Unit: dBm, EIRP power for all BWs (<= current channel BSS BW) */ + /* eirp_power: + * Unit: 0.25dBm, EIRP power for all BWs (<= current channel BSS BW) + * Example: a power of 1 dBm will be reported as the value 4. + */ + A_INT32 eirp_power; } wmi_vdev_ch_power_eirp_info; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9f53a54e2b2e..ff5d091f6781 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1438 +#define __WMI_REVISION_ 1439 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 303bcd67ad0538dc5795349f64dbd13d231c025e Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 6 Jan 2024 06:01:52 -0800 Subject: [PATCH 46/74] fw-api: CL 25746138 - update fw common interface files WMI: change variable-length arrays to not use [0] or [1] Modify defs of WMI TLV structs that have variable-length arrays of the form type name[0]; or type name[1]; to instead have type name[];, while ensuring the size of the TLV struct remains unchanged. Change-Id: I43e03ec0e426be4732cc1bded837fb5aaad36756 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 50 ++++++++++++++++++++++++++++++++++++++++-------- fw/wmi_version.h | 2 +- 2 files changed, 43 insertions(+), 9 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index c13cdf7c0d07..8d018a90e6ee 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -77,6 +77,40 @@ extern "C" { */ #include +/* WMI_VAR_LEN_ARRAY1: + * This macro is for converting the definition of existing variable-length + * arrays within TLV structs of the form "type name[1];" to use the form + * "type name[];" while ensuring that the length of the TLV struct is + * unmodified by the conversion. + * In general, any new variable-length structs should simply use + * "type name[];" directly, rather than using WMI_VAR_LEN_ARRAY1. + * However, if there's a legitimate reason to make the new variable-length + * struct appear to not have a variable length, WMI_VAR_LEN_ARRAY1 can be + * used for this purpose. + */ +#if !defined(__KERNEL__) + #define WMI_DUMMY_ZERO_LEN_FIELD A_UINT32 dummy_zero_len_field[0] +#else + /* + * Certain build settings of the Linux kernel don't allow zero-element + * arrays, and C++ doesn't allow zero-length empty structs. + * Confirm that there's no build that combines kernel with C++. + */ + #ifdef __cplusplus + #error unsupported combination of kernel and C plus plus + #endif + #define WMI_DUMMY_ZERO_LEN_FIELD struct {} dummy_zero_len_field +#endif + +#define WMI_VAR_LEN_ARRAY1(type, name) \ + union { \ + type name ## __first_elem; \ + struct { \ + WMI_DUMMY_ZERO_LEN_FIELD; \ + type name[]; \ + }; \ + } + #define ATH_MAC_LEN 6 /**< length of MAC in bytes */ #define WMI_EVENT_STATUS_SUCCESS 0 /* Success return status to host */ #define WMI_EVENT_STATUS_FAILURE 1 /* Failure return status to host */ @@ -3701,7 +3735,7 @@ typedef struct { /* bad channel range count, multi range is allowed, 0 means all channel clear */ A_UINT32 num_freq_ranges; /* multi range with num_freq_ranges, LTE advance multi carrier, CDMA,etc */ - avoid_freq_range_desc avd_freq_range[0]; + avoid_freq_range_desc avd_freq_range[]; } wmi_wlan_avoid_freq_ranges_event; #endif @@ -5541,7 +5575,7 @@ typedef struct { /** # of channels to scan */ A_UINT32 num_chan; /** channels in Mhz */ - A_UINT32 channel_list[1]; + WMI_VAR_LEN_ARRAY1(A_UINT32, channel_list); } wmi_chan_list; /** @@ -5553,7 +5587,7 @@ typedef struct { /** number of bssids */ A_UINT32 num_bssid; /** bssid list */ - wmi_mac_addr bssid_list[1]; + WMI_VAR_LEN_ARRAY1(wmi_mac_addr, bssid_list); } wmi_bssid_list; /** @@ -5565,7 +5599,7 @@ typedef struct { /** number of bytes in ie data */ A_UINT32 ie_len; /** ie data array (ie_len adjusted to number of words (ie_len + 4)/4) */ - A_UINT32 ie_data[1]; + WMI_VAR_LEN_ARRAY1(A_UINT32, ie_data); } wmi_ie_data; /** @@ -5629,7 +5663,7 @@ typedef struct { /** WMI_SSID_LIST_TAG */ A_UINT32 tag; A_UINT32 num_ssids; - wmi_ssid ssids[1]; + WMI_VAR_LEN_ARRAY1(wmi_ssid, ssids); } wmi_ssid_list; typedef struct { @@ -5638,7 +5672,7 @@ typedef struct { /** Number of start TSF offsets */ A_UINT32 num_offset; /** Array of start TSF offsets provided in milliseconds */ - A_UINT32 start_tsf_offset[1]; + WMI_VAR_LEN_ARRAY1(A_UINT32, start_tsf_offset); } wmi_scan_start_offset; /** @@ -7046,7 +7080,7 @@ typedef struct { /** Phy error event header */ wmi_single_phyerr_rx_hdr hdr; /** frame buffer */ - A_UINT8 bufp[1]; + WMI_VAR_LEN_ARRAY1(A_UINT8, bufp); } wmi_single_phyerr_rx_event; /* PHY ERROR MASK 0 */ @@ -22329,7 +22363,7 @@ typedef struct wmi_bcn_send_from_host { /* cmd to support bcn snd for all vaps at once */ typedef struct wmi_pdev_send_bcn { A_UINT32 num_vdevs; - wmi_bcn_send_from_host_cmd_fixed_param bcn_cmd[1]; + WMI_VAR_LEN_ARRAY1(wmi_bcn_send_from_host_cmd_fixed_param, bcn_cmd); } wmi_pdev_send_bcn_cmd_t; typedef struct wmi_fd_send_from_host { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index ff5d091f6781..feaef7c7077a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1439 +#define __WMI_REVISION_ 1440 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From bf0859d5330d2f529f63a3fb8e025b5a6535014c Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 11 Jan 2024 06:01:35 -0800 Subject: [PATCH 47/74] fw-api: CL 25775134 - update fw common interface files HTT stats: add pdev RTT stats Change-Id: I415fa2f884330167f9a51f53f4f04f0bdb7f6a3f CRs-Fixed: 2262693 --- fw/htt.h | 5 + fw/htt_stats.h | 535 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 540 insertions(+) diff --git a/fw/htt.h b/fw/htt.h index 96c8f1e7e603..e0de862d594b 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -816,6 +816,11 @@ typedef enum { HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */ HTT_STATS_WHAL_WSI_TAG = 192, /* htt_stats_whal_wsi_tlv */ HTT_STATS_LATENCY_PROF_CAL_DATA_TAG = 193, /* htt_stats_latency_prof_cal_data_tlv */ + HTT_STATS_PDEV_RTT_RESP_STATS_TAG = 194, /* htt_stats_pdev_rtt_resp_stats_tlv */ + HTT_STATS_PDEV_RTT_INIT_STATS_TAG = 195, /* htt_stats_pdev_rtt_init_stats_tlv */ + HTT_STATS_PDEV_RTT_HW_STATS_TAG = 196, /* htt_stats_pdev_rtt_hw_stats_tlv */ + HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG = 197, /* htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv */ + HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG = 198, /* htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv */ HTT_STATS_MAX_TAG, diff --git a/fw/htt_stats.h b/fw/htt_stats.h index eda2748aa6fd..9f15c384519b 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -599,6 +599,26 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_PDEV_MLO_IPC_STATS = 64, + /** HTT_DBG_EXT_PDEV_RTT_RESP_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_stats_pdev_rtt_resp_stats_tlv + * - htt_stats_pdev_rtt_hw_stats_tlv + * - htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv + * - htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv + */ + HTT_DBG_EXT_PDEV_RTT_RESP_STATS = 65, + + /** HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_stats_pdev_rtt_init_stats_tlv + * - htt_stats_pdev_rtt_hw_stats_tlv + */ + HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS = 66, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -7842,6 +7862,521 @@ typedef struct { htt_stats_vdev_rtt_init_stats_tlv vdev_rtt_init_stats; } htt_vdev_rtt_init_stats_t; + +#define HTT_STATS_MAX_SCH_CMD_RESULT 25 + +/* TXSEND self generated frames */ +typedef enum { + HTT_TXSEND_FTYPE_SGEN_TF_POLL, + HTT_TXSEND_FTYPE_SGEN_TF_SOUND, + HTT_TXSEND_FTYPE_SGEN_TBR_NDPA, + HTT_TXSEND_FTYPE_SGEN_TBR_NDP, + HTT_TXSEND_FTYPE_SGEN_TBR_LMR, + HTT_TXSEND_FTYPE_SGEN_TF_REPORT, + + HTT_TXSEND_FTYPE_MAX +} +htt_stats_txsend_ftype_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* 11AZ TBR SU Stats */ + A_UINT32 tbr_su_ftype_queued[HTT_TXSEND_FTYPE_MAX]; + /* 11AZ TBR MU Stats */ + A_UINT32 tbr_mu_ftype_queued[HTT_TXSEND_FTYPE_MAX]; +} htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /** tbr_num_sch_cmd_result_buckets: + * Number of sch cmd results buckets in use per chip + * Each bucket contains the counter of the number of times that bucket + * index was seen in the sch_cmd_result. The last bucket will capture + * the count of sch_cmd_result matching the last bucket index and the + * count of all the sch_cmd_results that exceeded the last bucket index + * value. + * tbr_num_sch_cmd_result_buckets must be <= HTT_STATS_MAX_SCH_CMD_RESULT + */ + A_UINT32 tbr_num_sch_cmd_result_buckets; + /* cmd result status for SU frames in case of TB ranging */ + A_UINT32 opaque_tbr_su_ftype_cmd_result[HTT_TXSEND_FTYPE_MAX][HTT_STATS_MAX_SCH_CMD_RESULT]; + /* cmd result status for MU frames in case of TB ranging */ + A_UINT32 opaque_tbr_mu_ftype_cmd_result[HTT_TXSEND_FTYPE_MAX][HTT_STATS_MAX_SCH_CMD_RESULT]; +} htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /** ista_ranging_ndpa_cnt: + * Indicates the number of Ranging NDPA sent successfully. + */ + A_UINT32 ista_ranging_ndpa_cnt; + /** ista_ranging_ndp_cnt: + * Indicates the number of Ranging NDP sent successfully. + */ + A_UINT32 ista_ranging_ndp_cnt; + /** ista_ranging_i2r_lmr_cnt: + * Indicates the number of Ranging I2R LMR sent successfully. + */ + A_UINT32 ista_ranging_i2r_lmr_cnt; + /** rtsa_ranging_resp_cnt + * Indicates the number of times RXPCU initiates a Ranging response + * as a RSTA. + */ + A_UINT32 rtsa_ranging_resp_cnt; + /** rtsa_ranging_ndp_cnt: + * Indicates the number of Ranging NDP response sent successfully. + */ + A_UINT32 rtsa_ranging_ndp_cnt; + /** rsta_ranging_lmr_cnt: + * Indicates the number of Ranging R2I LMR response sent successfully. + */ + A_UINT32 rsta_ranging_lmr_cnt; + /** tb_ranging_cts2s_rcvd_cnt: + * Indicates the number of expected CTS2S response received for TF Poll + * sent. + */ + A_UINT32 tb_ranging_cts2s_rcvd_cnt; + /** tb_ranging_ndp_rcvd_cnt: + * Indicates the number of expected NDP response received for TF Sound + * or Secure Sound sent. + */ + A_UINT32 tb_ranging_ndp_rcvd_cnt; + /** tb_ranging_lmr_rcvd_cnt: + * Indicates the number of expected LMR response received for TF Report + * sent. + */ + A_UINT32 tb_ranging_lmr_rcvd_cnt; + /** tb_ranging_tf_poll_resp_sent_cnt: + * Indicates the number of successful responses sent for TF Poll + * received. + */ + A_UINT32 tb_ranging_tf_poll_resp_sent_cnt; + /** tb_ranging_tf_sound_resp_sent_cnt: + * Indicates the number of successful responses sent for TF Sound + * (or Secure) received. + */ + A_UINT32 tb_ranging_tf_sound_resp_sent_cnt; + /** tb_ranging_tf_report_resp_sent_cnt: + * Indicates the number of successful responses sent for TF Report + * received. + */ + A_UINT32 tb_ranging_tf_report_resp_sent_cnt; +} htt_stats_pdev_rtt_hw_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 pdev_id; + /** tx_11mc_ftm_suc: + * Number of 11mc Fine Timing Measurement frames transmitted successfully. + */ + A_UINT32 tx_11mc_ftm_suc; + /** tx_11mc_ftm_suc_retry: + * Number of Fine Timing Measurement frames transmitted successfully + * after retrying. + */ + A_UINT32 tx_11mc_ftm_suc_retry; + /** tx_11mc_ftm_fail: + * Number of Fine Timing Measurement frames not transmitted successfully. + */ + A_UINT32 tx_11mc_ftm_fail; + /** rx_11mc_ftmr_cnt: + * Number of FTMR frames received, including initial, non-initial, + * and duplicates. + */ + A_UINT32 rx_11mc_ftmr_cnt; + /** rx_11mc_ftmr_dup_cnt: + * Number of duplicate Fine Timing Measurement Request frames received, + * including both initial and non-initial. + */ + A_UINT32 rx_11mc_ftmr_dup_cnt; + /** rx_11mc_iftmr_cnt: + * Number of initial Fine Timing Measurement Request frames received. + */ + A_UINT32 rx_11mc_iftmr_cnt; + /** rx_11mc_iftmr_dup_cnt: + * Number of duplicate initial Fine Timing Measurement Request frames + * received. + */ + A_UINT32 rx_11mc_iftmr_dup_cnt; + /** ftmr_drop_11mc_resp_role_not_enabled_cnt: + * Number of FTMR frames dropped as 11mc is not supported for this VAP. + */ + A_UINT32 ftmr_drop_11mc_resp_role_not_enabled_cnt; + /** initiator_active_responder_rejected_cnt: + * Number of responder sessions rejected when initiator was active. + */ + A_UINT32 initiator_active_responder_rejected_cnt; + /** responder_terminate_cnt: + * Number of times Responder session got terminated. + */ + A_UINT32 responder_terminate_cnt; + /** active_rsta_open: + * Number of active responder contexts in open mode. + */ + A_UINT32 active_rsta_open; + /** active_rsta_mac: + * Number of active responder contexts in mac security mode. + */ + A_UINT32 active_rsta_mac; + /** active_rsta_mac_phy: + * Number of active responder contexts in mac_phy security mode. + */ + A_UINT32 active_rsta_mac_phy; + /** num_assoc_ranging_peers: + * Number of active associated ISTA ranging peers. + */ + A_UINT32 num_assoc_ranging_peers; + /** num_unassoc_ranging_peers: + * Number of active un-associated ISTA ranging peers. + */ + A_UINT32 num_unassoc_ranging_peers; + /** responder_alloc_cnt: + * Number of responder contexts allocated. + */ + A_UINT32 responder_alloc_cnt; + /** responder_alloc_failure: + * Number of times responder context failed to be allocated. + */ + A_UINT32 responder_alloc_failure; + /** pn_check_failure_cnt: + * Number of times PN check failed. + */ + A_UINT32 pn_check_failure_cnt; + /** pasn_m1_auth_recv_cnt: + * Num of M1 auth frames received for PASN over the air from iSTA. + */ + A_UINT32 pasn_m1_auth_recv_cnt; + /** pasn_m1_auth_drop_cnt: + * Number of M1 auth frames received for PASN over the air from iSTA + * but dropped in FW due to any reason (such as unavailability of + * responder ctxt or any other check). + */ + A_UINT32 pasn_m1_auth_drop_cnt; + /** pasn_m2_auth_recv_cnt: + * Number of M2 auth frames received in FW for PASN from Host driver. + */ + A_UINT32 pasn_m2_auth_recv_cnt; + /** pasn_m2_auth_tx_fail_cnt: + * Number of M2 auth frames received in FW but Tx failed. + */ + A_UINT32 pasn_m2_auth_tx_fail_cnt; + /** pasn_m3_auth_recv_cnt: + * Number of M3 auth frames received for PASN. + */ + A_UINT32 pasn_m3_auth_recv_cnt; + /** pasn_m3_auth_drop_cnt: + * Number of M3 auth frames received for PASN over the air from iSTA but + * dropped in FW due to any reason. + */ + A_UINT32 pasn_m3_auth_drop_cnt; + /** pasn_peer_create_request_cnt: + * Number of times FW requested PASN peer create request to Host. + */ + A_UINT32 pasn_peer_create_request_cnt; + /** pasn_peer_create_timeout_cnt: + * Number of times PASN peer was not created within timeout period. + */ + A_UINT32 pasn_peer_create_timeout_cnt; + /** pasn_peer_created_cnt: + * Number of times Host sent PASN peer create request to FW. + */ + A_UINT32 pasn_peer_created_cnt; + /** sec_ranging_not_supported_mfp_not_setup: + * management frame protection not setup, drop secure ranging request. + */ + A_UINT32 sec_ranging_not_supported_mfp_not_setup; + /** non_sec_ranging_discarded_for_assoc_peer_with_mfpr_set: + * Non secured ranging request discarded for Assoc peer with MFPR set. + */ + A_UINT32 non_sec_ranging_discarded_for_assoc_peer_with_mfpr_set; + /** open_ranging_discarded_with_URNM_MFPR_set_for_pasn_peer: + * Failure in case non-secured frame is received for PASN peer and + * URNM_MFPR is set. + */ + A_UINT32 open_ranging_discarded_with_URNM_MFPR_set_for_pasn_peer; + /** unassoc_non_pasn_ranging_not_supported_with_URNM_MFPR: + * Failure in case non-assoc/non-PASN sta is sending open FTMR and + * RSTA does not support un-secured ranging. + */ + A_UINT32 unassoc_non_pasn_ranging_not_supported_with_URNM_MFPR; + /** num_req_bw_20_MHz: + * Number of requests with BW 20 MHz. + */ + A_UINT32 num_req_bw_20_MHz; + /** num_req_bw_40_MHz: + * Number of requests with BW 40 MHz. + */ + A_UINT32 num_req_bw_40_MHz; + /** num_req_bw_80_MHz: + * Number of requests with BW 80 MHz. + */ + A_UINT32 num_req_bw_80_MHz; + /** num_req_bw_160_MHz: + * Number of requests with BW 160 MHz. + */ + A_UINT32 num_req_bw_160_MHz; + /** tx_11az_ftm_successful: + * Number of 11AZ FTM frames transmitted successfully. + */ + A_UINT32 tx_11az_ftm_successful; + /** tx_11az_ftm_failed: + * Number of 11AZ FTM frames for which Tx failed. + */ + A_UINT32 tx_11az_ftm_failed; + /** rx_11az_ftmr_cnt: + * Number of 11AZ FTM frames received. + */ + A_UINT32 rx_11az_ftmr_cnt; + /** rx_11az_ftmr_dup_cnt: + * Number of duplicate 11az ftmr frames dropped. + */ + A_UINT32 rx_11az_ftmr_dup_cnt; + /** rx_11az_iftmr_dup_cnt: + * Number of duplicate 11az iftmr frames dropped. + */ + A_UINT32 rx_11az_iftmr_dup_cnt; + /** malformed_ftmr: + * Number of malformed FTMR frames received from client leading to + * frame parse error. + */ + A_UINT32 malformed_ftmr; + /** ftmr_drop_ntb_resp_role_not_enabled_cnt: + * Number of FTMR frames dropped as NTB is not supported for this VAP. + */ + A_UINT32 ftmr_drop_ntb_resp_role_not_enabled_cnt; + /** ftmr_drop_tb_resp_role_not_enabled_cnt: + * Number of FTMR frames dropped as TB is not supported for this VAP. + */ + A_UINT32 ftmr_drop_tb_resp_role_not_enabled_cnt; + /** invalid_ftm_request_params: + * Number of FTMR frames received with invalid params. + */ + A_UINT32 invalid_ftm_request_params; + /** requested_bw_format_not_supported: + * FTMR rejected as requested format is lower or higher than AP's + * capability, or unknown. + */ + A_UINT32 requested_bw_format_not_supported; + /** ntb_unsec_unassoc_mode_ranging_peer_alloc_failed: + * AST entry creation failed for NTB unsecured mode. + */ + A_UINT32 ntb_unsec_unassoc_mode_ranging_peer_alloc_failed; + /** tb_unassoc_unsec_mode_pasn_peer_creation_failed: + * PASN peer creation failed for unsecured mode TBR. + */ + A_UINT32 tb_unassoc_unsec_mode_pasn_peer_creation_failed; + /** num_ranging_sequences_processed: + * Number of ranging sequences processed for NTB and TB. + */ + A_UINT32 num_ranging_sequences_processed; + /** Number of NDPs transmitted for NTBR */ + A_UINT32 ntb_tx_ndp; + A_UINT32 ndp_rx_cnt; + /** Number of NDPAs received for 11AZ NTB ranging */ + A_UINT32 num_ntb_ranging_NDPAs_recv; + /** Number of LMR frames received */ + A_UINT32 recv_lmr; + /** invalid_ftmr_cnt: + * Number of invalid FTMR frames received + * iftmr with null ie element is invalid + * The Frame is valid if any of the following combination is present: + * a. LCI sub ie + parameter ie + * b. LCR sub ie + parameter ie + * c. parameter ie + * d. LCI sub ie + LCR sub ie + parameter ie + */ + A_UINT32 invalid_ftmr_cnt; + /** Number of times the 'max time b/w measurement' timer got expired */ + A_UINT32 max_time_bw_meas_exp_cnt; +} htt_stats_pdev_rtt_resp_stats_tlv; + +/* STATS_TYPE: HTT_DBG_EXT_PDEV_RTT_RESP_STATS + * TLV_TAGS: + * HTT_STATS_PDEV_RTT_RESP_STATS_TAG + * HTT_STATS_PDEV_RTT_HW_STATS_TAG + * HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG + * HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG + */ +typedef struct { + htt_stats_pdev_rtt_resp_stats_tlv pdev_rtt_resp_stats; + htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; + htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv pdev_rtt_tbr_selfgen_queued_stats; + htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv pdev_rtt_tbr_cmd_result_stats; +} htt_pdev_rtt_resp_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 pdev_id; + /** tx_11mc_ftmr_cnt: + * Number of 11mc Fine Timing Measurement request frames transmitted + * successfully. + */ + A_UINT32 tx_11mc_ftmr_cnt; + /** tx_11mc_ftmr_fail: + * Number of 11mc Fine Timing Measurement request frames not transmitted + * successfully. + */ + A_UINT32 tx_11mc_ftmr_fail; + /** tx_11mc_ftmr_suc_retry: + * Number of 11mc Fine Timing Measurement request frames transmitted + * successfully after retrying. + */ + A_UINT32 tx_11mc_ftmr_suc_retry; + /** rx_11mc_ftm_cnt: + * Number of 11mc Fine Timing Measurement frames received, including + * initial, non-initial, and duplicates. + */ + A_UINT32 rx_11mc_ftm_cnt; + /** Count of Ranging Measurement requests received from host */ + A_UINT32 tx_meas_req_count; + /** Initiator role not supported on the vdev */ + A_UINT32 init_role_not_enabled; + /** Number of times Initiator context got terminated */ + A_UINT32 initiator_terminate_cnt; + /** Number of times Tx of FTMR failed */ + A_UINT32 tx_11az_ftmr_fail; + /** tx_11az_ftmr_start: + * Number of Fine Timing Measurement start requests transmitted + * successfully. + */ + A_UINT32 tx_11az_ftmr_start; + /** tx_11az_ftmr_stop: + * Number of Fine Timing Measurement stop requests transmitted + * successfully. + */ + A_UINT32 tx_11az_ftmr_stop; + /** Number of FTM frames received successfully */ + A_UINT32 rx_11az_ftm_cnt; + /** Number of active ISTA sessions */ + A_UINT32 active_ista; + /** HE preamble not enabled on Initiator side */ + A_UINT32 invalid_preamble; + /** Initiator invalid channel bw format */ + A_UINT32 invalid_chan_bw_format; + /* mgmt_buff_alloc_fail_cnt Management Buffer allocation failure count */ + A_UINT32 mgmt_buff_alloc_fail_cnt; + /** ftm_parse_failure: + * Count of FTM frame IE parse failure or RSTA sending measurement + * negotiation failure. + */ + A_UINT32 ftm_parse_failure; + /** Count of NTB/TB ranging negotiation completed successfully */ + A_UINT32 ranging_negotiation_successful_cnt; + /** incompatible_ftm_params: + * Number of occurrences of failure due to incompatible parameters + * suggested by rSTA during negotiation. + */ + A_UINT32 incompatible_ftm_params; + /** sec_ranging_req_in_open_mode: + * Number of occurrences of failure if BSS peer exists in open mode and + * secured mode RTT ranging is requested. + */ + A_UINT32 sec_ranging_req_in_open_mode; + /** ftmr_tx_failed_null_11az_peer: + * Number of occurrences where FTMR was not transmitted as there was + * no 11AZ peer. + */ + A_UINT32 ftmr_tx_failed_null_11az_peer; + /** Number of times ftmr retry timed out */ + A_UINT32 ftmr_retry_timeout; + /** Number of times the 'max time b/w measurement' timer got expired */ + A_UINT32 max_time_bw_meas_exp_cnt; + /** tb_meas_duration_expiry_cnt: + * Number of times TBR measurement duration expired. + */ + A_UINT32 tb_meas_duration_expiry_cnt; + /** num_tb_ranging_requests: + * Number of TB ranging requests ready for negotiation. + */ + A_UINT32 num_tb_ranging_requests; + /** Number of times NTB ranging was triggered successfully */ + A_UINT32 ntbr_triggered_successfully; + /** Number of times NTB ranging failed to be triggered */ + A_UINT32 ntbr_trigger_failed; + /** No valid index found for programming vreg settings */ + A_UINT32 invalid_or_no_vreg_idx; + /** Number of times VREG setting failed */ + A_UINT32 set_vreg_params_failed; + /** Number of occurrences of SAC mismatch */ + A_UINT32 sac_mismatch; + /** pasn_m1_auth_recv_cnt: + * Number of M1 auth frames received for PASN from Host. + */ + A_UINT32 pasn_m1_auth_recv_cnt; + /** pasn_m1_auth_tx_fail_cnt: + * Number of M1 auth frames received in FW but Tx failed. + */ + A_UINT32 pasn_m1_auth_tx_fail_cnt; + /** pasn_m2_auth_recv_cnt: + * Number of M2 auth frames received in FW for PASN over the air from rSTA. + */ + A_UINT32 pasn_m2_auth_recv_cnt; + /** pasn_m2_auth_drop_cnt: + * Number of M2 auth frames received in FW but dropped due to any reason. + */ + A_UINT32 pasn_m2_auth_drop_cnt; + /** pasn_m3_auth_recv_cnt: + * Number of M3 auth frames received for PASN from Host. + */ + A_UINT32 pasn_m3_auth_recv_cnt; + /** pasn_m3_auth_tx_fail_cnt: + * Number of M3 auth frames received in FW but Tx failed. + */ + A_UINT32 pasn_m3_auth_tx_fail_cnt; + /** pasn_peer_create_request_cnt: + * Number of times FW requested PASN peer create request to Host. + */ + A_UINT32 pasn_peer_create_request_cnt; + /** pasn_peer_create_timeout_cnt: + * Number of times PASN peer was not created within timeout period. + */ + A_UINT32 pasn_peer_create_timeout_cnt; + /** pasn_peer_created_cnt: + * Number of times Host sent PASN peer create request to FW. + */ + A_UINT32 pasn_peer_created_cnt; + /** Number of occurrences of Tx of NDPA failing */ + A_UINT32 ntbr_ndpa_failed; + /** ntbr_sequence_successful: + * The NDPA, NDP and LMR exchanges are successful and sched cmd status + * is 0. + */ + A_UINT32 ntbr_sequence_successful; + /** ntbr_ndp_failed: + * Number of occurrences of NDPA being transmitted successfully + * but NDP failing for NTB ranging. + */ + A_UINT32 ntbr_ndp_failed; + /** sch_cmd_status_cnts: + * Elements 0-7 count the number of times the sch_cmd_status was equal to + * the corresponding value of the index of the array sch_cmd_status_cnts[], + * and element 8 counts the numbers of times the status was some other + * value >=8. + */ + A_UINT32 sch_cmd_status_cnts[9]; + /** Number of times LMR reception timed out */ + A_UINT32 lmr_timeout; + /** Number of LMR frames received */ + A_UINT32 lmr_recv; + /** Number of trigger frames received */ + A_UINT32 num_trigger_frames_received; + /** Number of NDPAs received for TBR */ + A_UINT32 num_tb_ranging_NDPAs_recv; + /** Number of ranging NDPs received for NTBR/TB */ + A_UINT32 ndp_rx_cnt; +} htt_stats_pdev_rtt_init_stats_tlv; + +/* STATS_TYPE: HTT_DBG_EXT_PDEV_RTT_INITIATOR_STATS + * TLV_TAGS: + * HTT_STATS_PDEV_RTT_INIT_STATS_TAG + * HTT_STATS_PDEV_RTT_HW_STATS_TAG + */ +typedef struct { + htt_stats_pdev_rtt_init_stats_tlv pdev_rtt_init_stats; + htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; +} htt_pdev_rtt_init_stats_t; + + /* STATS_TYPE : HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS * TLV_TAGS: * - HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG From b0d26ad1f4490c86e69938933e204408fa105010 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 11 Jan 2024 06:02:38 -0800 Subject: [PATCH 48/74] fw-api: CL 25777035 - update fw common interface files WMI: fix WMI_MLO_MODE_ const defs (remove semicolon) Change-Id: Ia5fc1bea8b1087fe3ca19a2e376a00d122fdd986 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 4 ++-- fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8d018a90e6ee..5e6a2d5b378f 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -45182,8 +45182,8 @@ typedef struct wmi_mlo_set_active_link_number_param } wmi_mlo_set_active_link_number_param; -#define WMI_MLO_MODE_MLMR 0x1; -#define WMI_MLO_MODE_EMLSR 0x2; +#define WMI_MLO_MODE_MLMR 0x1 +#define WMI_MLO_MODE_EMLSR 0x2 #define WMI_MLO_IEEE_LINK_ID_INVALID 0xFF diff --git a/fw/wmi_version.h b/fw/wmi_version.h index feaef7c7077a..4715829a36ca 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1440 +#define __WMI_REVISION_ 1441 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From fa6fe3611018e142e9b7755f791d6ba37ffa67db Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 11 Jan 2024 18:01:33 -0800 Subject: [PATCH 49/74] fw-api: CL 25779296 - update fw common interface files WMI: add more stats in ctrl_path_awgn_stats_struct Also, piggyback fixes for the sar_flags TLV tag in READY_EXT2_EVENT, and the Windows definition of the WMI_VAR_LEN_ARRAY1 macro. Change-Id: I5211f043eaafc234a06a2cc91b530904b9d0b3d1 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 2 +- fw/wmi_unified.h | 80 +++++++++++++++++++++++++++++++++++++++-------- fw/wmi_version.h | 2 +- 3 files changed, 69 insertions(+), 15 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index f45980d0c8a9..36e090500fef 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -5630,7 +5630,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sar_flags, wmi_sar_flag_tlv_param, sar_flags, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sar_flag_tlv_param, sar_flags, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID); #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 5e6a2d5b378f..92a04aff7fa6 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -102,14 +102,18 @@ extern "C" { #define WMI_DUMMY_ZERO_LEN_FIELD struct {} dummy_zero_len_field #endif -#define WMI_VAR_LEN_ARRAY1(type, name) \ - union { \ - type name ## __first_elem; \ - struct { \ - WMI_DUMMY_ZERO_LEN_FIELD; \ - type name[]; \ - }; \ - } +#if defined(__WINDOWS__) + #define WMI_VAR_LEN_ARRAY1(type, name) type name[1] +#else + #define WMI_VAR_LEN_ARRAY1(type, name) \ + union { \ + type name ## __first_elem; \ + struct { \ + WMI_DUMMY_ZERO_LEN_FIELD; \ + type name[]; \ + }; \ + } +#endif #define ATH_MAC_LEN 6 /**< length of MAC in bytes */ #define WMI_EVENT_STATUS_SUCCESS 0 /* Success return status to host */ @@ -13217,13 +13221,63 @@ typedef struct { A_UINT32 awgn_cca_ack_reset_cnt; /* * AWGN int BW cnt used to store interference occurred at 20/40/80/160MHz - * bw_cnt[0] counts interference detections in 20 MHz BW, - * bw_cnt[1] counts interference detections in 40 MHz BW, - * bw_cnt[2] counts interference detections in 80 MHz BW, - * bw_cnt[3] counts interference detections in 160 MHz BW, - * bw_cnt[4] and bw_cnt[6] are reserved for 240 MHz and 320 MHz. + * awgn_int_bw_cnt[0] counts interference detections in 20 MHz BW, + * awgn_int_bw_cnt[1] counts interference detections in 40 MHz BW, + * awgn_int_bw_cnt[2] counts interference detections in 80 MHz BW, + * awgn_int_bw_cnt[3] counts interference detections in 160 MHz BW, + * awgn_int_bw_cnt[4] is reserved for 240 MHz BW, + * awgn_int_bw_cnt[5] counts interference detections in 320 MHz BW. */ A_UINT32 awgn_int_bw_cnt[WMI_AWGN_MAX_BW]; + + /* Number of OBSS interference occurred */ + A_UINT32 obss_int_cnt; + + /* Number of OBSS interference Sent to host */ + A_UINT32 obss_int_evt_sent_host_cnt; + + /* Number of OBSS interference skiped due to AWGN as high priority */ + A_UINT32 obss_int_evt_skip_awgn_cnt; + + /* Number of OBSS interference skiped due to duplicate OBSS interference */ + A_UINT32 obss_int_evt_skip_dup_cnt; + + /* Current OBSS interference segment details + * chan_bw_interference_bitmap: + * Indicates which 20MHz segments contain interference + * 320 MHz: bits 0-15 + * 160 MHz: bits 0-7 + * 80 MHz: bits 0-3 + * Within the bitmap, Bit-0 represents lowest 20Mhz, Bit-1 represents + * second lowest 20Mhz and so on. + * Each bit position will indicate 20MHz in which interference is seen. + * (Valid 16 bits out of 32 bit integer) + */ + A_UINT32 obss_int_cur_int_seg; + + /* Previous OBSS Int Segment details + * chan_bw_interference_bitmap: + * Indicates which 20MHz segments contain interference + * 320 MHz: bits 0-15 + * 160 MHz: bits 0-7 + * 80 MHz: bits 0-3 + * Within the bitmap, Bit-0 represents lowest 20Mhz, Bit-1 represents + * second lowest 20Mhz and so on. + * Each bit position will indicate 20MHz in which interference is seen. + * (Valid 16 bits out of 32 bit integer) + */ + A_UINT32 obss_int_prv_int_seg; + + /* + * OBSS int BW cnt used to store interference occurred at 20/40/80/160MHz + * obss_int_bw_cnt[0] counts interference detections in 20 MHz BW, + * obss_int_bw_cnt[1] counts interference detections in 40 MHz BW, + * obss_int_bw_cnt[2] counts interference detections in 80 MHz BW, + * obss_int_bw_cnt[3] counts interference detections in 160 MHz BW, + * obss_int_bw_cnt[4] counts interference detections in 240 MHz BW, + * obss_int_bw_cnt[5] counts interference detections in 320 MHz BW, + */ + A_UINT32 obss_int_bw_cnt[WMI_AWGN_MAX_BW]; } wmi_ctrl_path_awgn_stats_struct; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4715829a36ca..eef411cda958 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1441 +#define __WMI_REVISION_ 1442 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 230ae6e258442029c0e3ebd81963eedbac294b6d Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 13 Jan 2024 12:01:32 -0800 Subject: [PATCH 50/74] fw-api: CL 25795907 - update fw common interface files WMI: add MLO_LINK_INFO_SYNC_EVENTID def Change-Id: I3f9b0b9ac600cecf5b68f37d8f0382675a08854e CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 13 ++++++++++++- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 36e090500fef..82b91eb71944 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -2293,6 +2293,7 @@ typedef enum { OP(WMI_VDEV_OOB_CONNECTION_RESP_EVENTID) \ OP(WMI_AUDIO_TRANSPORT_SWITCH_TYPE_EVENTID) \ OP(WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID) \ + OP(WMI_MLO_LINK_INFO_SYNC_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5856,6 +5857,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_fw_consumed_hdr, wmi_mgmt_rx_fw_consumed_hdr, hdr, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_FW_CONSUMED_EVENTID); +/* Management MLO LINK Info Sync Event */ +#define WMITLV_TABLE_WMI_MLO_LINK_INFO_SYNC_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_ml_info, ml_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_removal_tbtt_count, link_removal_tbtt_count, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_INFO_SYNC_EVENTID); + /* TBTT offset Event */ #define WMITLV_TABLE_WMI_TBTTOFFSET_UPDATE_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param, wmi_tbtt_offset_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 92a04aff7fa6..3fcafbc5eab0 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -2489,6 +2489,8 @@ typedef enum { WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID, /** WMI Event to spcify reason for link state switch */ WMI_MLO_LINK_STATE_SWITCH_EVENTID, + /** WMI Event to sync link info to host */ + WMI_MLO_LINK_INFO_SYNC_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), diff --git a/fw/wmi_version.h b/fw/wmi_version.h index eef411cda958..d921d967b9f7 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1442 +#define __WMI_REVISION_ 1443 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 9f3d1efe8970003efc3baa63e0bd382d43916eae Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 16 Jan 2024 18:01:49 -0800 Subject: [PATCH 51/74] fw-api: CL 25798927 - update fw common interface files WMI: add VDEV_PARAM_TELESDTIM_CNT + WOW_FLAG_TELES_DTIM_ON_SYS_SUSPEND defs Change-Id: I19089cdeea872daa5c04d64a1b3b6651aabaa65a CRs-Fixed: 2262693 --- fw/wmi_unified.h | 9 +++++++++ fw/wmi_version.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 3fcafbc5eab0..3a33cf18f4ab 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -18466,6 +18466,9 @@ typedef enum { /* DCS stats enable configuration at VDEV level */ WMI_VDEV_PARAM_DCS, /* 0xC2 */ + /* VDEV parameter to configure Telescopic DTIM count */ + WMI_VDEV_PARAM_TELESDTIM_CNT, /* 0xC3 */ + /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === * The below vdev param types are used for prototyping, and are @@ -23704,6 +23707,12 @@ enum { WMI_WOW_FLAG_FORCED_DTIM_ON_SYS_SUSPEND = 0x00000080, /* Flag to force DPD lock. */ WMI_WOW_FLAG_FORCED_DPD_LOCK = 0x00000100, + /* + * Feature flag for INI 'enable_teles_dtim_on_system_suspend' + * This flag/bit will be set if INI 'enable_teles_dtim_on_system_suspend' + * is enabled. + */ + WMI_WOW_FLAG_TELES_DTIM_ON_SYS_SUSPEND = 0x00000200, }; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index d921d967b9f7..b931cae48b56 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1443 +#define __WMI_REVISION_ 1444 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 8cc176287491d85d88fd866a2333507efb557a33 Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Mon, 22 Jan 2024 17:42:13 -0500 Subject: [PATCH 52/74] msm: npu: Fix OOB issue in IPC between driver and firmware We shoudn't trust the data from firmware, and need to validate all content before using them. Change-Id: I832c927a2a67b42a06625f1f62602d9d51e4a78e Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_common.h | 6 -- drivers/media/platform/msm/npu/npu_debugfs.c | 78 ------------------- drivers/media/platform/msm/npu/npu_host_ipc.c | 40 ++++++++-- .../media/platform/msm/npu/npu_hw_access.c | 47 ----------- .../media/platform/msm/npu/npu_hw_access.h | 3 - drivers/media/platform/msm/npu/npu_mgr.c | 64 +++------------ 6 files changed, 43 insertions(+), 195 deletions(-) diff --git a/drivers/media/platform/msm/npu/npu_common.h b/drivers/media/platform/msm/npu/npu_common.h index 5a9754b1efef..8f028cd957a6 100644 --- a/drivers/media/platform/msm/npu/npu_common.h +++ b/drivers/media/platform/msm/npu/npu_common.h @@ -109,12 +109,6 @@ struct npu_debugfs_ctx { struct dentry *root; uint32_t reg_off; uint32_t reg_cnt; - uint8_t *log_buf; - struct mutex log_lock; - uint32_t log_num_bytes_buffered; - uint32_t log_read_index; - uint32_t log_write_index; - uint32_t log_buf_size; }; struct npu_debugfs_reg_ctx { diff --git a/drivers/media/platform/msm/npu/npu_debugfs.c b/drivers/media/platform/msm/npu/npu_debugfs.c index 26bac2eaf4fd..92db1cb833c7 100644 --- a/drivers/media/platform/msm/npu/npu_debugfs.c +++ b/drivers/media/platform/msm/npu/npu_debugfs.c @@ -13,12 +13,6 @@ #include "npu_hw_access.h" #include "npu_common.h" -/* ------------------------------------------------------------------------- - * Defines - * ------------------------------------------------------------------------- - */ -#define NPU_LOG_BUF_SIZE 4096 - /* ------------------------------------------------------------------------- * Function Prototypes * ------------------------------------------------------------------------- @@ -33,8 +27,6 @@ static ssize_t npu_debug_off_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos); static ssize_t npu_debug_off_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos); -static ssize_t npu_debug_log_read(struct file *file, - char __user *user_buf, size_t count, loff_t *ppos); static ssize_t npu_debug_ctrl_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos); @@ -57,13 +49,6 @@ static const struct file_operations npu_off_fops = { .write = npu_debug_off_write, }; -static const struct file_operations npu_log_fops = { - .open = npu_debug_open, - .release = npu_debug_release, - .read = npu_debug_log_read, - .write = NULL, -}; - static const struct file_operations npu_ctrl_fops = { .open = npu_debug_open, .release = npu_debug_release, @@ -248,48 +233,6 @@ static ssize_t npu_debug_off_read(struct file *file, return len; } -/* ------------------------------------------------------------------------- - * Function Implementations - DebugFS Log - * ------------------------------------------------------------------------- - */ -static ssize_t npu_debug_log_read(struct file *file, - char __user *user_buf, size_t count, loff_t *ppos) -{ - size_t len = 0; - struct npu_device *npu_dev = file->private_data; - struct npu_debugfs_ctx *debugfs; - - NPU_DBG("npu_dev %pK %pK\n", npu_dev, g_npu_dev); - npu_dev = g_npu_dev; - debugfs = &npu_dev->debugfs_ctx; - - /* mutex log lock */ - mutex_lock(&debugfs->log_lock); - - if (debugfs->log_num_bytes_buffered != 0) { - len = min(debugfs->log_num_bytes_buffered, - debugfs->log_buf_size - debugfs->log_read_index); - len = min(count, len); - if (copy_to_user(user_buf, (debugfs->log_buf + - debugfs->log_read_index), len)) { - NPU_ERR("failed to copy to user\n"); - mutex_unlock(&debugfs->log_lock); - return -EFAULT; - } - debugfs->log_read_index += len; - if (debugfs->log_read_index == debugfs->log_buf_size) - debugfs->log_read_index = 0; - - debugfs->log_num_bytes_buffered -= len; - *ppos += len; - } - - /* mutex log unlock */ - mutex_unlock(&debugfs->log_lock); - - return len; -} - /* ------------------------------------------------------------------------- * Function Implementations - DebugFS Control * ------------------------------------------------------------------------- @@ -373,12 +316,6 @@ int npu_debugfs_init(struct npu_device *npu_dev) goto err; } - if (!debugfs_create_file("log", 0644, debugfs->root, - npu_dev, &npu_log_fops)) { - NPU_ERR("debugfs_create_file log fail\n"); - goto err; - } - if (!debugfs_create_file("ctrl", 0644, debugfs->root, npu_dev, &npu_ctrl_fops)) { NPU_ERR("debugfs_create_file ctrl fail\n"); @@ -421,15 +358,6 @@ int npu_debugfs_init(struct npu_device *npu_dev) goto err; } - debugfs->log_num_bytes_buffered = 0; - debugfs->log_read_index = 0; - debugfs->log_write_index = 0; - debugfs->log_buf_size = NPU_LOG_BUF_SIZE; - debugfs->log_buf = kzalloc(debugfs->log_buf_size, GFP_KERNEL); - if (!debugfs->log_buf) - goto err; - mutex_init(&debugfs->log_lock); - return 0; err: @@ -441,12 +369,6 @@ void npu_debugfs_deinit(struct npu_device *npu_dev) { struct npu_debugfs_ctx *debugfs = &npu_dev->debugfs_ctx; - debugfs->log_num_bytes_buffered = 0; - debugfs->log_read_index = 0; - debugfs->log_write_index = 0; - debugfs->log_buf_size = 0; - kfree(debugfs->log_buf); - if (!IS_ERR_OR_NULL(debugfs->root)) { debugfs_remove_recursive(debugfs->root); debugfs->root = NULL; diff --git a/drivers/media/platform/msm/npu/npu_host_ipc.c b/drivers/media/platform/msm/npu/npu_host_ipc.c index 0787406a830a..0740a0cb254f 100644 --- a/drivers/media/platform/msm/npu/npu_host_ipc.c +++ b/drivers/media/platform/msm/npu/npu_host_ipc.c @@ -31,15 +31,16 @@ struct npu_queue_tuple { uint32_t size; uint32_t hdr; + uint32_t start_offset; }; -static const struct npu_queue_tuple npu_q_setup[6] = { - { 1024, IPC_QUEUE_CMD_HIGH_PRIORITY | TX_HDR_TYPE | RX_HDR_TYPE }, - { 4096, IPC_QUEUE_APPS_EXEC | TX_HDR_TYPE | RX_HDR_TYPE }, - { 4096, IPC_QUEUE_DSP_EXEC | TX_HDR_TYPE | RX_HDR_TYPE }, - { 4096, IPC_QUEUE_APPS_RSP | TX_HDR_TYPE | RX_HDR_TYPE }, - { 4096, IPC_QUEUE_DSP_RSP | TX_HDR_TYPE | RX_HDR_TYPE }, - { 1024, IPC_QUEUE_LOG | TX_HDR_TYPE | RX_HDR_TYPE }, +static struct npu_queue_tuple npu_q_setup[6] = { + { 1024, IPC_QUEUE_CMD_HIGH_PRIORITY | TX_HDR_TYPE | RX_HDR_TYPE, 0}, + { 4096, IPC_QUEUE_APPS_EXEC | TX_HDR_TYPE | RX_HDR_TYPE, 0}, + { 4096, IPC_QUEUE_DSP_EXEC | TX_HDR_TYPE | RX_HDR_TYPE, 0}, + { 4096, IPC_QUEUE_APPS_RSP | TX_HDR_TYPE | RX_HDR_TYPE, 0}, + { 4096, IPC_QUEUE_DSP_RSP | TX_HDR_TYPE | RX_HDR_TYPE, 0}, + { 1024, IPC_QUEUE_LOG | TX_HDR_TYPE | RX_HDR_TYPE, 0}, }; /* ------------------------------------------------------------------------- @@ -111,6 +112,7 @@ static int npu_host_ipc_init_hfi(struct npu_device *npu_dev) /* queue is active */ q_hdr->qhdr_status = 0x01; q_hdr->qhdr_start_offset = cur_start_offset; + npu_q_setup[q_idx].start_offset = cur_start_offset; q_size = npu_q_setup[q_idx].size; q_hdr->qhdr_type = npu_q_setup[q_idx].hdr; /* in bytes */ @@ -217,6 +219,18 @@ static int ipc_queue_read(struct npu_device *npu_dev, /* Read the queue */ MEMR(npu_dev, (void *)((size_t)offset), (uint8_t *)&queue, HFI_QUEUE_HEADER_SIZE); + + if (queue.qhdr_type != npu_q_setup[target_que].hdr || + queue.qhdr_q_size != npu_q_setup[target_que].size || + queue.qhdr_read_idx >= queue.qhdr_q_size || + queue.qhdr_write_idx >= queue.qhdr_q_size || + queue.qhdr_start_offset != + npu_q_setup[target_que].start_offset) { + NPU_ERR("Invalid Queue header\n"); + status = -EIO; + goto exit; + } + /* check if queue is empty */ if (queue.qhdr_read_idx == queue.qhdr_write_idx) { /* @@ -314,6 +328,18 @@ static int ipc_queue_write(struct npu_device *npu_dev, MEMR(npu_dev, (void *)((size_t)offset), (uint8_t *)&queue, HFI_QUEUE_HEADER_SIZE); + + if (queue.qhdr_type != npu_q_setup[target_que].hdr || + queue.qhdr_q_size != npu_q_setup[target_que].size || + queue.qhdr_read_idx >= queue.qhdr_q_size || + queue.qhdr_write_idx >= queue.qhdr_q_size || + queue.qhdr_start_offset != + npu_q_setup[target_que].start_offset) { + NPU_ERR("Invalid Queue header\n"); + status = -EIO; + goto exit; + } + packet_size = (*(uint32_t *)packet); if (packet_size == 0) { /* assign failed status and return */ diff --git a/drivers/media/platform/msm/npu/npu_hw_access.c b/drivers/media/platform/msm/npu/npu_hw_access.c index 15883dbb25d1..0dbec0d4a50c 100644 --- a/drivers/media/platform/msm/npu/npu_hw_access.c +++ b/drivers/media/platform/msm/npu/npu_hw_access.c @@ -430,50 +430,3 @@ void subsystem_put_local(void *sub_system_handle) { return subsystem_put(sub_system_handle); } - -/* ------------------------------------------------------------------------- - * Functions - Log - * ------------------------------------------------------------------------- - */ -void npu_process_log_message(struct npu_device *npu_dev, uint32_t *message, - uint32_t size) -{ - struct npu_debugfs_ctx *debugfs = &npu_dev->debugfs_ctx; - - /* mutex log lock */ - mutex_lock(&debugfs->log_lock); - - if ((debugfs->log_num_bytes_buffered + size) > - debugfs->log_buf_size) { - /* No more space, invalidate it all and start over */ - debugfs->log_read_index = 0; - debugfs->log_write_index = size; - debugfs->log_num_bytes_buffered = size; - memcpy(debugfs->log_buf, message, size); - } else { - if ((debugfs->log_write_index + size) > - debugfs->log_buf_size) { - /* Wrap around case */ - uint8_t *src_addr = (uint8_t *)message; - uint8_t *dst_addr = 0; - uint32_t remaining_to_end = debugfs->log_buf_size - - debugfs->log_write_index + 1; - dst_addr = debugfs->log_buf + debugfs->log_write_index; - memcpy(dst_addr, src_addr, remaining_to_end); - src_addr = &(src_addr[remaining_to_end]); - dst_addr = debugfs->log_buf; - memcpy(dst_addr, src_addr, size-remaining_to_end); - debugfs->log_write_index = size-remaining_to_end; - } else { - memcpy((debugfs->log_buf + debugfs->log_write_index), - message, size); - debugfs->log_write_index += size; - if (debugfs->log_write_index == debugfs->log_buf_size) - debugfs->log_write_index = 0; - } - debugfs->log_num_bytes_buffered += size; - } - - /* mutex log unlock */ - mutex_unlock(&debugfs->log_lock); -} diff --git a/drivers/media/platform/msm/npu/npu_hw_access.h b/drivers/media/platform/msm/npu/npu_hw_access.h index 1d5f5209c12e..7bc27e2f4745 100644 --- a/drivers/media/platform/msm/npu/npu_hw_access.h +++ b/drivers/media/platform/msm/npu/npu_hw_access.h @@ -86,7 +86,4 @@ void npu_disable_sys_cache(struct npu_device *npu_dev); void *subsystem_get_local(char *sub_system); void subsystem_put_local(void *sub_system_handle); -void npu_process_log_message(struct npu_device *npu_dev, uint32_t *msg, - uint32_t size); - #endif /* _NPU_HW_ACCESS_H*/ diff --git a/drivers/media/platform/msm/npu/npu_mgr.c b/drivers/media/platform/msm/npu/npu_mgr.c index 768a431e4a0b..c2f9379dd314 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.c +++ b/drivers/media/platform/msm/npu/npu_mgr.c @@ -17,15 +17,6 @@ #include #include -/* ------------------------------------------------------------------------- - * Defines - * ------------------------------------------------------------------------- - */ -#define LOG_MSG_HEADER_SIZE 20 -#define LOG_MSG_START_MSG_INDEX 5 -#define LOG_MSG_TOTAL_SIZE_INDEX 0 -#define LOG_MSG_MSG_ID_INDEX 1 - /* ------------------------------------------------------------------------- * File Scope Function Prototypes * ------------------------------------------------------------------------- @@ -51,9 +42,7 @@ static void free_network(struct npu_host_ctx *ctx, struct npu_client *client, static int network_get(struct npu_network *network); static int network_put(struct npu_network *network); static int app_msg_proc(struct npu_host_ctx *host_ctx, uint32_t *msg); -static void log_msg_proc(struct npu_device *npu_dev, uint32_t *msg); static void host_session_msg_hdlr(struct npu_device *npu_dev); -static void host_session_log_hdlr(struct npu_device *npu_dev); static int host_error_hdlr(struct npu_device *npu_dev, bool force); static int npu_send_network_cmd(struct npu_device *npu_dev, struct npu_network *network, void *cmd_ptr, @@ -1154,7 +1143,6 @@ static void npu_ipc_irq_work(struct work_struct *work) host_ctx = container_of(work, struct npu_host_ctx, ipc_irq_work); npu_dev = container_of(host_ctx, struct npu_device, host_ctx); - host_session_log_hdlr(npu_dev); host_session_msg_hdlr(npu_dev); } @@ -1689,6 +1677,12 @@ static int app_msg_proc(struct npu_host_ctx *host_ctx, uint32_t *msg) } NPU_DBG("network id : %lld\n", network->id); + if (exe_rsp_pkt->header.size < sizeof(*exe_rsp_pkt)) { + NPU_ERR("invalid packet header size, header.size: %d", + exe_rsp_pkt->header.size); + network_put(network); + break; + } stats_size = exe_rsp_pkt->header.size - sizeof(*exe_rsp_pkt); NPU_DBG("stats_size %d:%d\n", exe_rsp_pkt->header.size, stats_size); @@ -1930,47 +1924,6 @@ static void host_session_msg_hdlr(struct npu_device *npu_dev) mutex_unlock(&host_ctx->lock); } -static void log_msg_proc(struct npu_device *npu_dev, uint32_t *msg) -{ - uint32_t msg_id; - uint32_t *log_msg; - uint32_t size; - - msg_id = msg[LOG_MSG_MSG_ID_INDEX]; - size = msg[LOG_MSG_TOTAL_SIZE_INDEX] - LOG_MSG_HEADER_SIZE; - - switch (msg_id) { - case NPU_IPC_MSG_EVENT_NOTIFY: - /* Process the message */ - log_msg = &(msg[LOG_MSG_START_MSG_INDEX]); - npu_process_log_message(npu_dev, log_msg, size); - break; - default: - NPU_ERR("unsupported log response received %d\n", msg_id); - break; - } -} - -static void host_session_log_hdlr(struct npu_device *npu_dev) -{ - struct npu_host_ctx *host_ctx = &npu_dev->host_ctx; - - mutex_lock(&host_ctx->lock); - if (host_ctx->fw_state != FW_ENABLED) { - NPU_WARN("handle npu session msg when FW is disabled\n"); - goto skip_read_msg; - } - - while (npu_host_ipc_read_msg(npu_dev, IPC_QUEUE_LOG, - host_ctx->ipc_msg_buf) == 0) { - NPU_DBG("received from log queue\n"); - log_msg_proc(npu_dev, host_ctx->ipc_msg_buf); - } - -skip_read_msg: - mutex_unlock(&host_ctx->lock); -} - /* ------------------------------------------------------------------------- * Function Definitions - Functionality * ------------------------------------------------------------------------- @@ -2368,7 +2321,10 @@ int32_t npu_host_get_fw_property(struct npu_device *npu_dev, NPU_ERR("prop_id: %x\n", prop_from_fw->prop_id); NPU_ERR("network_hdl: %x\n", prop_from_fw->network_hdl); NPU_ERR("param_num: %x\n", prop_from_fw->num_of_params); - for (i = 0; i < prop_from_fw->num_of_params; i++) + num_of_params = min_t(uint32_t, + prop_from_fw->num_of_params, + (uint32_t)PROP_PARAM_MAX_SIZE); + for (i = 0; i < num_of_params; i++) NPU_ERR("%x\n", prop_from_fw->prop_param[i]); } From 0b4a1f63182213b75b60f79339d6f2ccc97856f6 Mon Sep 17 00:00:00 2001 From: Srinivas Girigowda Date: Mon, 8 Jan 2024 12:15:39 -0800 Subject: [PATCH 53/74] fw-api: peach: v2: Fix compilation errors Add missing msmhwiobase.h header file, fields and fix compilation errors. CRs-Fixed: 3701189 Change-Id: Ic955f945c27f9096c896a5e3acb3e13155fd4ca3 --- hw/peach/v2/msmhwiobase.h | 187 ++++++++++++++++++++++++++++ hw/peach/v2/msmhwioreg.h | 88 +++++++++++++ hw/peach/v2/phyrx_rssi_legacy.h | 5 + hw/peach/v2/rx_msdu_details.h | 5 + hw/peach/v2/wcss_seq_hwioreg_umac.h | 5 + hw/peach/v2/wcss_version.h | 2 +- 6 files changed, 291 insertions(+), 1 deletion(-) create mode 100644 hw/peach/v2/msmhwiobase.h diff --git a/hw/peach/v2/msmhwiobase.h b/hw/peach/v2/msmhwiobase.h new file mode 100644 index 000000000000..ad53ab655680 --- /dev/null +++ b/hw/peach/v2/msmhwiobase.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __MSMHWIOBASE_H__ +#define __MSMHWIOBASE_H__ + +#define WCSS_WCSS_BASE 0x00000000 +#define WCSS_WCSS_BASE_SIZE 0x01000000 +#define WCSS_WCSS_BASE_PHYS 0x00000000 + +#define QDSS_STM_SIZE_BASE 0x00100000 +#define QDSS_STM_SIZE_BASE_SIZE 0x100000000 +#define QDSS_STM_SIZE_BASE_PHYS 0x00100000 + +#define BOOT_ROM_SIZE_BASE 0x00200000 +#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 +#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 + +#define SYSTEM_IRAM_SIZE_BASE 0x00400000 +#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 + +#define BOOT_ROM_START_ADDRESS_BASE 0x01200000 +#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 + +#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff +#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff + +#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 + +#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff +#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff + +#define QDSS_STM_BASE 0x01800000 +#define QDSS_STM_BASE_SIZE 0x100000000 +#define QDSS_STM_BASE_PHYS 0x01800000 + +#define QDSS_STM_END_BASE 0x018fffff +#define QDSS_STM_END_BASE_SIZE 0x100000000 +#define QDSS_STM_END_BASE_PHYS 0x018fffff + +#define TLMM_BASE 0x01900000 +#define TLMM_BASE_SIZE 0x00200000 +#define TLMM_BASE_PHYS 0x01900000 + +#define CORE_TOP_CSR_BASE 0x01b00000 +#define CORE_TOP_CSR_BASE_SIZE 0x00040000 +#define CORE_TOP_CSR_BASE_PHYS 0x01b00000 + +#define BLSP1_BLSP_BASE 0x01b40000 +#define BLSP1_BLSP_BASE_SIZE 0x00040000 +#define BLSP1_BLSP_BASE_PHYS 0x01b40000 + +#define SOC_WFSS_CE_REG_BASE 0x01b80000 +#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 +#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 + +#define WL_TLMM_BASE 0x01bc0000 +#define WL_TLMM_BASE_SIZE 0x00020000 +#define WL_TLMM_BASE_PHYS 0x01bc0000 + +#define MEMSS_CSR_BASE 0x01be0000 +#define MEMSS_CSR_BASE_SIZE 0x0000001c +#define MEMSS_CSR_BASE_PHYS 0x01be0000 + +#define TSENS_SROT_BASE 0x01bf0000 +#define TSENS_SROT_BASE_SIZE 0x00001000 +#define TSENS_SROT_BASE_PHYS 0x01bf0000 + +#define TSENS_TM_BASE 0x01bf1000 +#define TSENS_TM_BASE_SIZE 0x00001000 +#define TSENS_TM_BASE_PHYS 0x01bf1000 + +#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 +#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 +#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 + +#define QDSS_WRAPPER_TOP_BASE 0x01c80000 +#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd +#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 + +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 + +#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 + +#define SECURITY_CONTROL_WLAN_BASE 0x01e20000 +#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 +#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 + +#define EDPD_CAL_ACC_BASE 0x01e28000 +#define EDPD_CAL_ACC_BASE_SIZE 0x00003000 +#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 + +#define CPR_CX_CPR3_BASE 0x01e30000 +#define CPR_CX_CPR3_BASE_SIZE 0x00004000 +#define CPR_CX_CPR3_BASE_PHYS 0x01e30000 + +#define CPR_MX_CPR3_BASE 0x01e34000 +#define CPR_MX_CPR3_BASE_SIZE 0x00004000 +#define CPR_MX_CPR3_BASE_PHYS 0x01e34000 + +#define GCC_GCC_BASE 0x01e40000 +#define GCC_GCC_BASE_SIZE 0x000003e8 +#define GCC_GCC_BASE_PHYS 0x01e40000 + +#define PRNG_PRNG_TOP_BASE 0x01e50000 +#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 +#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 + +#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 +#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 + +#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 +#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 + +#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 +#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 + +#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 +#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 + +#define RRI_PREFETCH_REG_BASE 0x01e70000 +#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 +#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 + +#define SYSTEM_NOC_BASE 0x01e80000 +#define SYSTEM_NOC_BASE_SIZE 0x0000a000 +#define SYSTEM_NOC_BASE_PHYS 0x01e80000 + +#define PC_NOC_BASE 0x01f00000 +#define PC_NOC_BASE_SIZE 0x00003880 +#define PC_NOC_BASE_PHYS 0x01f00000 + +#define WLAON_WL_AON_REG_BASE 0x01f80000 +#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 +#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 + +#define SYSPM_SYSPM_REG_BASE 0x01f82000 +#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 +#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 + +#define PMU_WLAN_PMU_TOP_BASE 0x01f88000 +#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 +#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 + +#define PMU_NOC_BASE 0x01f8a000 +#define PMU_NOC_BASE_SIZE 0x00000080 +#define PMU_NOC_BASE_PHYS 0x01f8a000 + +#define PCIE_ATU_REGION_BASE 0x04000000 +#define PCIE_ATU_REGION_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_BASE_PHYS 0x04000000 + +#define PCIE_ATU_REGION_SIZE_BASE 0x40000000 +#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 + +#define PCIE_ATU_REGION_END_BASE 0x43ffffff +#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff + +#endif diff --git a/hw/peach/v2/msmhwioreg.h b/hw/peach/v2/msmhwioreg.h index dfc3a5a0205a..79f3c02d28c7 100644 --- a/hw/peach/v2/msmhwioreg.h +++ b/hw/peach/v2/msmhwioreg.h @@ -19,6 +19,94 @@ #include "msmhwiobase.h" +#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 +#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) #endif diff --git a/hw/peach/v2/phyrx_rssi_legacy.h b/hw/peach/v2/phyrx_rssi_legacy.h index f1a95baddde6..f1d8085b2d66 100644 --- a/hw/peach/v2/phyrx_rssi_legacy.h +++ b/hw/peach/v2/phyrx_rssi_legacy.h @@ -73,6 +73,11 @@ struct phyrx_rssi_legacy { #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000e0 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK + #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x00000000 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 diff --git a/hw/peach/v2/rx_msdu_details.h b/hw/peach/v2/rx_msdu_details.h index 45e67d58c104..a904a11f0981 100644 --- a/hw/peach/v2/rx_msdu_details.h +++ b/hw/peach/v2/rx_msdu_details.h @@ -135,6 +135,11 @@ struct rx_msdu_details { #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 diff --git a/hw/peach/v2/wcss_seq_hwioreg_umac.h b/hw/peach/v2/wcss_seq_hwioreg_umac.h index a4e3d3bf3738..4bfd1cc75984 100644 --- a/hw/peach/v2/wcss_seq_hwioreg_umac.h +++ b/hw/peach/v2/wcss_seq_hwioreg_umac.h @@ -803,6 +803,11 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c) #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554) #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558) #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c) diff --git a/hw/peach/v2/wcss_version.h b/hw/peach/v2/wcss_version.h index a8f986a7d7fd..6efbfa85d4d7 100644 --- a/hw/peach/v2/wcss_version.h +++ b/hw/peach/v2/wcss_version.h @@ -13,4 +13,4 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#define WCSS_VERSION V1_7 +#define WCSS_VERSION 2576 From 28d11abc58a33fe468407215f485af5b1cfa3d96 Mon Sep 17 00:00:00 2001 From: Nandha Kishore Easwaran Date: Thu, 18 Jan 2024 12:24:03 +0530 Subject: [PATCH 54/74] fw-api: Fix compilation warnings Fix compilation warning interger to void cast by changing static inline to #define. Change-Id: I7862774dd790eaec1822fa6a0b5450d269de11b3 CRs-Fixed: 3707766 --- hw/qca8074/v1/HALhwio.h | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/hw/qca8074/v1/HALhwio.h b/hw/qca8074/v1/HALhwio.h index f5e6bab429f9..bd347318272f 100644 --- a/hw/qca8074/v1/HALhwio.h +++ b/hw/qca8074/v1/HALhwio.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -459,17 +460,7 @@ extern void busywait(uint32 pause_time_us); #define __outp(port, val) (*((volatile uint8 *) ((uint32)(port))) = ((uint8) (val))) #define __outpw(port, val) (*((volatile uint16 *) ((uint32)(port))) = ((uint16) (val))) -#ifdef MAC_ADDRESS_POWER_CHECK -static inline void __outpdw(uint32 port ,uint32 val){ - whal_pwr_debug_register_address_check(port, TRUE); - (*((volatile uint32 *) (port)) = ((uint32) (val))); -} -#else -static inline void __outpdw(uint32 port ,uint32 val){ - (*((volatile uint32 *) (port)) = ((uint32) (val))); - busywait(1); -} -#endif +#define __outpdw(port, val) (*((volatile uint32 *) ((uint32)(port))) = ((uint32) (val))) #define registerRead(port) (*((volatile uint32 *) ((uint32)(port) ))) #define registerWrite(port, val) (*((volatile uint32 *) ((uint32)(port) )) = ((uint32) (val))) From 6bad3ae2b9e166df33fff8172e0940f2751f1c45 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 24 Jan 2024 06:01:15 -0800 Subject: [PATCH 55/74] fw-api: CL 25839627 - update fw common interface files add WMI_PDEV_PARAM_PWR_REDUCTION_IN_DBM def Change-Id: If79bce3c3743ad4d578639b7b375adc78c9380c6 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++++ fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 3a33cf18f4ab..2459f5907b17 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9495,6 +9495,13 @@ typedef enum { * For a 320 MHz channel, bit0 = highest 20 MHz, bit15 = lowest 20 MHz */ WMI_PDEV_PARAM_DFS_RADAR_MASK, + + /** PWR_REDUCTION_IN_DBM: + * Reduce final Tx power (derived after all considerations) + * by specified value in units of 0.25 dB. + * E.g. a value of 4 will result in a 1.0 dB tx power reduction. + */ + WMI_PDEV_PARAM_PWR_REDUCTION_IN_DBM, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index b931cae48b56..9922fc902f3a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1444 +#define __WMI_REVISION_ 1445 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 7d94456e480cf274c60ab15e8a2bc6ed730c448b Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 24 Jan 2024 06:02:44 -0800 Subject: [PATCH 56/74] fw-api: CL 25840790 - update fw common interface files WMI: add more ROAM_SCAN_CANCEL reasons, add ROAM_FAIL_REASON_SCAN_CANCEL also, piggyback name update: WMI_PDEV_PARAM_PWR_REDUCTION_IN_DBM -> WMI_PDEV_PARAM_PWR_REDUCTION_IN_QUARTER_DB Change-Id: I5c1737b8414d87ab90ff58e4a6f8ae9d8d7350dd CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++-- fw/wmi_version.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 2459f5907b17..a13596731a47 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9496,12 +9496,12 @@ typedef enum { */ WMI_PDEV_PARAM_DFS_RADAR_MASK, - /** PWR_REDUCTION_IN_DBM: + /** PWR_REDUCTION_IN_QUARTER_DB: * Reduce final Tx power (derived after all considerations) * by specified value in units of 0.25 dB. * E.g. a value of 4 will result in a 1.0 dB tx power reduction. */ - WMI_PDEV_PARAM_PWR_REDUCTION_IN_DBM, + WMI_PDEV_PARAM_PWR_REDUCTION_IN_QUARTER_DB, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -40241,6 +40241,7 @@ typedef enum { WMI_ROAM_FAIL_REASON_NO_AP_FOUND_AND_FINAL_BMISS_SENT, /* No roamable APs found during roam scan and final bmiss event sent */ WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND_AND_FINAL_BMISS_SENT, /* No candidate APs found during roam scan and final bmiss event sent */ WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK, /* Roam scan not happen due to current network condition is fine */ + WMI_ROAM_FAIL_REASON_SCAN_CANCEL, /* Roam scan canceled */ WMI_ROAM_FAIL_REASON_UNKNOWN = 255, } WMI_ROAM_FAIL_REASON_ID; @@ -40251,6 +40252,8 @@ typedef enum { WMI_ROAM_ABORT_LOWRSSI_LINK_SPEED_GOOD, /* Roam scan is not started due to good link speed during low-RSSI roaming */ WMI_ROAM_ABORT_BG_DATA_RSSI_HIGH, /* Roam scan is not started due to high data RSSI during background roaming */ WMI_ROAM_ABORT_BG_RSSI_ABOVE_THRESHOLD, /* Roam scan is not started due to high beacon RSSI during background roaming */ + WMI_ROAM_SCAN_CANCEL_IDLE_SCREEN_ON, /* Idle roam scan is canceled due to screen on */ + WMI_ROAM_SCAN_CANCEL_OTHER_PRIORITY_ROAM_SCAN, /* Roam scan is canceled due to other high priority roam scan */ } WMI_ROAM_FAIL_SUB_REASON_ID; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9922fc902f3a..3a03ed8bd254 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1445 +#define __WMI_REVISION_ 1446 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 825908d5589979b1600ab9aef02fc8d8300356c5 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 25 Jan 2024 06:01:26 -0800 Subject: [PATCH 57/74] fw-api: CL 25866433 - update fw common interface files HTT stats: clean up var len array defs Also, add properly-named macros for accessing bitfields in HTT stats TLV structs. Change-Id: I6fc0501e99d5f28f2520d81e4cce25bd4bbc95ef CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 46 ++- fw/htt_stats.h | 711 +++++++++++++++++++++++++++++++++++++------- 2 files changed, 652 insertions(+), 105 deletions(-) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index 8425b487ccb0..1fd2698551cd 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -28,6 +28,42 @@ #include #include /* HTT_STATS_MAX_CHAINS */ + +/* HTT_PPDU_STATS_VAR_LEN_ARRAY1: + * This macro is for converting the definition of existing variable-length + * arrays within HTT PPDU stats structs of the form "type name[1];" to use + * the form "type name[];" while ensuring that the length of the TLV struct + * is unmodified by the conversion. + * In general, any new variable-length structs should simply use + * "type name[];" directly, rather than using HTT_PPDU_STATS_VAR_LEN_ARRAY1. + * However, if there's a legitimate reason to make the new variable-length + * struct appear to not have a variable length, HTT_PPDU_STATS_VAR_LEN_ARRAY1 + * can be used for this purpose. + */ +#if defined(ATH_TARGET) || defined(__WINDOWS__) + #define HTT_PPDU_STATS_VAR_LEN_ARRAY1(type, name) type name[1] +#else + /* + * Certain build settings of the Linux kernel don't allow zero-element + * arrays, and C++ doesn't allow zero-length empty structs. + * Confirm that there's no build that combines kernel with C++. + */ + #ifdef __cplusplus + #error unsupported combination of kernel and C plus plus + #endif + #define HTT_PPDU_STATS_DUMMY_ZERO_LEN_FIELD struct {} dummy_zero_len_field + + #define HTT_PPDU_STATS_VAR_LEN_ARRAY1(type, name) \ + union { \ + type name ## __first_elem; \ + struct { \ + HTT_PPDU_STATS_DUMMY_ZERO_LEN_FIELD; \ + type name[]; \ + }; \ + } +#endif + + #define HTT_STATS_NUM_SUPPORTED_BW_SMART_ANTENNA 4 /* 20, 40, 80, 160 MHz */ #define HTT_BA_64_BIT_MAP_SIZE_DWORDS 2 @@ -298,7 +334,7 @@ typedef struct { * The hw portion of this struct contains a scheduler_command_status * struct, whose definition is different for different target HW types. */ - A_UINT32 hw[1]; + HTT_PPDU_STATS_VAR_LEN_ARRAY1(A_UINT32, hw); }; } htt_ppdu_stats_sch_cmd_tlv_v; @@ -2888,7 +2924,7 @@ typedef struct { * (in bytes) can be derived from the length in tlv parameters, * minus the 12 bytes of the above fields. */ - A_UINT32 payload[1]; + HTT_PPDU_STATS_VAR_LEN_ARRAY1(A_UINT32, payload); } htt_ppdu_stats_tx_mgmtctrl_payload_tlv; #define HTT_PPDU_STATS_RX_MGMTCTRL_TLV_FRAME_LENGTH_M 0x0000ffff @@ -2930,7 +2966,7 @@ typedef struct { * (in bytes) can be derived from the length in tlv parameters, * minus the 12 bytes of the above fields. */ - A_UINT32 payload[1]; + HTT_PPDU_STATS_VAR_LEN_ARRAY1(A_UINT32, payload); } htt_ppdu_stats_rx_mgmtctrl_payload_tlv; #define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_M 0x000000ff @@ -2997,7 +3033,7 @@ typedef struct { win_size : 8, reserved2 : 3; /* The number of elements in the ba_bitmap array depends on win_size. */ - A_UINT32 ba_bitmap[1]; + HTT_PPDU_STATS_VAR_LEN_ARRAY1(A_UINT32, ba_bitmap); } htt_ppdu_stats_for_smu_tlv; typedef struct { diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 9f15c384519b..66260d939222 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -29,6 +29,43 @@ #include #include /* HTT stats TLV struct def and tag defs */ + +/* HTT_STATS_VAR_LEN_ARRAY1: + * This macro is for converting the definition of existing variable-length + * arrays within TLV structs of the form "type name[1];" to use the form + * "type name[];" while ensuring that the length of the TLV struct is + * unmodified by the conversion. + * In general, any new variable-length structs should simply use + * "type name[];" directly, rather than using HTT_STATS_VAR_LEN_ARRAY1. + * However, if there's a legitimate reason to make the new variable-length + * struct appear to not have a variable length, HTT_STATS_VAR_LEN_ARRAY1 + * can be used for this purpose. + */ + +#if defined(ATH_TARGET) || defined(__WINDOWS__) + #define HTT_STATS_VAR_LEN_ARRAY1(type, name) type name[1] +#else + /* + * Certain build settings of the Linux kernel don't allow zero-element + * arrays, and C++ doesn't allow zero-length empty structs. + * Confirm that there's no build that combines kernel with C++. + */ + #ifdef __cplusplus + #error unsupported combination of kernel and C plus plus + #endif + #define HTT_STATS_DUMMY_ZERO_LEN_FIELD struct {} dummy_zero_len_field + + #define HTT_STATS_VAR_LEN_ARRAY1(type, name) \ + union { \ + type name ## __first_elem; \ + struct { \ + HTT_STATS_DUMMY_ZERO_LEN_FIELD; \ + type name[]; \ + }; \ + } +#endif + + /** * htt_dbg_ext_stats_type - * The base structure for each of the stats_type is only for reference @@ -819,7 +856,7 @@ typedef enum { /* Length should be multiple of DWORD */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 data[1]; /* Can be variable length */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, data); /* Can be variable length */ } htt_stats_string_tlv; #define HTT_TX_PDEV_STATS_CMN_MAC_ID_M 0x000000ff @@ -1022,7 +1059,9 @@ typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 urrn_stats[1]; /* HTT_TX_PDEV_MAX_URRN_STATS */ + + /* HTT_TX_PDEV_MAX_URRN_STATS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, urrn_stats); } htt_stats_tx_pdev_underrun_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_underrun_tlv htt_tx_pdev_stats_urrn_tlv_v; @@ -1031,7 +1070,9 @@ typedef htt_stats_tx_pdev_underrun_tlv htt_tx_pdev_stats_urrn_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ + + /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, flush_errs); } htt_stats_tx_pdev_flush_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_flush_tlv htt_tx_pdev_stats_flush_tlv_v; @@ -1040,7 +1081,9 @@ typedef htt_stats_tx_pdev_flush_tlv htt_tx_pdev_stats_flush_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 mlo_abort_cnt[1]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ + + /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, mlo_abort_cnt); } htt_stats_tx_pdev_mlo_abort_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_mlo_abort_tlv htt_tx_pdev_stats_mlo_abort_tlv_v; @@ -1049,7 +1092,9 @@ typedef htt_stats_tx_pdev_mlo_abort_tlv htt_tx_pdev_stats_mlo_abort_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 mlo_txop_abort_cnt[1]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ + + /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, mlo_txop_abort_cnt); } htt_stats_tx_pdev_mlo_txop_abort_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_mlo_txop_abort_tlv @@ -1059,7 +1104,9 @@ typedef htt_stats_tx_pdev_mlo_txop_abort_tlv /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 sifs_status[1]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ + + /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sifs_status); } htt_stats_tx_pdev_sifs_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_sifs_tlv htt_tx_pdev_stats_sifs_tlv_v; @@ -1068,7 +1115,9 @@ typedef htt_stats_tx_pdev_sifs_tlv htt_tx_pdev_stats_sifs_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 phy_errs[1]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ + + /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, phy_errs); } htt_stats_tx_pdev_phy_err_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_phy_err_tlv htt_tx_pdev_stats_phy_err_tlv_v; @@ -1124,7 +1173,9 @@ typedef htt_stats_tx_pdev_ap_edca_params_stats_tlv /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 sifs_hist_status[1]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ + + /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sifs_hist_status); } htt_stats_tx_pdev_sifs_hist_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_sifs_hist_tlv htt_tx_pdev_stats_sifs_hist_tlv_v; @@ -1202,7 +1253,9 @@ typedef htt_stats_mu_ppdu_dist_tlv htt_pdev_mu_ppdu_dist_tlv_v; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 hist_bin_size; - A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ + + /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, tried_mpdu_cnt_hist); } htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv @@ -1233,6 +1286,7 @@ typedef htt_stats_pdev_ctrl_path_tx_stats_tlv htt_pdev_ctrl_path_tx_stats_tlv_v; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct _htt_tx_pdev_stats { htt_stats_tx_pdev_cmn_tlv cmn_tlv; htt_stats_tx_pdev_underrun_tlv underrun_tlv; @@ -1245,6 +1299,7 @@ typedef struct _htt_tx_pdev_stats { htt_stats_pdev_ctrl_path_tx_stats_tlv ctrl_path_tx_tlv; htt_stats_mu_ppdu_dist_tlv mu_ppdu_dist_tlv; } htt_tx_pdev_stats_t; +#endif /* ATH_TARGET */ /* == SOC ERROR STATS == */ @@ -1408,10 +1463,12 @@ typedef struct { * The target has an internal HW WAR mapping that it uses to keep * track of which HW WAR is WAR 0, which HW WAR is WAR 1, etc. */ - A_UINT32 hw_wars[1/*or more*/]; + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, hw_wars); } htt_stats_hw_war_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_hw_war_tlv htt_hw_war_stats_tlv; +/* provide properly-named macro */ +#define HTT_STATS_HW_WAR_MAC_ID_GET(word) (word & 0xff) /* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_ERROR * TLV_TAGS: @@ -1425,6 +1482,7 @@ typedef htt_stats_hw_war_tlv htt_hw_war_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct _htt_pdev_err_stats { htt_stats_hw_pdev_errs_tlv pdev_errs; htt_stats_hw_intr_misc_tlv misc_stats[1]; @@ -1432,6 +1490,7 @@ typedef struct _htt_pdev_err_stats { htt_stats_whal_tx_tlv whal_tx_stats; htt_stats_hw_war_tlv hw_war; } htt_hw_err_stats_t; +#endif /* ATH_TARGET */ /* ============ PEER STATS ============ */ @@ -1801,19 +1860,38 @@ typedef struct { htt_mac_addr mac_addr; A_UINT32 peer_flags; A_UINT32 qpeer_flags; + /* Dword 8 */ - A_UINT32 ml_peer_id_valid : 1, /* [0:0] */ - ml_peer_id : 12, /* [12:1] */ - link_idx : 8, /* [20:13] */ - use_ppe : 1, /* [21:21] */ - rsvd0 : 10; /* [31:22] */ + union { + A_UINT32 word__ml_peer_id_valid__ml_peer_id__link_idx__use_ppe; + struct { + A_UINT32 ml_peer_id_valid : 1, /* [0:0] */ + ml_peer_id : 12, /* [12:1] */ + link_idx : 8, /* [20:13] */ + use_ppe : 1, /* [21:21] */ + rsvd0 : 10; /* [31:22] */ + }; + }; + /* Dword 9 */ - A_UINT32 src_info : 12, /* [11:0] */ - rsvd1 : 20; /* [31:12] */ + union { + A_UINT32 word__src_info; + struct { + A_UINT32 src_info : 12, /* [11:0] */ + rsvd1 : 20; /* [31:12] */ + }; + }; } htt_stats_peer_details_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_details_tlv htt_peer_details_tlv; +#define HTT_STATS_PEER_DETAILS_ML_PEER_ID_VALID_GET(word) ((word >> 0) & 0x1) +#define HTT_STATS_PEER_DETAILS_ML_PEER_ID_GET(word) ((word >> 1) & 0xfff) +#define HTT_STATS_PEER_DETAILS_LINK_IDX_GET(word) ((word >> 13) & 0xff) +#define HTT_STATS_PEER_DETAILS_USE_PPE_GET(word) ((word >> 21) & 0x1) + +#define HTT_STATS_PEER_DETAILS_SRC_INFO_GET(word) ((word >> 0) & 0xfff) + typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 sw_peer_id; @@ -2187,6 +2265,7 @@ typedef htt_stats_peer_be_ofdma_stats_tlv htt_peer_be_ofdma_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct _htt_peer_stats { htt_stats_peer_stats_cmn_tlv cmn_tlv; @@ -2202,6 +2281,7 @@ typedef struct _htt_peer_stats { htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats; htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; } htt_peer_stats_t; +#endif /* ATH_TARGET */ /* =========== ACTIVE PEER LIST ========== */ @@ -2213,9 +2293,11 @@ typedef struct _htt_peer_stats { * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_peer_details_tlv peer_details[1]; } htt_active_peer_details_list_t; +#endif /* ATH_TARGET */ /* =========== MUMIMO HWQ stats =========== */ @@ -2296,6 +2378,7 @@ typedef htt_stats_tx_hwq_mumimo_cmn_stats_tlv htt_tx_hwq_mu_mimo_cmn_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { struct { htt_stats_tx_hwq_mumimo_cmn_stats_tlv cmn_tlv; @@ -2305,6 +2388,7 @@ typedef struct { htt_stats_tx_hwq_mumimo_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; } hwq[1]; } htt_tx_hwq_mu_mimo_stats_t; +#endif /* ATH_TARGET */ /* == TX HWQ STATS == */ #define HTT_TX_HWQ_STATS_CMN_MAC_ID_M 0x000000ff @@ -2405,8 +2489,11 @@ typedef htt_stats_tx_hwq_cmn_tlv htt_tx_hwq_stats_cmn_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 hist_intvl; - /** histogram of ppdu post to hwsch - > cmd status received */ - A_UINT32 difs_latency_hist[1]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ + /** difs_latency_hist: + * histogram of ppdu post to hwsch - > cmd status receive, + * HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, difs_latency_hist); } htt_stats_tx_hwq_difs_latency_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_hwq_difs_latency_tlv htt_tx_hwq_difs_latency_stats_tlv_v; @@ -2416,8 +2503,11 @@ typedef htt_stats_tx_hwq_difs_latency_tlv htt_tx_hwq_difs_latency_stats_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Histogram of sched cmd result */ - A_UINT32 cmd_result[1]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ + /** cmd_result: + * Histogram of sched cmd result, + * HTT_TX_HWQ_MAX_CMD_RESULT_STATS + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, cmd_result); } htt_stats_tx_hwq_cmd_result_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_hwq_cmd_result_tlv htt_tx_hwq_cmd_result_stats_tlv_v; @@ -2427,8 +2517,11 @@ typedef htt_stats_tx_hwq_cmd_result_tlv htt_tx_hwq_cmd_result_stats_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Histogram of various pause conitions */ - A_UINT32 cmd_stall_status[1]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */ + /** cmd_stall_status: + * Histogram of various pause conitions + * HTT_TX_HWQ_MAX_CMD_STALL_STATS + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, cmd_stall_status); } htt_stats_tx_hwq_cmd_stall_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_hwq_cmd_stall_tlv htt_tx_hwq_cmd_stall_stats_tlv_v; @@ -2438,8 +2531,11 @@ typedef htt_stats_tx_hwq_cmd_stall_tlv htt_tx_hwq_cmd_stall_stats_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Histogram of number of user fes result */ - A_UINT32 fes_result[1]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */ + /** fes_result: + * Histogram of number of user fes result, + * HTT_TX_HWQ_MAX_FES_RESULT_STATS + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fes_result); } htt_stats_tx_hwq_fes_status_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_hwq_fes_status_tlv htt_tx_hwq_fes_result_stats_tlv_v; @@ -2461,8 +2557,11 @@ typedef htt_stats_tx_hwq_fes_status_tlv htt_tx_hwq_fes_result_stats_tlv_v; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 hist_bin_size; - /** Histogram of number of mpdus on tried mpdu */ - A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ + /** tried_mpdu_cnt_hist: + * Histogram of number of mpdus on tried mpdu, + * HTT_TX_HWQ_TRIED_MPDU_CNT_HIST + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, tried_mpdu_cnt_hist); } htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv @@ -2482,8 +2581,11 @@ typedef htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv * */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Histogram of txop used cnt */ - A_UINT32 txop_used_cnt_hist[1]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */ + /** txop_used_cnt_hist: + * Histogram of txop used cnt, + * HTT_TX_HWQ_TXOP_USED_CNT_HIST + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, txop_used_cnt_hist); } htt_stats_tx_hwq_txop_used_cnt_hist_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_hwq_txop_used_cnt_hist_tlv @@ -2509,6 +2611,7 @@ typedef htt_stats_tx_hwq_txop_used_cnt_hist_tlv * buffer the HWQ ID is filled in mac_id__hwq_id, thus identifying each * HWQ distinctly. */ +#ifdef ATH_TARGET typedef struct _htt_tx_hwq_stats { htt_stats_string_tlv hwq_str_tlv; htt_stats_tx_hwq_cmn_tlv cmn_tlv; @@ -2519,6 +2622,7 @@ typedef struct _htt_tx_hwq_stats { htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv tried_mpdu_tlv; htt_stats_tx_hwq_txop_used_cnt_hist_tlv txop_used_tlv; } htt_tx_hwq_stats_t; +#endif /* ATH_TARGET */ /* == TX SELFGEN STATS == */ @@ -2923,12 +3027,14 @@ typedef htt_stats_txbf_ofdma_steer_stats_tlv htt_txbf_ofdma_steer_stats_tlv; * struct TLVs are deprecated, due to the need for restructuring these * stats into a variable length array */ +#ifdef ATH_TARGET typedef struct { /* DEPRECATED */ htt_stats_txbf_ofdma_ndpa_stats_tlv ofdma_ndpa_tlv; htt_stats_txbf_ofdma_ndp_stats_tlv ofdma_ndp_tlv; htt_stats_txbf_ofdma_brp_stats_tlv ofdma_brp_tlv; htt_stats_txbf_ofdma_steer_stats_tlv ofdma_steer_tlv; } htt_tx_pdev_txbf_ofdma_stats_t; +#endif /* ATH_TARGET */ typedef struct { /** 11AX HE OFDMA NDPA frame queued to the HW */ @@ -2956,7 +3062,7 @@ typedef struct { * had used. */ A_UINT32 arr_elem_size_ax_ndpa; - htt_txbf_ofdma_ax_ndpa_stats_elem_t ax_ndpa[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_ndpa_stats_elem_t, ax_ndpa); } htt_stats_txbf_ofdma_ax_ndpa_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_ax_ndpa_stats_tlv htt_txbf_ofdma_ax_ndpa_stats_tlv; @@ -2987,7 +3093,7 @@ typedef struct { * had used. */ A_UINT32 arr_elem_size_ax_ndp; - htt_txbf_ofdma_ax_ndp_stats_elem_t ax_ndp[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_ndp_stats_elem_t, ax_ndp); } htt_stats_txbf_ofdma_ax_ndp_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_ax_ndp_stats_tlv htt_txbf_ofdma_ax_ndp_stats_tlv; @@ -3023,7 +3129,7 @@ typedef struct { * had used. */ A_UINT32 arr_elem_size_ax_brp; - htt_txbf_ofdma_ax_brp_stats_elem_t ax_brp[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_brp_stats_elem_t, ax_brp); } htt_stats_txbf_ofdma_ax_brp_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_ax_brp_stats_tlv htt_txbf_ofdma_ax_brp_stats_tlv; @@ -3065,7 +3171,7 @@ typedef struct { * had used. */ A_UINT32 arr_elem_size_ax_steer; - htt_txbf_ofdma_ax_steer_stats_elem_t ax_steer[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_ax_steer_stats_elem_t, ax_steer); } htt_stats_txbf_ofdma_ax_steer_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_ax_steer_stats_tlv @@ -3112,7 +3218,7 @@ typedef struct { * had used. */ A_UINT32 arr_elem_size_be_ndpa; - htt_txbf_ofdma_be_ndpa_stats_elem_t be_ndpa[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_ndpa_stats_elem_t, be_ndpa); } htt_stats_txbf_ofdma_be_ndpa_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_be_ndpa_stats_tlv htt_txbf_ofdma_be_ndpa_stats_tlv; @@ -3143,7 +3249,7 @@ typedef struct { * had used. */ A_UINT32 arr_elem_size_be_ndp; - htt_txbf_ofdma_be_ndp_stats_elem_t be_ndp[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_ndp_stats_elem_t, be_ndp); } htt_stats_txbf_ofdma_be_ndp_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_be_ndp_stats_tlv htt_txbf_ofdma_be_ndp_stats_tlv; @@ -3179,7 +3285,7 @@ typedef struct { * had used */ A_UINT32 arr_elem_size_be_brp; - htt_txbf_ofdma_be_brp_stats_elem_t be_brp[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_brp_stats_elem_t, be_brp); } htt_stats_txbf_ofdma_be_brp_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_be_brp_stats_tlv htt_txbf_ofdma_be_brp_stats_tlv; @@ -3223,7 +3329,7 @@ typedef struct { * had used. */ A_UINT32 arr_elem_size_be_steer; - htt_txbf_ofdma_be_steer_stats_elem_t be_steer[1]; /* variable length */ + HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_be_steer_stats_elem_t, be_steer); } htt_stats_txbf_ofdma_be_steer_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_txbf_ofdma_be_steer_stats_tlv @@ -3560,6 +3666,7 @@ typedef htt_stats_tx_selfgen_be_sched_status_stats_tlv * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_tx_selfgen_cmn_stats_tlv cmn_tlv; htt_stats_tx_selfgen_ac_stats_tlv ac_tlv; @@ -3572,6 +3679,7 @@ typedef struct { htt_stats_tx_selfgen_be_err_stats_tlv be_err_tlv; htt_stats_tx_selfgen_be_sched_status_stats_tlv be_sched_status_tlv; } htt_tx_pdev_selfgen_stats_t; +#endif /* ATH_TARGET */ /* == TX MU STATS == */ @@ -3866,6 +3974,7 @@ typedef htt_stats_tx_pdev_mpdu_stats_tlv htt_tx_pdev_mpdu_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_tx_pdev_mu_mimo_stats_tlv mu_mimo_sch_stats_tlv[1]; /* WAL_TX_STATS_MAX_GROUP_SIZE */ htt_stats_tx_pdev_dl_mu_mimo_stats_tlv dl_mu_mimo_sch_stats_tlv[1]; @@ -3879,6 +3988,7 @@ typedef struct { htt_stats_tx_pdev_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; /* WAL_TX_STATS_MAX_NUM_USERS */ htt_stats_tx_pdev_mumimo_grp_stats_tlv mumimo_grp_stats_tlv; } htt_tx_pdev_mu_mimo_stats_t; +#endif /* ATH_TARGET */ /* == TX SCHED STATS == */ @@ -3915,8 +4025,10 @@ typedef struct { * The array is circular; it's unspecified which array element corresponds * to the most recent scheduler invocation, and which corresponds to * the (NUM_SCHED_ORDER_LOG-1) most recent scheduler invocation. + * + * HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ - A_UINT32 sched_order_su[1]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_order_su); } htt_stats_sched_txq_sched_order_su_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_sched_order_su_tlv htt_sched_txq_sched_order_su_tlv_v; @@ -3984,7 +4096,7 @@ typedef struct { * * Indexed by htt_sched_txq_sched_ineligibility_tlv_enum. */ - A_UINT32 sched_ineligibility[1]; + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_ineligibility); } htt_stats_sched_txq_sched_ineligibility_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_sched_ineligibility_tlv @@ -4183,7 +4295,9 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 gen_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ + + /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, gen_mpdu_end_reason); } htt_stats_tx_tqm_gen_mpdu_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_tqm_gen_mpdu_tlv htt_tx_tqm_gen_mpdu_stats_tlv_v; @@ -4193,7 +4307,9 @@ typedef htt_stats_tx_tqm_gen_mpdu_tlv htt_tx_tqm_gen_mpdu_stats_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 list_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ + + /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, list_mpdu_end_reason); } htt_stats_tx_tqm_list_mpdu_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_tqm_list_mpdu_tlv htt_tx_tqm_list_mpdu_stats_tlv_v; @@ -4203,7 +4319,9 @@ typedef htt_stats_tx_tqm_list_mpdu_tlv htt_tx_tqm_list_mpdu_stats_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 list_mpdu_cnt_hist[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ + + /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, list_mpdu_cnt_hist); } htt_stats_tx_tqm_list_mpdu_cnt_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_tqm_list_mpdu_cnt_tlv htt_tx_tqm_list_mpdu_cnt_tlv_v; @@ -4347,6 +4465,7 @@ typedef htt_stats_tx_tqm_error_stats_tlv htt_tx_tqm_error_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_tx_tqm_cmn_tlv cmn_tlv; htt_stats_tx_tqm_error_stats_tlv err_tlv; @@ -4355,6 +4474,7 @@ typedef struct { htt_stats_tx_tqm_list_mpdu_cnt_tlv list_mpdu_cnt_tlv; htt_stats_tx_tqm_pdev_tlv tqm_pdev_stats_tlv; } htt_tx_tqm_pdev_stats_t; +#endif /* ATH_TARGET */ /* == TQM CMDQ stats == */ #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M 0x000000ff @@ -4416,12 +4536,14 @@ typedef htt_stats_tx_tqm_cmdq_status_tlv htt_tx_tqm_cmdq_status_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { struct { htt_stats_string_tlv cmdq_str_tlv; htt_stats_tx_tqm_cmdq_status_tlv status_tlv; } q[1]; } htt_tx_tqm_cmdq_stats_t; +#endif /* ATH_TARGET */ /* == TX-DE STATS == */ @@ -4584,7 +4706,7 @@ typedef htt_stats_tx_de_compl_stats_tlv htt_tx_de_compl_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - A_UINT32 fw2wbm_ring_full_hist[1]; + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fw2wbm_ring_full_hist); } htt_stats_tx_de_fw2wbm_ring_full_hist_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_de_fw2wbm_ring_full_hist_tlv @@ -4667,6 +4789,7 @@ typedef htt_stats_rx_ring_stats_tlv htt_rx_fw_ring_stats_tlv_v; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_tx_de_cmn_tlv cmn_tlv; htt_stats_tx_de_fw2wbm_ring_full_hist_tlv fw2wbm_hist_tlv; @@ -4678,6 +4801,7 @@ typedef struct { htt_stats_tx_de_enqueue_discard_tlv enqueue_discard_tlv; htt_stats_tx_de_compl_stats_tlv comp_status_tlv; } htt_tx_de_stats_t; +#endif /* ATH_TARGET */ /* == RING-IF STATS == */ /* DWORD num_elems__prefetch_tail_idx */ @@ -4865,6 +4989,7 @@ typedef htt_stats_ring_if_cmn_tlv htt_ring_if_cmn_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_ring_if_cmn_tlv cmn_tlv; /** Variable based on the Number of records. */ @@ -4873,6 +4998,7 @@ typedef struct { htt_stats_ring_if_tlv ring_tlv; } r[1]; } htt_ring_if_stats_t; +#endif /* ATH_TARGET */ /* == SFM STATS == */ @@ -4882,7 +5008,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; /** Number of DWORDS used per user and per client */ - A_UINT32 dwords_used_by_user_n[1]; + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, dwords_used_by_user_n); } htt_stats_sfm_client_user_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sfm_client_user_tlv htt_sfm_client_user_tlv_v; @@ -4957,6 +5083,7 @@ typedef htt_stats_sfm_cmn_tlv htt_sfm_cmn_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_sfm_cmn_tlv cmn_tlv; /** Variable based on the Number of records. */ @@ -4966,6 +5093,7 @@ typedef struct { htt_stats_sfm_client_user_tlv user_tlv; } r[1]; } htt_sfm_stats_t; +#endif /* ATH_TARGET */ /* == SRNG STATS == */ /* DWORD mac_id__ring_id__arena__ep */ @@ -5193,6 +5321,7 @@ typedef htt_stats_sring_cmn_tlv htt_sring_cmn_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_sring_cmn_tlv cmn_tlv; /** Variable based on the Number of records */ @@ -5201,6 +5330,7 @@ typedef struct { htt_stats_sring_stats_tlv sring_stats_tlv; } r[1]; } htt_sring_stats_t; +#endif /* ATH_TARGET */ /* == PDEV TX RATE CTRL STATS == */ @@ -5551,12 +5681,14 @@ typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_tx_pdev_rate_stats_tlv rate_tlv; htt_stats_tx_pdev_be_rate_stats_tlv rate_be_tlv; htt_stats_tx_pdev_sawf_rate_stats_tlv rate_sawf_tlv; htt_stats_tx_pdev_ppdu_dur_tlv tx_ppdu_dur_tlv; } htt_tx_pdev_rate_stats_t; +#endif /* ATH_TARGET */ /* == PDEV RX RATE CTRL STATS == */ @@ -5822,10 +5954,12 @@ typedef htt_stats_rx_pdev_ppdu_dur_tlv htt_rx_pdev_ppdu_dur_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_pdev_rate_stats_tlv rate_tlv; htt_stats_rx_pdev_ppdu_dur_tlv rx_ppdu_dur_tlv; } htt_rx_pdev_rate_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -5868,9 +6002,11 @@ typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_pdev_rate_ext_stats_tlv rate_tlv; } htt_rx_pdev_rate_ext_stats_t; +#endif /* ATH_TARGET */ #define HTT_STATS_CMN_MAC_ID_M 0x000000ff #define HTT_STATS_CMN_MAC_ID_S 0 @@ -5955,9 +6091,11 @@ typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_pdev_ul_trig_stats_tlv ul_trigger_tlv; } htt_rx_pdev_ul_trigger_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -6035,9 +6173,11 @@ typedef htt_stats_rx_pdev_be_ul_trig_stats_tlv * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_pdev_be_ul_trig_stats_tlv ul_trigger_tlv; } htt_rx_pdev_be_ul_trigger_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -6233,10 +6373,12 @@ typedef htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv ul_mumimo_trig_tlv; htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv ul_mumimo_trig_be_tlv; } htt_rx_pdev_ul_mumimo_trig_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -6277,8 +6419,11 @@ typedef htt_stats_rx_soc_fw_stats_tlv htt_rx_soc_fw_stats_tlv; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Num ring empty encountered */ - A_UINT32 refill_ring_empty_cnt[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ + /** refill_ring_empty_cnt: + * Num ring empty encountered, + * HTT_RX_STATS_REFILL_MAX_RING + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, refill_ring_empty_cnt); } htt_stats_rx_soc_fw_refill_ring_empty_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_soc_fw_refill_ring_empty_tlv @@ -6289,8 +6434,11 @@ typedef htt_stats_rx_soc_fw_refill_ring_empty_tlv /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Num total buf refilled from refill ring */ - A_UINT32 refill_ring_num_refill[1]; /* HTT_RX_STATS_REFILL_MAX_RING */ + /** refill_ring_num_refill: + * Num total buf refilled from refill ring, + * HTT_RX_STATS_REFILL_MAX_RING + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, refill_ring_num_refill); } htt_stats_rx_soc_fw_refill_ring_num_refill_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_soc_fw_refill_ring_num_refill_tlv @@ -6334,8 +6482,10 @@ typedef struct { * for each of the htt_rx_rxdma_error_code_enum values, up to but not including * MAX_ERR_CODE. The host should ignore any array elements whose * indices are >= the MAX_ERR_CODE value the host was compiled with. + * + * HTT_RX_RXDMA_MAX_ERR_CODE */ - A_UINT32 rxdma_err[1]; /* HTT_RX_RXDMA_MAX_ERR_CODE */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, rxdma_err); } htt_stats_rx_refill_rxdma_err_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_refill_rxdma_err_tlv @@ -6379,8 +6529,10 @@ typedef struct { * for each of the htt_rx_reo_error_code_enum values, up to but not including * MAX_ERR_CODE. The host should ignore any array elements whose * indices are >= the MAX_ERR_CODE value the host was compiled with. + * + * HTT_RX_REO_MAX_ERR_CODE */ - A_UINT32 reo_err[1]; /* HTT_RX_REO_MAX_ERR_CODE */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, reo_err); } htt_stats_rx_refill_reo_err_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_refill_reo_err_tlv @@ -6390,6 +6542,7 @@ typedef htt_stats_rx_refill_reo_err_tlv * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_soc_fw_stats_tlv fw_tlv; htt_stats_rx_soc_fw_refill_ring_empty_tlv fw_refill_ring_empty_tlv; @@ -6398,6 +6551,7 @@ typedef struct { htt_stats_rx_refill_rxdma_err_tlv fw_refill_ring_num_rxdma_err_tlv; htt_stats_rx_refill_reo_err_tlv fw_refill_ring_num_reo_err_tlv; } htt_rx_soc_stats_t; +#endif /* ATH_TARGET */ /* == RX PDEV STATS == */ #define HTT_RX_PDEV_FW_STATS_MAC_ID_M 0x000000ff @@ -6602,8 +6756,11 @@ typedef htt_stats_rx_pdev_fw_stats_phy_err_tlv htt_rx_pdev_fw_stats_phy_err_tlv; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Num error MPDU for each RxDMA error type */ - A_UINT32 fw_ring_mpdu_err[1]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ + /** fw_ring_mpdu_err: + * Num error MPDU for each RxDMA error type, + * HTT_RX_STATS_RXDMA_MAX_ERR + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fw_ring_mpdu_err); } htt_stats_rx_pdev_fw_ring_mpdu_err_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_fw_ring_mpdu_err_tlv @@ -6614,8 +6771,11 @@ typedef htt_stats_rx_pdev_fw_ring_mpdu_err_tlv /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Num MPDU dropped */ - A_UINT32 fw_mpdu_drop[1]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ + /** fw_mpdu_drop: + * Num MPDU dropped, + * HTT_RX_STATS_FW_DROP_REASON_MAX + */ + HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, fw_mpdu_drop); } htt_stats_rx_pdev_fw_mpdu_drop_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_fw_mpdu_drop_tlv htt_rx_pdev_fw_mpdu_drop_tlv_v; @@ -6633,22 +6793,26 @@ typedef htt_stats_rx_pdev_fw_mpdu_drop_tlv htt_rx_pdev_fw_mpdu_drop_tlv_v; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { - htt_rx_soc_stats_t soc_stats; + htt_rx_soc_stats_t soc_stats; htt_stats_rx_pdev_fw_stats_tlv fw_stats_tlv; htt_stats_rx_pdev_fw_ring_mpdu_err_tlv fw_ring_mpdu_err_tlv; htt_stats_rx_pdev_fw_mpdu_drop_tlv fw_ring_mpdu_drop; htt_stats_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv; } htt_rx_pdev_stats_t; +#endif /* ATH_TARGET */ /* STATS_TYPE : HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS * TLV_TAGS: * - HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG * */ +#ifdef ATH_TARGET typedef struct { htt_stats_peer_ctrl_path_txrx_stats_tlv peer_ctrl_path_txrx_stats_tlv; } htt_ctrl_path_txrx_stats_t; +#endif /* ATH_TARGET */ #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) @@ -6719,7 +6883,7 @@ typedef struct { * Then the pdev_cca_stats[0] element contains the oldest CCA stats * and pdev_cca_stats[N-1] will have the most recent CCA stats. */ - htt_stats_pdev_cca_counters_tlv cca_hist_tlv[1]; + HTT_STATS_VAR_LEN_ARRAY1(htt_stats_pdev_cca_counters_tlv, cca_hist_tlv); } htt_pdev_cca_stats_hist_tlv; typedef struct { @@ -6855,7 +7019,7 @@ typedef struct { A_UINT32 pdev_id; A_UINT32 num_sessions; - htt_stats_pdev_twt_session_tlv twt_session[1]; + HTT_STATS_VAR_LEN_ARRAY1(htt_stats_pdev_twt_session_tlv, twt_session); } htt_stats_pdev_twt_sessions_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_twt_sessions_tlv htt_pdev_stats_twt_sessions_tlv; @@ -6869,9 +7033,11 @@ typedef htt_stats_pdev_twt_sessions_tlv htt_pdev_stats_twt_sessions_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_pdev_twt_session_tlv twt_sessions[1]; } htt_pdev_twt_sessions_stats_t; +#endif /* ATH_TARGET */ typedef enum { /* Global link descriptor queued in REO */ @@ -6927,9 +7093,11 @@ typedef htt_stats_rx_reo_resource_stats_tlv htt_rx_reo_resource_stats_tlv_v; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_reo_resource_stats_tlv reo_resource_stats; } htt_soc_reo_resource_stats_t; +#endif /* ATH_TARGET */ /* == TX SOUNDING STATS == */ @@ -7147,9 +7315,11 @@ typedef htt_stats_tx_sounding_stats_tlv htt_tx_sounding_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_tx_sounding_stats_tlv sounding_tlv; } htt_tx_sounding_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -7279,9 +7449,11 @@ typedef htt_stats_pdev_obss_pd_tlv htt_pdev_obss_pd_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_pdev_obss_pd_tlv obss_pd_stat; } htt_pdev_obss_pd_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -7321,6 +7493,7 @@ typedef htt_stats_ring_backpressure_stats_tlv htt_ring_backpressure_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_sring_cmn_tlv cmn_tlv; struct { @@ -7328,6 +7501,7 @@ typedef struct { htt_stats_ring_backpressure_stats_tlv backpressure_stats_tlv; } r[1]; /* variable-length array */ } htt_ring_backpressure_stats_t; +#endif /* ATH_TARGET */ #define HTT_LATENCY_PROFILE_MAX_HIST 3 #define HTT_STATS_MAX_PROF_STATS_NAME_LEN 32 @@ -7415,11 +7589,13 @@ typedef htt_stats_latency_cnt_tlv htt_latency_prof_cnt_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_latency_prof_stats_tlv latency_prof_stat; htt_stats_latency_ctx_tlv latency_ctx_stat; htt_stats_latency_cnt_tlv latency_cnt_stat; } htt_soc_latency_stats_t; +#endif /* ATH_TARGET */ #define HTT_RX_MAX_PEAK_OCCUPANCY_INDEX 10 #define HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX 10 @@ -7544,9 +7720,11 @@ typedef htt_stats_rx_fse_stats_tlv htt_rx_fse_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_rx_fse_stats_tlv rx_fse_stats; } htt_rx_fse_stats_t; +#endif /* ATH_TARGET */ #define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 #define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 /* 20, 40, 80, 160, 320 */ @@ -7661,13 +7839,17 @@ typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_pdev_tx_rate_txbf_stats_tlv txbf_rate_stats; } htt_pdev_txbf_rate_stats_t; +#endif /* ATH_TARGET */ +#ifdef ATH_TARGET typedef struct { htt_stats_per_rate_stats_tlv per_stats; } htt_tx_pdev_per_stats_t; +#endif /* ATH_TARGET */ typedef enum { HTT_ULTRIG_QBOOST_TRIGGER = 0, @@ -7784,9 +7966,11 @@ typedef htt_stats_sta_ul_ofdma_stats_tlv htt_sta_ul_ofdma_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_sta_ul_ofdma_stats_tlv ul_ofdma_sta_stats; } htt_sta_11ax_ul_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -7824,9 +8008,11 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_vdev_rtt_resp_stats_tlv htt_vdev_rtt_resp_stats_tlv; +#ifdef ATH_TARGET typedef struct { htt_stats_vdev_rtt_resp_stats_tlv vdev_rtt_resp_stats; } htt_vdev_rtt_resp_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -7858,9 +8044,11 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_vdev_rtt_init_stats_tlv htt_vdev_rtt_init_stats_tlv; +#ifdef ATH_TARGET typedef struct { htt_stats_vdev_rtt_init_stats_tlv vdev_rtt_init_stats; } htt_vdev_rtt_init_stats_t; +#endif /* ATH_TARGET */ #define HTT_STATS_MAX_SCH_CMD_RESULT 25 @@ -8197,12 +8385,14 @@ typedef struct { * HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG * HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG */ +#ifdef ATH_TARGET typedef struct { htt_stats_pdev_rtt_resp_stats_tlv pdev_rtt_resp_stats; htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv pdev_rtt_tbr_selfgen_queued_stats; htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv pdev_rtt_tbr_cmd_result_stats; } htt_pdev_rtt_resp_stats_t; +#endif /* ATH_TARGET */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -8371,10 +8561,12 @@ typedef struct { * HTT_STATS_PDEV_RTT_INIT_STATS_TAG * HTT_STATS_PDEV_RTT_HW_STATS_TAG */ +#ifdef ATH_TARGET typedef struct { htt_stats_pdev_rtt_init_stats_tlv pdev_rtt_init_stats; htt_stats_pdev_rtt_hw_stats_tlv pdev_rtt_hw_stats; } htt_pdev_rtt_init_stats_t; +#endif /* ATH_TARGET */ /* STATS_TYPE : HTT_DBG_EXT_PKTLOG_AND_HTT_RING_STATS @@ -8420,6 +8612,9 @@ typedef htt_stats_pktlog_and_htt_ring_stats_tlv #define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_GET(_var) \ (((_var) & HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M) >> \ HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S) +#define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_ASYNC_LOCK_GET(_var) \ + HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_GET(_var) + #define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ do { \ @@ -8431,6 +8626,8 @@ typedef htt_stats_pktlog_and_htt_ring_stats_tlv #define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_GET(_var) \ (((_var) & HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M) >> \ HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S) +#define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_SYNC_LOCK_GET(_var) \ + HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_GET(_var) #define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ do { \ @@ -8442,6 +8639,8 @@ typedef htt_stats_pktlog_and_htt_ring_stats_tlv #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_GET(_var) \ (((_var) & HTT_DLPAGER_TOTAL_LOCKED_PAGES_M) >> \ HTT_DLPAGER_TOTAL_LOCKED_PAGES_S) +#define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_TOTAL_LOCKED_PAGES_GET(_var) \ + HTT_DLPAGER_TOTAL_LOCKED_PAGES_GET(_var) #define HTT_DLPAGER_TOTAL_LOCKED_PAGES_SET(_var, _val) \ do { \ @@ -8453,6 +8652,8 @@ typedef htt_stats_pktlog_and_htt_ring_stats_tlv #define HTT_DLPAGER_TOTAL_FREE_PAGES_GET(_var) \ (((_var) & HTT_DLPAGER_TOTAL_FREE_PAGES_M) >> \ HTT_DLPAGER_TOTAL_FREE_PAGES_S) +#define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_TOTAL_FREE_PAGES_GET(_var) \ + HTT_DLPAGER_TOTAL_FREE_PAGES_GET(_var) #define HTT_DLPAGER_TOTAL_FREE_PAGES_SET(_var, _val) \ do { \ @@ -8464,6 +8665,8 @@ typedef htt_stats_pktlog_and_htt_ring_stats_tlv #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(_var) \ (((_var) & HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M) >> \ HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S) +#define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_LAST_LOCKED_PAGE_IDX_GET(_var) \ + HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(_var) #define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_SET(_var, _val) \ do { \ @@ -8475,6 +8678,8 @@ typedef htt_stats_pktlog_and_htt_ring_stats_tlv #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(_var) \ (((_var) & HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M) >> \ HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S) +#define HTT_STATS_DLPAGER_STATS_DL_PAGER_STATS_LAST_UNLOCKED_PAGE_IDX_GET(_var) \ + HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(_var) #define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_SET(_var, _val) \ do { \ @@ -8497,17 +8702,37 @@ typedef struct{ * sync_lock : 8, * reserved : 16; */ - A_UINT32 msg_dword_1; + union { + struct { + A_UINT32 async_lock: 8, + sync_lock: 8, + reserved1: 16; + + }; + A_UINT32 msg_dword_1; + }; /** mst_dword_2 bitfields: * total_locked_pages : 16, * total_free_pages : 16; */ - A_UINT32 msg_dword_2; + union { + struct { + A_UINT32 total_locked_pages: 16, + total_free_pages: 16; + }; + A_UINT32 msg_dword_2; + }; /** msg_dword_3 bitfields: * last_locked_page_idx : 16, * last_unlocked_page_idx : 16; */ - A_UINT32 msg_dword_3; + union { + struct { + A_UINT32 last_locked_page_idx: 16, + last_unlocked_page_idx: 16; + }; + A_UINT32 msg_dword_3; + }; struct { A_UINT32 page_num; @@ -8532,6 +8757,7 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_dlpager_stats_tlv htt_dlpager_stats_t; + /*======= PHY STATS ====================*/ /* * STATS TYPE : HTT_DBG_EXT_PHY_COUNTERS_AND_PHY_STATS @@ -8937,6 +9163,9 @@ typedef htt_stats_phy_reset_counters_tlv htt_phy_reset_counters_tlv; #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \ (((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \ HTT_PHY_TPC_STATS_CTL_REGION_GRP_S) +/* provide properly-named macro */ +#define HTT_STATS_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \ + HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) #define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \ @@ -8950,6 +9179,9 @@ typedef htt_stats_phy_reset_counters_tlv htt_phy_reset_counters_tlv; #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \ (((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \ HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S) +/* provide properly-named macro */ +#define HTT_STATS_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \ + HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) #define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \ @@ -8963,6 +9195,9 @@ typedef htt_stats_phy_reset_counters_tlv htt_phy_reset_counters_tlv; #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \ (((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \ HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S) +/* provide properly-named macro */ +#define HTT_STATS_PHY_TPC_STATS_ARRAY_GAIN_CAP_EXT2_ENABLED_GET(_var) \ + HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) #define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \ @@ -8976,6 +9211,9 @@ typedef htt_stats_phy_reset_counters_tlv htt_phy_reset_counters_tlv; #define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \ (((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \ HTT_PHY_TPC_STATS_CTL_FLAG_S) +/* provide properly-named macro */ +#define HTT_STATS_PHY_TPC_STATS_CTL_FLAG_GET(_var) \ + HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) #define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \ @@ -9056,6 +9294,7 @@ typedef htt_stats_phy_tpc_stats_tlv htt_phy_tpc_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_phy_counters_tlv phy_counters; htt_stats_phy_stats_tlv phy_stats; @@ -9063,31 +9302,61 @@ typedef struct { htt_stats_phy_reset_stats_tlv phy_reset_stats; htt_stats_phy_tpc_stats_tlv phy_tpc_stats; } htt_phy_counters_and_phy_stats_t; +#endif /* ATH_TARGET */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_soc_txrx_stats_common_tlv soc_common_stats; htt_stats_vdev_txrx_stats_hw_stats_tlv vdev_hw_stats[1/*or more*/]; } htt_vdevs_txrx_stats_t; +#endif /* ATH_TARGET */ typedef struct { - A_UINT32 - success: 16, - fail: 16; + union { + A_UINT32 word32; + struct { + A_UINT32 + success: 16, + fail: 16; + }; + }; } htt_stats_strm_gen_mpdus_cntr_t; typedef struct { /* MSDU queue identification */ - A_UINT32 - peer_id: 16, - tid: 4, /* only TIDs 0-7 actually expected to be used */ - htt_qtype: 4, /* refer to HTT_MSDUQ_INDEX */ - reserved: 8; + union { + A_UINT32 word32; + struct { + A_UINT32 + peer_id: 16, + tid: 4, /* only TIDs 0-7 actually expected to be used */ + htt_qtype: 4, /* refer to HTT_MSDUQ_INDEX */ + reserved: 8; + }; + }; } htt_stats_strm_msdu_queue_id; +#define HTT_STATS_STRM_GEN_MPDUS_QUEUE_ID_PEER_ID_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_QUEUE_ID_TID_GET(word) \ + ((word >> 16) & 0xf) +#define HTT_STATS_STRM_GEN_MPDUS_QUEUE_ID_HTT_QTYPE_GET(word) \ + ((word >> 20) & 0xf) + +#define HTT_STATS_STRM_GEN_MPDUS_SVC_INTERVAL_SUCCESS_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_SVC_INTERVAL_FAIL_GET(word) \ + ((word >> 16) & 0xffff) + +#define HTT_STATS_STRM_GEN_MPDUS_BURST_SIZE_SUCCESS_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_BURST_SIZE_FAIL_GET(word) \ + ((word >> 16) & 0xffff) + typedef struct { htt_tlv_hdr_t tlv_hdr; htt_stats_strm_msdu_queue_id queue_id; @@ -9101,44 +9370,97 @@ typedef struct { htt_tlv_hdr_t tlv_hdr; htt_stats_strm_msdu_queue_id queue_id; struct { - A_UINT32 - timestamp_prior_ms: 16, - timestamp_now_ms: 16; - A_UINT32 - interval_spec_ms: 16, - margin_ms: 16; + union { + A_UINT32 timestamp_prior__timestamp_now__word; + struct { + A_UINT32 + timestamp_prior_ms: 16, + timestamp_now_ms: 16; + }; + }; + union { + A_UINT32 interval_spec__margin__word; + struct { + A_UINT32 + interval_spec_ms: 16, + margin_ms: 16; + }; + }; } svc_interval; struct { - A_UINT32 - /* consumed_bytes_orig: - * Raw count (actually estimate) of how many bytes were removed - * from the MSDU queue by the GEN_MPDUS operation. - */ - consumed_bytes_orig: 16, - /* consumed_bytes_final: - * Adjusted count of removed bytes that incorporates normalizing - * by the actual service interval compared to the expected - * service interval. - * This allows the burst size computation to be independent of - * whether the target is doing GEN_MPDUS at only the service - * interval, or substantially more often than the service - * interval. - * consumed_bytes_final = consumed_bytes_orig / - * (svc_interval / ref_svc_interval) - */ - consumed_bytes_final: 16; - A_UINT32 - remaining_bytes: 16, - reserved: 16; - A_UINT32 - burst_size_spec: 16, - margin_bytes: 16; + union { + A_UINT32 consumed_bytes_orig__consumed_bytes_final__word; + struct { + A_UINT32 + /* consumed_bytes_orig: + * Raw count (actually estimate) of how many bytes were + * removed from the MSDU queue by the GEN_MPDUS operation. + */ + consumed_bytes_orig: 16, + /* consumed_bytes_final: + * Adjusted count of removed bytes that incorporates + * normalizing by the actual service interval compared to + * the expected service interval. + * This allows the burst size computation to be independent + * of whether the target is doing GEN_MPDUS at only the + * service interval, or substantially more often than the + * service interval. + * consumed_bytes_final = consumed_bytes_orig / + * (svc_interval / ref_svc_interval) + */ + consumed_bytes_final: 16; + }; + }; + union { + A_UINT32 remaining_bytes__word; + struct { + A_UINT32 + remaining_bytes: 16, + reserved: 16; + }; + }; + union { + A_UINT32 burst_size_spec__margin_bytes__word; + struct { + A_UINT32 + burst_size_spec: 16, + margin_bytes: 16; + }; + }; } burst_size; } htt_stats_strm_gen_mpdus_details_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_strm_gen_mpdus_details_tlv htt_stats_strm_gen_mpdus_details_tlv_t; +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_QUEUE_ID_PEER_ID_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_QUEUE_ID_TID_GET(word) \ + ((word >> 16) & 0xf) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_QUEUE_ID_HTT_QTYPE_GET(word) \ + ((word >> 20) & 0xf) + +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_TIMESTAMP_PRIOR_MS_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_TIMESTAMP_NOW_MS_GET(word) \ + ((word >> 16) & 0xffff) + +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_INTERVAL_SPEC_MS_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_SVC_INTERVAL_MARGIN_MS_GET(word) \ + ((word >> 16) & 0xffff) + +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_CONSUMED_BYTES_ORIG_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_CONSUMED_BYTES_FINAL_GET(word) \ + ((word >> 16) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_REMAINING_BYTES_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_BURST_SIZE_SPEC_GET(word) \ + ((word >> 0) & 0xffff) +#define HTT_STATS_STRM_GEN_MPDUS_DETAILS_BURST_SIZE_MARGIN_BYTES_GET(word) \ + ((word >> 16) & 0xffff) + typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 reset_count; @@ -9251,6 +9573,8 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_puncture_stats_tlv htt_pdev_puncture_stats_tlv; +#define HTT_STATS_PDEV_PUNCTURE_STATS_MAC_ID_GET(word) ((word >> 0) & 0xff) + enum { HTT_STATS_CAL_PROF_COLD_BOOT = 0, HTT_STATS_CAL_PROF_FULL_CHAN_SWITCH = 1, @@ -9398,6 +9722,9 @@ typedef struct { #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ (((_var) & HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M) >> \ HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ + HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_SET(_var, _val) \ do { \ @@ -9409,6 +9736,9 @@ typedef struct { #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) \ (((_var) & HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M) >> \ HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) \ + HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) #define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_SET(_var, _val) \ do { \ @@ -9420,6 +9750,9 @@ typedef struct { #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) \ (((_var) & HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M) >> \ HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) \ + HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_SET(_var, _val) \ do { \ @@ -9474,6 +9807,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_VALID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_VALID_M) >> \ HTT_ML_LINK_INFO_VALID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_VALID_GET(_var) \ + HTT_ML_LINK_INFO_VALID_GET(_var) #define HTT_ML_LINK_INFO_VALID_SET(_var, _val) \ do { \ @@ -9485,6 +9821,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_ACTIVE_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_ACTIVE_M) >> \ HTT_ML_LINK_INFO_ACTIVE_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_ACTIVE_GET(_var) \ + HTT_ML_LINK_INFO_ACTIVE_GET(_var) #define HTT_ML_LINK_INFO_ACTIVE_SET(_var, _val) \ do { \ @@ -9496,6 +9835,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_PRIMARY_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_PRIMARY_M) >> \ HTT_ML_LINK_INFO_PRIMARY_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_PRIMARY_GET(_var) \ + HTT_ML_LINK_INFO_PRIMARY_GET(_var) #define HTT_ML_LINK_INFO_PRIMARY_SET(_var, _val) \ do { \ @@ -9507,6 +9849,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_ASSOC_LINK_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_ASSOC_LINK_M) >> \ HTT_ML_LINK_INFO_ASSOC_LINK_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_ASSOC_LINK_GET(_var) \ + HTT_ML_LINK_INFO_ASSOC_LINK_GET(_var) #define HTT_ML_LINK_INFO_ASSOC_LINK_SET(_var, _val) \ do { \ @@ -9518,6 +9863,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_CHIP_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_CHIP_ID_M) >> \ HTT_ML_LINK_INFO_CHIP_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_CHIP_ID_GET(_var) \ + HTT_ML_LINK_INFO_CHIP_ID_GET(_var) #define HTT_ML_LINK_INFO_CHIP_ID_SET(_var, _val) \ do { \ @@ -9529,6 +9877,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_IEEE_LINK_ID_M) >> \ HTT_ML_LINK_INFO_IEEE_LINK_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_IEEE_LINK_ID_GET(_var) \ + HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(_var) #define HTT_ML_LINK_INFO_IEEE_LINK_ID_SET(_var, _val) \ do { \ @@ -9540,6 +9891,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_HW_LINK_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_HW_LINK_ID_M) >> \ HTT_ML_LINK_INFO_HW_LINK_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_HW_LINK_ID_GET(_var) \ + HTT_ML_LINK_INFO_HW_LINK_ID_GET(_var) #define HTT_ML_LINK_INFO_HW_LINK_ID_SET(_var, _val) \ do { \ @@ -9551,6 +9905,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M) >> \ HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_LOGICAL_LINK_ID_GET(_var) \ + HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(_var) #define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_SET(_var, _val) \ do { \ @@ -9562,6 +9919,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_MASTER_LINK_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_MASTER_LINK_M) >> \ HTT_ML_LINK_INFO_MASTER_LINK_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_MASTER_LINK_GET(_var) \ + HTT_ML_LINK_INFO_MASTER_LINK_GET(_var) #define HTT_ML_LINK_INFO_MASTER_LINK_SET(_var, _val) \ do { \ @@ -9573,6 +9933,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_ANCHOR_LINK_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_ANCHOR_LINK_M) >> \ HTT_ML_LINK_INFO_ANCHOR_LINK_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_ANCHOR_LINK_GET(_var) \ + HTT_ML_LINK_INFO_ANCHOR_LINK_GET(_var) #define HTT_ML_LINK_INFO_ANCHOR_LINK_SET(_var, _val) \ do { \ @@ -9584,6 +9947,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_INITIALIZED_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_INITIALIZED_M) >> \ HTT_ML_LINK_INFO_INITIALIZED_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_INITIALIZED_GET(_var) \ + HTT_ML_LINK_INFO_INITIALIZED_GET(_var) #define HTT_ML_LINK_INFO_INITIALIZED_SET(_var, _val) \ do { \ @@ -9595,6 +9961,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_SW_PEER_ID_M) >> \ HTT_ML_LINK_INFO_SW_PEER_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_SW_PEER_ID_GET(_var) \ + HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) #define HTT_ML_LINK_INFO_SW_PEER_ID_SET(_var, _val) \ do { \ @@ -9606,6 +9975,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_VDEV_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_VDEV_ID_M) >> \ HTT_ML_LINK_INFO_VDEV_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_LINK_INFO_DETAILS_VDEV_ID_GET(_var) \ + HTT_ML_LINK_INFO_VDEV_ID_GET(_var) #define HTT_ML_LINK_INFO_VDEV_ID_SET(_var, _val) \ do { \ @@ -9680,6 +10052,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_NUM_LINKS_M) >> \ HTT_ML_PEER_DETAILS_NUM_LINKS_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ + HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) #define HTT_ML_PEER_DETAILS_NUM_LINKS_SET(_var, _val) \ do { \ @@ -9691,6 +10066,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_ML_PEER_ID_M) >> \ HTT_ML_PEER_DETAILS_ML_PEER_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) \ + HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) #define HTT_ML_PEER_DETAILS_ML_PEER_ID_SET(_var, _val) \ do { \ @@ -9702,6 +10080,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M) >> \ HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) \ + HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) #define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_SET(_var, _val) \ do { \ @@ -9713,6 +10094,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M) >> \ HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) \ + HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) #define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_SET(_var, _val) \ do { \ @@ -9724,6 +10108,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M) >> \ HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) \ + HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) #define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_SET(_var, _val) \ do { \ @@ -9735,6 +10122,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_NON_STR_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_NON_STR_M) >> \ HTT_ML_PEER_DETAILS_NON_STR_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_NON_STR_GET(_var) \ + HTT_ML_PEER_DETAILS_NON_STR_GET(_var) #define HTT_ML_PEER_DETAILS_NON_STR_SET(_var, _val) \ do { \ @@ -9746,6 +10136,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_M) >> \ HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_GET(_var) \ + HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_GET(_var) #define HTT_ML_PEER_DETAILS_IS_EMLSR_ACTIVE_SET(_var, _val) \ do { \ @@ -9772,6 +10165,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_IS_STA_KO_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_IS_STA_KO_M) >> \ HTT_ML_PEER_DETAILS_IS_STA_KO_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_IS_STA_KO_GET(_var) \ + HTT_ML_PEER_DETAILS_IS_STA_KO_GET(_var) #define HTT_ML_PEER_DETAILS_IS_STA_KO_SET(_var, _val) \ do { \ @@ -9783,6 +10179,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M) >> \ HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) \ + HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) #define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_SET(_var, _val) \ do { \ @@ -9794,6 +10193,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_ALLOCATED_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_ALLOCATED_M) >> \ HTT_ML_PEER_DETAILS_ALLOCATED_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_ALLOCATED_GET(_var) \ + HTT_ML_PEER_DETAILS_ALLOCATED_GET(_var) #define HTT_ML_PEER_DETAILS_ALLOCATED_SET(_var, _val) \ do { \ @@ -9805,6 +10207,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_M) >> \ HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_EMLSR_SUPPORT_GET(_var) \ + HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_GET(_var) #define HTT_ML_PEER_DETAILS_EMLSR_SUPPORT_SET(_var, _val) \ do { \ @@ -9817,6 +10222,9 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M) >> \ HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S) +/* provide properly-named macro */ +#define HTT_STATS_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) \ + HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_SET(_var, _val) \ do { \ @@ -9881,11 +10289,13 @@ typedef htt_stats_ml_peer_details_tlv htt_ml_peer_details_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct _htt_ml_peer_stats { htt_stats_ml_peer_details_tlv ml_peer_details; htt_stats_ml_peer_ext_details_tlv ml_peer_ext_details; htt_stats_ml_link_info_details_tlv ml_link_info[1]; } htt_ml_peer_stats_t; +#endif /* ATH_TARGET */ /* * ODD Mandatory Stats are grouped together from all the existing different @@ -10122,6 +10532,8 @@ typedef struct { typedef htt_stats_pdev_sched_algo_ofdma_stats_tlv htt_pdev_sched_algo_ofdma_stats_tlv; +#define HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_GET(word) ((word >> 0) & 0xff) + typedef struct { htt_tlv_hdr_t tlv_hdr; /** mac_id__word: @@ -10182,7 +10594,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv; #define HTT_STATS_TDMA_MAC_ID_GET(_var) \ (((_var) & HTT_STATS_TDMA_MAC_ID_M) >> \ HTT_STATS_TDMA_MAC_ID_S) - +/* provide properly-named macro */ +#define HTT_STATS_PDEV_TDMA_MAC_ID_GET(_var) \ + HTT_STATS_TDMA_MAC_ID_GET(_var) /*======= Bandwidth Manager stats ====================*/ @@ -10315,9 +10729,11 @@ typedef htt_stats_pdev_bw_mgr_stats_tlv htt_pdev_bw_mgr_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct { htt_stats_pdev_bw_mgr_stats_tlv bw_mgr_tlv; } htt_pdev_bw_mgr_stats_t; +#endif /* ATH_TARGET */ /*============= start MLO UMAC SSR stats ============= { */ @@ -10454,6 +10870,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH, _val); \ @@ -10466,6 +10885,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_PMACS_HWMLOS_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS, _val); \ @@ -10478,6 +10900,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_GLOBAL_WSI_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI, _val); \ @@ -10490,6 +10915,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_PMACS_DMAC_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC, _val); \ @@ -10502,6 +10930,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_TCL_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL, _val); \ @@ -10514,6 +10945,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_TQM_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM, _val); \ @@ -10526,6 +10960,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_WBM_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM, _val); \ @@ -10538,6 +10975,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_REO_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO, _val); \ @@ -10550,6 +10990,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M) >> \ HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_PRE_RESET_HOST_GET(word) \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word) #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST, _val); \ @@ -10562,6 +11005,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M) >> \ HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_PREREQUISITES_GET(word) \ + HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word) #define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES, _val); \ @@ -10574,6 +11020,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M) >> \ HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_PRE_RING_RESET_GET(word) \ + HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word) #define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET, _val); \ @@ -10586,6 +11035,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M) >> \ HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_APPLY_SOFT_RESET_GET(word) \ + HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word) #define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET, _val); \ @@ -10598,6 +11050,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M) >> \ HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_POST_RING_RESET_GET(word) \ + HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word) #define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET, _val); \ @@ -10610,6 +11065,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M) >> \ HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_RESET_FW_TQM_CMDQS_GET(word) \ + HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word) #define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS, _val); \ @@ -10622,6 +11080,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_HOST_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST, _val); \ @@ -10634,6 +11095,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_UMAC_INTERRUPTS_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS, _val); \ @@ -10646,6 +11110,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_WBM_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM, _val); \ @@ -10658,6 +11125,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_REO_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_REO, _val); \ @@ -10670,6 +11140,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_TQM_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM, _val); \ @@ -10682,6 +11155,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_PMACS_DMAC_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC, _val); \ @@ -10694,6 +11170,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_TQM_SYNC_CMD_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD, _val); \ @@ -10706,6 +11185,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_GLOBAL_WSI_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI, _val); \ @@ -10718,6 +11200,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_PMACS_HWMLOS_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS, _val); \ @@ -10730,6 +11215,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH, _val); \ @@ -10742,6 +11230,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_TCL_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL, _val); \ @@ -10754,6 +11245,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_HOST_ENQ_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ, _val); \ @@ -10766,6 +11260,9 @@ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word0) \ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M) >> \ HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S) +/* provide properly-named macro */ +#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word) \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word) #define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_SET(word0, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED, _val); \ @@ -10805,6 +11302,7 @@ typedef struct { typedef htt_stats_mlo_umac_ssr_handshake_tlv htt_mlo_umac_htt_handshake_stats_tlv; +#ifdef ATH_TARGET typedef struct { /* * Note that the host cannot use this struct directly, but instead needs @@ -10814,7 +11312,9 @@ typedef struct { htt_stats_mlo_umac_ssr_dbg_tlv dbg_point[HTT_MLO_UMAC_SSR_DBG_POINT_MAX]; htt_stats_mlo_umac_ssr_handshake_tlv htt_handshakes[HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT]; } htt_mlo_umac_ssr_kpi_delta_stats_t; +#endif /* ATH_TARGET */ +#ifdef ATH_TARGET typedef struct { /* * Since each item within htt_mlo_umac_ssr_kpi_delta_stats_t has its own @@ -10829,6 +11329,7 @@ typedef struct { */ htt_mlo_umac_ssr_kpi_delta_stats_t kpi_delta; } htt_mlo_umac_ssr_kpi_delta_stats_tlv; +#endif /* ATH_TARGET */ typedef struct { A_UINT32 last_e2e_delta_ms; @@ -10874,6 +11375,7 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_mlo_umac_ssr_trigger_tlv htt_mlo_umac_ssr_trigger_stats_tlv; +#ifdef ATH_TARGET typedef struct { /* * Note that the host cannot use this struct directly, but instead needs @@ -10883,7 +11385,9 @@ typedef struct { htt_mlo_umac_ssr_kpi_delta_stats_tlv kpi_delta_tlv; htt_stats_mlo_umac_ssr_kpi_tstmp_tlv kpi_tstamp_tlv; } htt_mlo_umac_ssr_kpi_stats_t; +#endif /* ATH_TARGET */ +#ifdef ATH_TARGET typedef struct { /* * Since the embedded sub-struct within htt_mlo_umac_ssr_kpi_stats_tlv @@ -10897,7 +11401,9 @@ typedef struct { */ htt_mlo_umac_ssr_kpi_stats_t kpi; } htt_mlo_umac_ssr_kpi_stats_tlv; +#endif /* ATH_TARGET */ +#ifdef ATH_TARGET typedef struct { /* * Note that the host cannot use this struct directly, but instead needs @@ -10909,6 +11415,7 @@ typedef struct { htt_stats_mlo_umac_ssr_mlo_tlv mlo_tlv; htt_stats_mlo_umac_ssr_cmn_tlv cmn_tlv; } htt_mlo_umac_ssr_stats_tlv; +#endif /* ATH_TARGET */ /*============= end MLO UMAC SSR stats ============= } */ @@ -11057,9 +11564,11 @@ typedef htt_stats_mlo_sched_stats_tlv htt_mlo_sched_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct _htt_mlo_sched_stats { htt_stats_mlo_sched_stats_tlv preferred_link_stats; } htt_mlo_sched_stats_t; +#endif /* ATH_TARGET */ #define HTT_STATS_HWMLO_MAX_LINKS 6 #define HTT_STATS_MLO_MAX_IPC_RINGS 7 @@ -11079,9 +11588,11 @@ typedef htt_stats_pdev_mlo_ipc_stats_tlv htt_pdev_mlo_ipc_stats_tlv; * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ +#ifdef ATH_TARGET typedef struct _htt_mlo_ipc_stats { htt_stats_pdev_mlo_ipc_stats_tlv mlo_ipc_stats; } htt_pdev_mlo_ipc_stats_t; +#endif /* ATH_TARGET */ /*===================== end MLO stats ======================*/ From 5eae6b382ab09a18232adc5cc8196ff18987bff3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 25 Jan 2024 18:01:33 -0800 Subject: [PATCH 58/74] fw-api: CL 25869885 - update fw common interface files WMI: add MLO_BRIDGE_LINK flag, DYNAMIC_WSI_REMAP svc flag + MLO teardown reason Change-Id: I6a9a00a6e2194b19f2b3c4f7524ac1a45a738de0 CRs-Fixed: 2262693 --- fw/wmi_services.h | 3 ++- fw/wmi_unified.h | 3 +++ fw/wmi_version.h | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index a5d07510af2b..ab5f07a6e88b 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -653,6 +653,7 @@ typedef enum { WMI_SERVICE_WIFI_RADAR_SUPPORT = 400, /* FW supports wifi radar */ WMI_SERVICE_P2P_DEVICE_UPDATE_MAC_ADDR_SUPPORT = 401, /* indicate FW support dynamic update mac address for P2P device */ WMI_SERVICE_DCS_OBSS_INT_SUPPORT = 402, /* Indicates FW supports OBSS Interference detection */ + WMI_SERVICE_DYNAMIC_WSI_REMAP_SUPPORT = 403, /* WSI bypass remap is supported by Firmware */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index a13596731a47..12fc6d3cbaff 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -16310,6 +16310,8 @@ typedef struct { #define WMI_MLO_FLAGS_SET_NSTR_BITMAP_SIZE(mlo_flags, value) WMI_SET_BITS(mlo_flags, 12, 1, value) #define WMI_MLO_FLAGS_GET_MLO_LINK_SWITCH(mlo_flags) WMI_GET_BITS(mlo_flags, 13, 1) #define WMI_MLO_FLAGS_SET_MLO_LINK_SWITCH(mlo_flags, value) WMI_SET_BITS(mlo_flags, 13, 1, value) +#define WMI_MLO_FLAGS_GET_MLO_BRIDGE_LINK(mlo_flags) WMI_GET_BITS(mlo_flags, 14, 1) +#define WMI_MLO_FLAGS_SET_MLO_BRIDGE_LINK(mlo_flags, value) WMI_SET_BITS(mlo_flags, 14, 1, value) /* this structure used for pass mlo flags*/ typedef struct { @@ -45410,6 +45412,7 @@ typedef enum wmi_mlo_tear_down_reason_code_type { WMI_MLO_TEARDOWN_HOST_INITIATED_REASON = WMI_MLO_TEARDOWN_REASON_HOST_INITIATED, WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN, + WMI_MLO_TEARDOWN_REASON_DYNAMIC_WSI_REMAP, } WMI_MLO_TEARDOWN_REASON_TYPE; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 3a03ed8bd254..d65655777d8e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1446 +#define __WMI_REVISION_ 1447 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work From 8e71e53483bdc530d5fbcac3b73bdc8cf2dd89f2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 25 Jan 2024 18:02:38 -0800 Subject: [PATCH 59/74] fw-api: CL 25873460 - update fw common interface files add WMI_SERVICE_QMS_DLKM_SUPPORT def Change-Id: I1c6cd9017840e7cde58ff0627311429e2aba30f4 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index ab5f07a6e88b..a4de44723525 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -654,6 +654,7 @@ typedef enum { WMI_SERVICE_P2P_DEVICE_UPDATE_MAC_ADDR_SUPPORT = 401, /* indicate FW support dynamic update mac address for P2P device */ WMI_SERVICE_DCS_OBSS_INT_SUPPORT = 402, /* Indicates FW supports OBSS Interference detection */ WMI_SERVICE_DYNAMIC_WSI_REMAP_SUPPORT = 403, /* WSI bypass remap is supported by Firmware */ + WMI_SERVICE_QMS_DLKM_SUPPORT = 404, /* FW code has qms_dlkm support enabled */ WMI_MAX_EXT2_SERVICE From 78d5c31a258cfa0e88590eb9bbd2acae4faa78ac Mon Sep 17 00:00:00 2001 From: Shivi Mangal Date: Tue, 16 Jan 2024 13:50:21 +0530 Subject: [PATCH 60/74] msm: camera: sensor: Proper handling of race condition in util api Power count is coming from user space which can be modified due to access to shared memory. This change scopes the data locally so as to avoid vulnerability of count being modified by external means while executing due to being in shared memory. CRs-Fixed: 3691744. Change-Id: I57d13435453195f8aab0c9aad4414d290274ff81 Signed-off-by: Shivi Mangal --- .../cam_sensor_utils/cam_sensor_util.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index d2b4e65687c3..c4afe6fc3013 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1155,22 +1155,29 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, int32_t i = 0, pwr_up = 0, pwr_down = 0; struct cam_sensor_power_setting *pwr_settings; void *ptr = cmd_buf, *scr; - struct cam_cmd_power *pwr_cmd = (struct cam_cmd_power *)cmd_buf; struct common_header *cmm_hdr = (struct common_header *)cmd_buf; + struct cam_cmd_power *pwr_cmd = + kzalloc(sizeof(struct cam_cmd_power), GFP_KERNEL); + if (!pwr_cmd) + return -ENOMEM; + memcpy(pwr_cmd, cmd_buf, sizeof(struct cam_cmd_power)); if (!pwr_cmd || !cmd_length || cmd_buf_len < (size_t)cmd_length || cam_sensor_validate(cmd_buf, cmd_buf_len)) { CAM_ERR(CAM_SENSOR, "Invalid Args: pwr_cmd %pK, cmd_length: %d", pwr_cmd, cmd_length); - return -EINVAL; + rc = -EINVAL; + goto free_power_command; } power_info->power_setting_size = 0; power_info->power_setting = kzalloc(sizeof(struct cam_sensor_power_setting) * MAX_POWER_CONFIG, GFP_KERNEL); - if (!power_info->power_setting) - return -ENOMEM; + if (!power_info->power_setting) { + rc = -ENOMEM; + goto free_power_command; + } power_info->power_down_setting_size = 0; power_info->power_down_setting = @@ -1180,7 +1187,8 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, kfree(power_info->power_setting); power_info->power_setting = NULL; power_info->power_setting_size = 0; - return -ENOMEM; + rc = -ENOMEM; + goto free_power_command; } while (tot_size < cmd_length) { @@ -1364,7 +1372,7 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, } } - return rc; + goto free_power_command; free_power_settings: kfree(power_info->power_down_setting); kfree(power_info->power_setting); @@ -1372,6 +1380,9 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, power_info->power_setting = NULL; power_info->power_down_setting_size = 0; power_info->power_setting_size = 0; +free_power_command: + kfree(pwr_cmd); + pwr_cmd = NULL; return rc; } From 69df853d40b5be8239a19d11e29a0b77483135bd Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Fri, 19 Jan 2024 08:38:17 -0800 Subject: [PATCH 61/74] msm: kgsl: Keep the timeline fence valid for logging The timeline fence needs to remain valid for logging purposes. Take an extra refcount on the timeline dma_fence to make sure it doesn't go away till we're done with it. Change-Id: I6670ef7add099a72684c1fe20ed009dff85d1f27 Signed-off-by: Lynus Vaz --- drivers/gpu/msm/kgsl_drawobj.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/msm/kgsl_drawobj.c b/drivers/gpu/msm/kgsl_drawobj.c index 63fefc5b98f3..cce40192a3e5 100644 --- a/drivers/gpu/msm/kgsl_drawobj.c +++ b/drivers/gpu/msm/kgsl_drawobj.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ /* @@ -508,6 +508,8 @@ static int drawobj_add_sync_timeline(struct kgsl_device *device, /* Set pending flag before adding callback to avoid race */ set_bit(event->id, &syncobj->pending); + /* Get a dma_fence refcount to hand over to the callback */ + dma_fence_get(event->fence); ret = dma_fence_add_callback(event->fence, &event->cb, drawobj_sync_timeline_fence_callback); @@ -520,10 +522,15 @@ static int drawobj_add_sync_timeline(struct kgsl_device *device, ret = 0; } + /* Put the refcount from fence creation */ + dma_fence_put(event->fence); kgsl_drawobj_put(drawobj); + return ret; } - return ret; + /* Put the refcount from fence creation */ + dma_fence_put(event->fence); + return 0; } static int drawobj_add_sync_fence(struct kgsl_device *device, From ab27a52cf140affecd3a2f7d76ea08d7b76952df Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Wed, 20 Dec 2023 13:52:55 -0800 Subject: [PATCH 62/74] msm: kgsl: Do not release dma and anon buffers if unmap fails If iommu unmap fails and leaves dma or anon buffers still mapped in the iommu, do not free them. Change-Id: Ice0e1a59c1ac0ee7a9d62d8899966b84fa63d5ca Signed-off-by: Lynus Vaz --- drivers/gpu/msm/kgsl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 124244538060..6276dc3568f6 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -300,6 +300,9 @@ static void kgsl_destroy_ion(struct kgsl_memdesc *memdesc) struct kgsl_mem_entry, memdesc); struct kgsl_dma_buf_meta *meta = entry->priv_data; + if (memdesc->priv & KGSL_MEMDESC_MAPPED) + return; + if (meta != NULL) { remove_dmabuf_list(meta); dma_buf_unmap_attachment(meta->attach, meta->table, @@ -328,6 +331,9 @@ static void kgsl_destroy_anon(struct kgsl_memdesc *memdesc) struct scatterlist *sg; struct page *page; + if (memdesc->priv & KGSL_MEMDESC_MAPPED) + return; + for_each_sg(memdesc->sgt->sgl, sg, memdesc->sgt->nents, i) { page = sg_page(sg); for (j = 0; j < (sg->length >> PAGE_SHIFT); j++) { From 3b3f786414993e96a37f50a3af114507d5a07b2c Mon Sep 17 00:00:00 2001 From: Shivi Mangal Date: Tue, 16 Jan 2024 13:50:21 +0530 Subject: [PATCH 63/74] msm: camera: sensor: Proper handling of race condition in util api Power count is coming from user space which can be modified due to access to shared memory. This change scopes the data locally so as to avoid vulnerability of count being modified by external means while executing due to being in shared memory. CRs-Fixed: 3691744. Change-Id: I57d13435453195f8aab0c9aad4414d290274ff81 Signed-off-by: Shivi Mangal --- .../cam_sensor_utils/cam_sensor_util.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index f50d6584684c..2f2fe35f81c2 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1158,22 +1158,29 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, int32_t i = 0, pwr_up = 0, pwr_down = 0; struct cam_sensor_power_setting *pwr_settings; void *ptr = cmd_buf, *scr; - struct cam_cmd_power *pwr_cmd = (struct cam_cmd_power *)cmd_buf; struct common_header *cmm_hdr = (struct common_header *)cmd_buf; + struct cam_cmd_power *pwr_cmd = + kzalloc(sizeof(struct cam_cmd_power), GFP_KERNEL); + if (!pwr_cmd) + return -ENOMEM; + memcpy(pwr_cmd, cmd_buf, sizeof(struct cam_cmd_power)); if (!pwr_cmd || !cmd_length || cmd_buf_len < (size_t)cmd_length || cam_sensor_validate(cmd_buf, cmd_buf_len)) { CAM_ERR(CAM_SENSOR, "Invalid Args: pwr_cmd %pK, cmd_length: %d", pwr_cmd, cmd_length); - return -EINVAL; + rc = -EINVAL; + goto free_power_command; } power_info->power_setting_size = 0; power_info->power_setting = kzalloc(sizeof(struct cam_sensor_power_setting) * MAX_POWER_CONFIG, GFP_KERNEL); - if (!power_info->power_setting) - return -ENOMEM; + if (!power_info->power_setting) { + rc = -ENOMEM; + goto free_power_command; + } power_info->power_down_setting_size = 0; power_info->power_down_setting = @@ -1183,7 +1190,8 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, kfree(power_info->power_setting); power_info->power_setting = NULL; power_info->power_setting_size = 0; - return -ENOMEM; + rc = -ENOMEM; + goto free_power_command; } while (tot_size < cmd_length) { @@ -1367,7 +1375,7 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, } } - return rc; + goto free_power_command; free_power_settings: kfree(power_info->power_down_setting); kfree(power_info->power_setting); @@ -1375,6 +1383,9 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, power_info->power_setting = NULL; power_info->power_down_setting_size = 0; power_info->power_setting_size = 0; +free_power_command: + kfree(pwr_cmd); + pwr_cmd = NULL; return rc; } From aad4cd6b0550af823bfadc01c027cae0d2dcfde1 Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Fri, 22 Sep 2023 13:13:58 +0530 Subject: [PATCH 64/74] soc: qcom: smem: Add boundary checks for partitions Add condition check to make sure that the end address of private entry does not go out of partition. Change-Id: I88b3c69d86d90905b214c13a8c632b134b487a49 Signed-off-by: Sarannya S Signed-off-by: Pranav Mahesh Phansalkar (cherry picked from commit e9c3b19682eb270d9fd85a2b3e2d215c74f1463c) --- drivers/soc/qcom/smem.c | 111 +++++++++++++++++++++++++++------------- 1 file changed, 76 insertions(+), 35 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index ee005e1a8552..353c1320e3e6 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2015, Sony Mobile Communications AB. * Copyright (c) 2012-2013, 2018-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -85,6 +86,17 @@ /* Max number of processors/hosts in a system */ #define SMEM_HOST_COUNT 11 +/* Entry range check + * ptr >= start : Checks if ptr is greater than the start of access region + * ptr + size >= ptr: Check for integer overflow (On 32bit system where ptr + * and size are 32bits, ptr + size can wrap around to be a small integer) + * ptr + size <= end: Checks if ptr+size is less than the end of access region + */ +#define IN_PARTITION_RANGE(ptr, size, start, end) \ + (((void *)(ptr) >= (void *)(start)) && \ + (((void *)(ptr) + (size)) >= (void *)(ptr)) && \ + (((void *)(ptr) + (size)) <= (void *)(end))) + /** * struct smem_proc_comm - proc_comm communication struct (legacy) * @command: current command to be executed @@ -359,6 +371,7 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem, size_t size) { struct smem_private_entry *hdr, *end; + struct smem_private_entry *next_hdr; struct smem_partition_header *phdr; size_t alloc_size; void *cached; @@ -371,18 +384,25 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem, end = phdr_to_last_uncached_entry(phdr); cached = phdr_to_last_cached_entry(phdr); - if (WARN_ON((void *)end > p_end || (void *)cached > p_end)) + if (WARN_ON(!IN_PARTITION_RANGE(end, 0, phdr, cached) || + cached > p_end)) return -EINVAL; - while (hdr < end) { + while ((hdr < end) && ((hdr + 1) < end)) { if (hdr->canary != SMEM_PRIVATE_CANARY) goto bad_canary; if (le16_to_cpu(hdr->item) == item) return -EEXIST; - hdr = uncached_entry_next(hdr); + next_hdr = uncached_entry_next(hdr); + + if (WARN_ON(next_hdr <= hdr)) + return -EINVAL; + + hdr = next_hdr; } - if (WARN_ON((void *)hdr > p_end)) + + if (WARN_ON((void *)hdr > (void *)end)) return -EINVAL; /* Check that we don't grow into the cached region */ @@ -540,84 +560,105 @@ static void *qcom_smem_get_private(struct qcom_smem *smem, unsigned item, size_t *size) { - struct smem_private_entry *e, *end; + struct smem_private_entry *e, *uncached_end, *cached_end; + struct smem_private_entry *next_e; struct smem_partition_header *phdr; void *item_ptr, *p_end; + size_t entry_size = 0; + u32 partition_size; size_t cacheline; u32 padding_data; u32 e_size; phdr = p_desc->virt_base; + partition_size = le32_to_cpu(p_desc->size); p_end = (void *)phdr + p_desc->size; cacheline = p_desc->cacheline; e = phdr_to_first_uncached_entry(phdr); - end = phdr_to_last_uncached_entry(phdr); + uncached_end = phdr_to_last_uncached_entry(phdr); + cached_end = phdr_to_last_cached_entry(phdr); - if (WARN_ON((void *)end > p_end)) + if (WARN_ON(!IN_PARTITION_RANGE(uncached_end, 0, phdr, cached_end) + || (void *)cached_end > p_end)) return ERR_PTR(-EINVAL); - while (e < end) { + while ((e < uncached_end) && ((e + 1) < uncached_end)) { if (e->canary != SMEM_PRIVATE_CANARY) goto invalid_canary; if (le16_to_cpu(e->item) == item) { - if (size != NULL) { - e_size = le32_to_cpu(e->size); - padding_data = le16_to_cpu(e->padding_data); + e_size = le32_to_cpu(e->size); + padding_data = le16_to_cpu(e->padding_data); - if (e_size < p_desc->size - && padding_data < e_size) - *size = e_size - padding_data; - else - return ERR_PTR(-EINVAL); - } + if (e_size < partition_size && padding_data < e_size) + entry_size = e_size - padding_data; + else + return ERR_PTR(-EINVAL); item_ptr = uncached_entry_to_item(e); - if (WARN_ON(item_ptr > p_end)) + + if (WARN_ON(!IN_PARTITION_RANGE(item_ptr, entry_size, e, + uncached_end))) return ERR_PTR(-EINVAL); + if (size != NULL) + *size = entry_size; + return item_ptr; } - e = uncached_entry_next(e); + next_e = uncached_entry_next(e); + if (WARN_ON(next_e <= e)) + return ERR_PTR(-EINVAL); + + e = next_e; } - if (WARN_ON((void *)e > p_end)) + if (WARN_ON((void *)e > (void *)uncached_end)) return ERR_PTR(-EINVAL); /* Item was not found in the uncached list, search the cached list */ - e = phdr_to_first_cached_entry(phdr, cacheline); - end = phdr_to_last_cached_entry(phdr); + if (cached_end == p_end) + return ERR_PTR(-ENOENT); - if (WARN_ON((void *)e < (void *)phdr || (void *)end > p_end)) + e = phdr_to_first_cached_entry(phdr, cacheline); + + if (WARN_ON(!IN_PARTITION_RANGE(cached_end, 0, uncached_end, p_end) || + !IN_PARTITION_RANGE(e, sizeof(*e), cached_end, p_end))) return ERR_PTR(-EINVAL); - while (e > end) { + while (e > cached_end) { if (e->canary != SMEM_PRIVATE_CANARY) goto invalid_canary; if (le16_to_cpu(e->item) == item) { - if (size != NULL) { - e_size = le32_to_cpu(e->size); - padding_data = le16_to_cpu(e->padding_data); + e_size = le32_to_cpu(e->size); + padding_data = le16_to_cpu(e->padding_data); - if (e_size < p_desc->size - && padding_data < e_size) - *size = e_size - padding_data; - else - return ERR_PTR(-EINVAL); - } + if (e_size < partition_size && padding_data < e_size) + entry_size = e_size - padding_data; + else + return ERR_PTR(-EINVAL); item_ptr = cached_entry_to_item(e); - if (WARN_ON(item_ptr < (void *)phdr)) + if (WARN_ON(!IN_PARTITION_RANGE(item_ptr, entry_size, + cached_end, e))) return ERR_PTR(-EINVAL); + if (size != NULL) + *size = entry_size; + return item_ptr; } - e = cached_entry_next(e, cacheline); + next_e = cached_entry_next(e, cacheline); + if (WARN_ON(next_e >= e)) + return ERR_PTR(-EINVAL); + + e = next_e; } + if (WARN_ON((void *)e < (void *)phdr)) return ERR_PTR(-EINVAL); From 50240b4951a7d9bd54db41215d43def5413be48d Mon Sep 17 00:00:00 2001 From: Krupali Dhanvijay Date: Mon, 5 Feb 2024 16:53:50 +0530 Subject: [PATCH 65/74] qcacmn: Fix out of bound read issue in ESP ie parse While parsing ESP IE from beacon/probe response frame, the condition in loop to copy ESP_INFO from the ESP IE is incorrect which will iterate for 5 times rather than 4 times, this may cause OOB access. data < ((uint8_t *)esp_ie + esp_ie->esp_len + 3) Here adding 3 for esp_ie->esp_len, actually esp_len itself is 1 byte extra (esp_ len = ESP_ID_EXTN + ESP_INFO * 4), but by adding 3 again will loop for one more iteration this will cause OOB access. Remove 3 in loop condition to avoid one more extra iteration and ignore ESP_ID_EXTN element for total elements, in function util_scan_update_esp_data. Change-Id: Ia9226e483672369af36c6914e3ac914fe9de45e5 CRs-Fixed: 3710081 --- umac/scan/dispatcher/src/wlan_scan_utils_api.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/umac/scan/dispatcher/src/wlan_scan_utils_api.c b/umac/scan/dispatcher/src/wlan_scan_utils_api.c index b8b2f87c9ea2..86c1c1b81a02 100644 --- a/umac/scan/dispatcher/src/wlan_scan_utils_api.c +++ b/umac/scan/dispatcher/src/wlan_scan_utils_api.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1185,7 +1185,8 @@ static void util_scan_update_esp_data(struct wlan_esp_ie *esp_information, esp_ie = (struct wlan_esp_ie *) util_scan_entry_esp_info(scan_entry); - total_elements = esp_ie->esp_len; + // Ignore ESP_ID_EXTN element + total_elements = esp_ie->esp_len - 1; data = (uint8_t *)esp_ie + 3; do_div(total_elements, ESP_INFORMATION_LIST_LENGTH); @@ -1195,7 +1196,7 @@ static void util_scan_update_esp_data(struct wlan_esp_ie *esp_information, } for (i = 0; i < total_elements && - data < ((uint8_t *)esp_ie + esp_ie->esp_len + 3); i++) { + data < ((uint8_t *)esp_ie + esp_ie->esp_len); i++) { esp_info = (struct wlan_esp_info *)data; if (esp_info->access_category == ESP_AC_BK) { qdf_mem_copy(&esp_information->esp_info_AC_BK, From 66391f6445d3e6b40750675264f4f246b411fb49 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Fri, 8 Jul 2022 18:10:01 +0800 Subject: [PATCH 66/74] erofs: avoid consecutive detection for Highmem memory [ Upstream commit 448b5a1548d87c246c3d0c3df8480d3c6eb6c11a ] Currently, vmap()s are avoided if physical addresses are consecutive for decompressed buffers. I observed that is very common for 4KiB pclusters since the numbers of decompressed pages are almost 2 or 3. However, such detection doesn't work for Highmem pages on 32-bit machines, let's fix it now. Reported-by: Liu Jinbao Fixes: 7fc45dbc938a ("staging: erofs: introduce generic decompression backend") Link: https://lore.kernel.org/r/20220708101001.21242-1-hsiangkao@linux.alibaba.com Signed-off-by: Gao Xiang Signed-off-by: Sasha Levin Change-Id: I5a05bb5e4feae764e820565e4a7f2cbeed8a7a3e --- fs/erofs/decompressor.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index ad3f31380e6b..8193c14bb111 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -93,14 +93,18 @@ static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, if (page) { __clear_bit(j, bounced); - if (kaddr) { - if (kaddr + PAGE_SIZE == page_address(page)) + if (!PageHighMem(page)) { + if (!i) { + kaddr = page_address(page); + continue; + } + if (kaddr && + kaddr + PAGE_SIZE == page_address(page)) { kaddr += PAGE_SIZE; - else - kaddr = NULL; - } else if (!i) { - kaddr = page_address(page); + continue; + } } + kaddr = NULL; continue; } kaddr = NULL; From 978a1729a727c58352655b05e44e44c3e155f1bb Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Tue, 11 Apr 2023 01:37:14 +0800 Subject: [PATCH 67/74] erofs: stop parsing non-compact HEAD index if clusterofs is invalid [ Upstream commit cc4efd3dd2ac9f89143e5d881609747ecff04164 ] Syzbot generated a crafted image [1] with a non-compact HEAD index of clusterofs 33024 while valid numbers should be 0 ~ lclustersize-1, which causes the following unexpected behavior as below: BUG: unable to handle page fault for address: fffff52101a3fff9 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 23ffed067 P4D 23ffed067 PUD 0 Oops: 0000 [#1] PREEMPT SMP KASAN CPU: 1 PID: 4398 Comm: kworker/u5:1 Not tainted 6.3.0-rc6-syzkaller-g09a9639e56c0 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 03/30/2023 Workqueue: erofs_worker z_erofs_decompressqueue_work RIP: 0010:z_erofs_decompress_queue+0xb7e/0x2b40 ... Call Trace: z_erofs_decompressqueue_work+0x99/0xe0 process_one_work+0x8f6/0x1170 worker_thread+0xa63/0x1210 kthread+0x270/0x300 ret_from_fork+0x1f/0x30 Note that normal images or images using compact indexes are not impacted. Let's fix this now. [1] https://lore.kernel.org/r/000000000000ec75b005ee97fbaa@google.com Reported-and-tested-by: syzbot+aafb3f37cfeb6534c4ac@syzkaller.appspotmail.com Fixes: 02827e1796b3 ("staging: erofs: add erofs_map_blocks_iter") Fixes: 152a333a5895 ("staging: erofs: add compacted compression indexes support") Signed-off-by: Gao Xiang Reviewed-by: Chao Yu Link: https://lore.kernel.org/r/20230410173714.104604-1-hsiangkao@linux.alibaba.com Signed-off-by: Sasha Levin Change-Id: I1725f5d72ccab455da9e1fc30aa969383ff97e7e --- fs/erofs/zmap.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c index a7da7ed4bda7..046a2515e309 100644 --- a/fs/erofs/zmap.c +++ b/fs/erofs/zmap.c @@ -191,6 +191,10 @@ static int legacy_load_cluster_from_disk(struct z_erofs_maprecorder *m, case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN: case Z_EROFS_VLE_CLUSTER_TYPE_HEAD: m->clusterofs = le16_to_cpu(di->di_clusterofs); + if (m->clusterofs >= 1 << vi->z_logical_clusterbits) { + DBG_BUGON(1); + return -EFSCORRUPTED; + } m->pblk = le32_to_cpu(di->di_u.blkaddr); break; default: From b597945e2b30f406dfd06bcaee965b19017489f9 Mon Sep 17 00:00:00 2001 From: Jingbo Xu Date: Fri, 14 Apr 2023 14:18:10 +0800 Subject: [PATCH 68/74] erofs: fix potential overflow calculating xattr_isize [ Upstream commit 1b3567a1969b26f709d82a874498c0754ea841c3 ] Given on-disk i_xattr_icount is 16 bits and xattr_isize is calculated from i_xattr_icount multiplying 4, xattr_isize has a theoretical maximum of 256K (64K * 4). Thus declare xattr_isize as unsigned int to avoid the potential overflow. Fixes: bfb8674dc044 ("staging: erofs: add erofs in-memory stuffs") Signed-off-by: Jingbo Xu Reviewed-by: Gao Xiang Reviewed-by: Chao Yu Link: https://lore.kernel.org/r/20230414061810.6479-1-jefflexu@linux.alibaba.com Signed-off-by: Gao Xiang Signed-off-by: Sasha Levin Change-Id: I7c981e8ad55a019534a2e3f8abeb3897df5706e5 --- fs/erofs/internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index c8f904bbe985..50d359101642 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -246,7 +246,7 @@ struct erofs_inode { unsigned char datalayout; unsigned char inode_isize; - unsigned short xattr_isize; + unsigned int xattr_isize; unsigned int xattr_shared_count; unsigned int *xattr_shared_xattrs; From 786f883cc920f48638cc59c940ba0e3150c45374 Mon Sep 17 00:00:00 2001 From: Chunhai Guo Date: Mon, 10 Jul 2023 17:34:10 +0800 Subject: [PATCH 69/74] erofs: avoid infinite loop in z_erofs_do_read_page() when reading beyond EOF [ Upstream commit 8191213a5835b0317c5e4d0d337ae1ae00c75253 ] z_erofs_do_read_page() may loop infinitely due to the inappropriate truncation in the below statement. Since the offset is 64 bits and min_t() truncates the result to 32 bits. The solution is to replace unsigned int with a 64-bit type, such as erofs_off_t. cur = end - min_t(unsigned int, offset + end - map->m_la, end); - For example: - offset = 0x400160000 - end = 0x370 - map->m_la = 0x160370 - offset + end - map->m_la = 0x400000000 - offset + end - map->m_la = 0x00000000 (truncated as unsigned int) - Expected result: - cur = 0 - Actual result: - cur = 0x370 Signed-off-by: Chunhai Guo Fixes: 3883a79abd02 ("staging: erofs: introduce VLE decompression support") Reviewed-by: Gao Xiang Reviewed-by: Chao Yu Link: https://lore.kernel.org/r/20230710093410.44071-1-guochunhai@vivo.com Signed-off-by: Gao Xiang Signed-off-by: Sasha Levin Change-Id: Ibbabe41c5a338a2def37b9d29cd8c229a44450f9 --- fs/erofs/zdata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 2d2cbfac500b..d689cf2211ee 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -714,7 +714,7 @@ static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, tight &= (clt->mode >= COLLECT_PRIMARY_HOOKED && clt->mode != COLLECT_PRIMARY_FOLLOWED_NOINPLACE); - cur = end - min_t(unsigned int, offset + end - map->m_la, end); + cur = end - min_t(erofs_off_t, offset + end - map->m_la, end); if (!(map->m_flags & EROFS_MAP_MAPPED)) { zero_user_segment(page, cur, end); goto next_part; From 91041fcd82255c2f2d0b6dc6f8aa7a552dc79c22 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Thu, 1 Jun 2023 19:23:41 +0800 Subject: [PATCH 70/74] erofs: fix compact 4B support for 16k block size commit 001b8ccd0650727e54ec16ef72bf1b8eeab7168e upstream. In compact 4B, two adjacent lclusters are packed together as a unit to form on-disk indexes for effective random access, as below: (amortized = 4, vcnt = 2) _____________________________________________ |___@_____ encoded bits __________|_ blkaddr _| 0 . amortized * vcnt = 8 . . . . amortized * vcnt - 4 = 4 . . .____________________________. |_type (2 bits)_|_clusterofs_| Therefore, encoded bits for each pack are 32 bits (4 bytes). IOWs, since each lcluster can get 16 bits for its type and clusterofs, the maximum supported lclustersize for compact 4B format is 16k (14 bits). Fix this to enable compact 4B format for 16k lclusters (blocks), which is tested on an arm64 server with 16k page size. Fixes: 152a333a5895 ("staging: erofs: add compacted compression indexes support") Signed-off-by: Gao Xiang Link: https://lore.kernel.org/r/20230601112341.56960-1-hsiangkao@linux.alibaba.com Signed-off-by: Greg Kroah-Hartman Change-Id: If1c45681c60f6897bb9d83662e379951084b7a32 --- fs/erofs/zmap.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/fs/erofs/zmap.c b/fs/erofs/zmap.c index 046a2515e309..5cc6e6837a92 100644 --- a/fs/erofs/zmap.c +++ b/fs/erofs/zmap.c @@ -228,7 +228,7 @@ static int unpack_compacted_index(struct z_erofs_maprecorder *m, u8 *in, type; bool big_pcluster; - if (1 << amortizedshift == 4) + if (1 << amortizedshift == 4 && lclusterbits <= 14) vcnt = 2; else if (1 << amortizedshift == 2 && lclusterbits == 12) vcnt = 16; @@ -321,7 +321,6 @@ static int compacted_load_cluster_from_disk(struct z_erofs_maprecorder *m, { struct inode *const inode = m->inode; struct erofs_inode *const vi = EROFS_I(inode); - const unsigned int lclusterbits = vi->z_logical_clusterbits; const erofs_off_t ebase = ALIGN(iloc(EROFS_I_SB(inode), vi->nid) + vi->inode_isize + vi->xattr_isize, 8) + sizeof(struct z_erofs_map_header); @@ -331,9 +330,6 @@ static int compacted_load_cluster_from_disk(struct z_erofs_maprecorder *m, erofs_off_t pos; int err; - if (lclusterbits != 12) - return -EOPNOTSUPP; - if (lcn >= totalidx) return -EINVAL; From 0a6b1078f5ec067368b35c8983bcfad25b0ee806 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Thu, 31 Aug 2023 19:29:58 +0800 Subject: [PATCH 71/74] erofs: ensure that the post-EOF tails are all zeroed commit e4c1cf523d820730a86cae2c6d55924833b6f7ac upstream. This was accidentally fixed up in commit e4c1cf523d82 but we can't take the full change due to other dependancy issues, so here is just the actual bugfix that is needed. [Background] keltargw reported an issue [1] that with mmaped I/Os, sometimes the tail of the last page (after file ends) is not filled with zeroes. The root cause is that such tail page could be wrongly selected for inplace I/Os so the zeroed part will then be filled with compressed data instead of zeroes. A simple fix is to avoid doing inplace I/Os for such tail parts, actually that was already fixed upstream in commit e4c1cf523d82 ("erofs: tidy up z_erofs_do_read_page()") by accident. [1] https://lore.kernel.org/r/3ad8b469-25db-a297-21f9-75db2d6ad224@linux.alibaba.com Reported-by: keltargw Fixes: 3883a79abd02 ("staging: erofs: introduce VLE decompression support") Signed-off-by: Gao Xiang Signed-off-by: Greg Kroah-Hartman Change-Id: I7936777249ed01775984c200d405d101fd74d881 --- fs/erofs/zdata.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index d689cf2211ee..35a08f3a53d0 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -717,6 +717,8 @@ static int z_erofs_do_read_page(struct z_erofs_decompress_frontend *fe, cur = end - min_t(erofs_off_t, offset + end - map->m_la, end); if (!(map->m_flags & EROFS_MAP_MAPPED)) { zero_user_segment(page, cur, end); + ++spiltted; + tight = false; goto next_part; } From 950e1e4a2d76f45fb4e22d7a38441217c77cda8b Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 17 Mar 2024 02:12:25 +0100 Subject: [PATCH 72/74] Revert "erofs: support decompress big pcluster for lz4 backend" This reverts commit 3337f637087fce04bcc5ba28f66abdefe21142fa. Reason: Conflicts with next change and doesn't exist upstream Change-Id: I65fdef31d221f6536254a3dffa3f0b1e871e28ff --- fs/erofs/decompressor.c | 220 ++++++++++++++++++---------------------- fs/erofs/internal.h | 15 --- 2 files changed, 96 insertions(+), 139 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 8193c14bb111..5396cf0ca1d4 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -123,85 +123,44 @@ static int z_erofs_lz4_prepare_destpages(struct z_erofs_decompress_req *rq, return kaddr ? 1 : 0; } -static void *z_erofs_handle_inplace_io(struct z_erofs_decompress_req *rq, - void *inpage, unsigned int *inputmargin, int *maptype, - bool support_0padding) +static void *generic_copy_inplace_data(struct z_erofs_decompress_req *rq, + u8 *src, unsigned int pageofs_in) { - unsigned int nrpages_in, nrpages_out; - unsigned int ofull, oend, inputsize, total, i, j; - struct page **in; - void *src, *tmp; + /* + * if in-place decompression is ongoing, those decompressed + * pages should be copied in order to avoid being overlapped. + */ + struct page **in = rq->in; + u8 *const tmp = erofs_get_pcpubuf(1); + u8 *tmpp = tmp; + unsigned int inlen = rq->inputsize - pageofs_in; + unsigned int count = min_t(uint, inlen, PAGE_SIZE - pageofs_in); - inputsize = rq->inputsize; - nrpages_in = PAGE_ALIGN(inputsize) >> PAGE_SHIFT; - oend = rq->pageofs_out + rq->outputsize; - ofull = PAGE_ALIGN(oend); - nrpages_out = ofull >> PAGE_SHIFT; - - if (rq->inplace_io) { - if (rq->partial_decoding || !support_0padding || - ofull - oend < LZ4_DECOMPRESS_INPLACE_MARGIN(inputsize)) - goto docopy; - - for (i = 0; i < nrpages_in; ++i) { - DBG_BUGON(rq->in[i] == NULL); - for (j = 0; j < nrpages_out - nrpages_in + i; ++j) - if (rq->out[j] == rq->in[i]) - goto docopy; - } - } - - if (nrpages_in <= 1) { - *maptype = 0; - return inpage; - } - kunmap_atomic(inpage); - might_sleep(); - src = erofs_vm_map_ram(rq->in, nrpages_in); - if (!src) - return ERR_PTR(-ENOMEM); - *maptype = 1; - return src; - -docopy: - /* Or copy compressed data which can be overlapped to per-CPU buffer */ - in = rq->in; - src = erofs_get_pcpubuf(nrpages_in); - if (!src) { - DBG_BUGON(1); - kunmap_atomic(inpage); - return ERR_PTR(-EFAULT); - } - - tmp = src; - total = rq->inputsize; - while (total) { - unsigned int page_copycnt = - min_t(unsigned int, total, PAGE_SIZE - *inputmargin); - - if (!inpage) - inpage = kmap_atomic(*in); - memcpy(tmp, inpage + *inputmargin, page_copycnt); - kunmap_atomic(inpage); - inpage = NULL; - tmp += page_copycnt; - total -= page_copycnt; + while (tmpp < tmp + inlen) { + if (!src) + src = kmap_atomic(*in); + memcpy(tmpp, src + pageofs_in, count); + kunmap_atomic(src); + src = NULL; + tmpp += count; + pageofs_in = 0; + count = PAGE_SIZE; ++in; - *inputmargin = 0; } - *maptype = 2; - return src; + return tmp; } static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) { - unsigned int inputmargin; - u8 *headpage, *src; - bool support_0padding; - int ret, maptype; + unsigned int inputmargin, inlen; + u8 *src; + bool copied, support_0padding; + int ret; - DBG_BUGON(*rq->in == NULL); - headpage = kmap_atomic(*rq->in); + if (rq->inputsize > PAGE_SIZE) + return -EOPNOTSUPP; + + src = kmap_atomic(*rq->in); inputmargin = 0; support_0padding = false; @@ -209,36 +168,49 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) if (erofs_sb_has_lz4_0padding(EROFS_SB(rq->sb))) { support_0padding = true; - while (!headpage[inputmargin & ~PAGE_MASK]) + while (!src[inputmargin & ~PAGE_MASK]) if (!(++inputmargin & ~PAGE_MASK)) break; if (inputmargin >= rq->inputsize) { - kunmap_atomic(headpage); + kunmap_atomic(src); return -EIO; } } - rq->inputsize -= inputmargin; - src = z_erofs_handle_inplace_io(rq, headpage, &inputmargin, &maptype, - support_0padding); - if (IS_ERR(src)) - return PTR_ERR(src); + copied = false; + inlen = rq->inputsize - inputmargin; + if (rq->inplace_io) { + const uint oend = (rq->pageofs_out + + rq->outputsize) & ~PAGE_MASK; + const uint nr = PAGE_ALIGN(rq->pageofs_out + + rq->outputsize) >> PAGE_SHIFT; + + if (rq->partial_decoding || !support_0padding || + rq->out[nr - 1] != rq->in[0] || + rq->inputsize - oend < + LZ4_DECOMPRESS_INPLACE_MARGIN(inlen)) { + src = generic_copy_inplace_data(rq, src, inputmargin); + inputmargin = 0; + copied = true; + } + } /* legacy format could compress extra data in a pcluster. */ if (rq->partial_decoding || !support_0padding) ret = LZ4_decompress_safe_partial(src + inputmargin, out, - rq->inputsize, rq->outputsize, rq->outputsize); + inlen, rq->outputsize, + rq->outputsize); else ret = LZ4_decompress_safe(src + inputmargin, out, - rq->inputsize, rq->outputsize); + inlen, rq->outputsize); if (ret != rq->outputsize) { erofs_err(rq->sb, "failed to decompress %d in[%u, %u] out[%u]", - ret, rq->inputsize, inputmargin, rq->outputsize); + ret, inlen, inputmargin, rq->outputsize); print_hex_dump(KERN_DEBUG, "[ in]: ", DUMP_PREFIX_OFFSET, - 16, 1, src + inputmargin, rq->inputsize, true); + 16, 1, src + inputmargin, inlen, true); print_hex_dump(KERN_DEBUG, "[out]: ", DUMP_PREFIX_OFFSET, 16, 1, out, rq->outputsize, true); @@ -247,16 +219,10 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) ret = -EIO; } - if (maptype == 0) { - kunmap_atomic(src); - } else if (maptype == 1) { - vm_unmap_ram(src, PAGE_ALIGN(rq->inputsize) >> PAGE_SHIFT); - } else if (maptype == 2) { + if (copied) erofs_put_pcpubuf(src); - } else { - DBG_BUGON(1); - return -EFAULT; - } + else + kunmap_atomic(src); return ret; } @@ -306,51 +272,57 @@ static int z_erofs_decompress_generic(struct z_erofs_decompress_req *rq, const struct z_erofs_decompressor *alg = decompressors + rq->alg; unsigned int dst_maptype; void *dst; - int ret; + int ret, i; - /* two optimized fast paths only for non bigpcluster cases yet */ - if (rq->inputsize <= PAGE_SIZE) { - if (nrpages_out == 1 && !rq->inplace_io) { - DBG_BUGON(!*rq->out); - dst = kmap_atomic(*rq->out); - dst_maptype = 0; - goto dstmap_out; - } - - /* - * For the case of small output size (especially much less - * than PAGE_SIZE), memcpy the decompressed data rather than - * compressed data is preferred. - */ - if (rq->outputsize <= PAGE_SIZE * 7 / 8) { - dst = erofs_get_pcpubuf(1); - if (IS_ERR(dst)) - return PTR_ERR(dst); - - rq->inplace_io = false; - ret = alg->decompress(rq, dst); - if (!ret) - copy_from_pcpubuf(rq->out, dst, rq->pageofs_out, - rq->outputsize); - - erofs_put_pcpubuf(dst); - return ret; - } + if (nrpages_out == 1 && !rq->inplace_io) { + DBG_BUGON(!*rq->out); + dst = kmap_atomic(*rq->out); + dst_maptype = 0; + goto dstmap_out; } - /* general decoding path which can be used for all cases */ - ret = alg->prepare_destpages(rq, pagepool); - if (ret < 0) + /* + * For the case of small output size (especially much less + * than PAGE_SIZE), memcpy the decompressed data rather than + * compressed data is preferred. + */ + if (rq->outputsize <= PAGE_SIZE * 7 / 8) { + dst = erofs_get_pcpubuf(1); + if (IS_ERR(dst)) + return PTR_ERR(dst); + + rq->inplace_io = false; + ret = alg->decompress(rq, dst); + if (!ret) + copy_from_pcpubuf(rq->out, dst, rq->pageofs_out, + rq->outputsize); + + erofs_put_pcpubuf(dst); return ret; - if (ret) { + } + + ret = alg->prepare_destpages(rq, pagepool); + if (ret < 0) { + return ret; + } else if (ret) { dst = page_address(*rq->out); dst_maptype = 1; goto dstmap_out; } - dst = erofs_vm_map_ram(rq->out, nrpages_out); + i = 0; + while (1) { + dst = vm_map_ram(rq->out, nrpages_out, -1, PAGE_KERNEL); + + /* retry two more times (totally 3 times) */ + if (dst || ++i >= 3) + break; + vm_unmap_aliases(); + } + if (!dst) return -ENOMEM; + dst_maptype = 2; dstmap_out: diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h index 50d359101642..814541bf0cce 100644 --- a/fs/erofs/internal.h +++ b/fs/erofs/internal.h @@ -396,21 +396,6 @@ int erofs_namei(struct inode *dir, struct qstr *name, /* dir.c */ extern const struct file_operations erofs_dir_fops; -static inline void *erofs_vm_map_ram(struct page **pages, unsigned int count) -{ - int retried = 0; - - while (1) { - void *p = vm_map_ram(pages, count, -1, PAGE_KERNEL); - - /* retry two more times (totally 3 times) */ - if (p || ++retried >= 3) - return p; - vm_unmap_aliases(); - } - return NULL; -} - /* pcpubuf.c */ void *erofs_get_pcpubuf(unsigned int requiredpages); void erofs_put_pcpubuf(void *ptr); From 1a9efb0ce229854b8c4d4d83dedd80da59e2eee9 Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Wed, 6 Dec 2023 12:55:34 +0800 Subject: [PATCH 73/74] erofs: fix lz4 inplace decompression commit 3c12466b6b7bf1e56f9b32c366a3d83d87afb4de upstream. Currently EROFS can map another compressed buffer for inplace decompression, that was used to handle the cases that some pages of compressed data are actually not in-place I/O. However, like most simple LZ77 algorithms, LZ4 expects the compressed data is arranged at the end of the decompressed buffer and it explicitly uses memmove() to handle overlapping: __________________________________________________________ |_ direction of decompression --> ____ |_ compressed data _| Although EROFS arranges compressed data like this, it typically maps two individual virtual buffers so the relative order is uncertain. Previously, it was hardly observed since LZ4 only uses memmove() for short overlapped literals and x86/arm64 memmove implementations seem to completely cover it up and they don't have this issue. Juhyung reported that EROFS data corruption can be found on a new Intel x86 processor. After some analysis, it seems that recent x86 processors with the new FSRM feature expose this issue with "rep movsb". Let's strictly use the decompressed buffer for lz4 inplace decompression for now. Later, as an useful improvement, we could try to tie up these two buffers together in the correct order. Reported-and-tested-by: Juhyung Park Closes: https://lore.kernel.org/r/CAD14+f2AVKf8Fa2OO1aAUdDNTDsVzzR6ctU_oJSmTyd6zSYR2Q@mail.gmail.com Fixes: 0ffd71bcc3a0 ("staging: erofs: introduce LZ4 decompression inplace") Fixes: 598162d05080 ("erofs: support decompress big pcluster for lz4 backend") Cc: stable # 5.4+ Tested-by: Yifan Zhao Signed-off-by: Gao Xiang Link: https://lore.kernel.org/r/20231206045534.3920847-1-hsiangkao@linux.alibaba.com Signed-off-by: Greg Kroah-Hartman Change-Id: I2a2b773421bbbaef7ec97ec75e0e93bf8a78255e --- fs/erofs/decompressor.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/fs/erofs/decompressor.c b/fs/erofs/decompressor.c index 5396cf0ca1d4..04468c05cba7 100644 --- a/fs/erofs/decompressor.c +++ b/fs/erofs/decompressor.c @@ -23,7 +23,8 @@ struct z_erofs_decompressor { */ int (*prepare_destpages)(struct z_erofs_decompress_req *rq, struct list_head *pagepool); - int (*decompress)(struct z_erofs_decompress_req *rq, u8 *out); + int (*decompress)(struct z_erofs_decompress_req *rq, u8 *out, + u8 *obase); char *name; }; @@ -150,10 +151,13 @@ static void *generic_copy_inplace_data(struct z_erofs_decompress_req *rq, return tmp; } -static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) +static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out, + u8 *obase) { + const uint nrpages_out = PAGE_ALIGN(rq->pageofs_out + + rq->outputsize) >> PAGE_SHIFT; unsigned int inputmargin, inlen; - u8 *src; + u8 *src, *src2; bool copied, support_0padding; int ret; @@ -161,6 +165,7 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) return -EOPNOTSUPP; src = kmap_atomic(*rq->in); + src2 = src; inputmargin = 0; support_0padding = false; @@ -183,16 +188,15 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) if (rq->inplace_io) { const uint oend = (rq->pageofs_out + rq->outputsize) & ~PAGE_MASK; - const uint nr = PAGE_ALIGN(rq->pageofs_out + - rq->outputsize) >> PAGE_SHIFT; - if (rq->partial_decoding || !support_0padding || - rq->out[nr - 1] != rq->in[0] || + rq->out[nrpages_out - 1] != rq->in[0] || rq->inputsize - oend < LZ4_DECOMPRESS_INPLACE_MARGIN(inlen)) { src = generic_copy_inplace_data(rq, src, inputmargin); inputmargin = 0; copied = true; + } else { + src = obase + ((nrpages_out - 1) << PAGE_SHIFT); } } @@ -222,7 +226,7 @@ static int z_erofs_lz4_decompress(struct z_erofs_decompress_req *rq, u8 *out) if (copied) erofs_put_pcpubuf(src); else - kunmap_atomic(src); + kunmap_atomic(src2); return ret; } @@ -292,7 +296,7 @@ static int z_erofs_decompress_generic(struct z_erofs_decompress_req *rq, return PTR_ERR(dst); rq->inplace_io = false; - ret = alg->decompress(rq, dst); + ret = alg->decompress(rq, dst, NULL); if (!ret) copy_from_pcpubuf(rq->out, dst, rq->pageofs_out, rq->outputsize); @@ -326,7 +330,7 @@ static int z_erofs_decompress_generic(struct z_erofs_decompress_req *rq, dst_maptype = 2; dstmap_out: - ret = alg->decompress(rq, dst + rq->pageofs_out); + ret = alg->decompress(rq, dst + rq->pageofs_out, dst); if (!dst_maptype) kunmap_atomic(dst); From 30cc8bc23ac2dbb5081b48dcfc2580410efd6320 Mon Sep 17 00:00:00 2001 From: Manoj Prabhu B Date: Tue, 3 Oct 2023 12:09:39 +0530 Subject: [PATCH 74/74] BACKPORT: memshare: Prevent possible integer overflow Prevent possible integer overflow by sanitizing the alloc request size coming from the client against allottable amount of memory. Change-Id: I74cb0f7b0808f20299586969fd5c810d44c3e576 Signed-off-by: Manoj Prabhu B Signed-off-by: Michael Bestas --- drivers/soc/qcom/memshare/msm_memshare.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/memshare/msm_memshare.c b/drivers/soc/qcom/memshare/msm_memshare.c index 35e600a7bad9..8e8e28a79c34 100644 --- a/drivers/soc/qcom/memshare/msm_memshare.c +++ b/drivers/soc/qcom/memshare/msm_memshare.c @@ -481,8 +481,12 @@ static void handle_alloc_generic_req(struct qmi_handle *handle, return; } - if (!memblock[client_id].allotted) { - if (memblock[client_id].guard_band && alloc_req->num_bytes > 0) + if (!memblock[client_id].allotted && alloc_req->num_bytes > 0) { + + if (alloc_req->num_bytes > memblock[client_id].init_size) + alloc_req->num_bytes = memblock[client_id].init_size; + + if (memblock[client_id].guard_band) size = alloc_req->num_bytes + MEMSHARE_GUARD_BYTES; else size = alloc_req->num_bytes;