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ARM: 8914/1: NOMMU: Fix exc_ret for XIP

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[ Upstream commit 4c0742f65b4ee466546fd24b71b56516cacd4613 ]

It was reported that 72cd4064fcca "NOMMU: Toggle only bits in
EXC_RETURN we are really care of" breaks NOMMU+XIP combination.
It happens because saved EXC_RETURN gets overwritten when data
section is relocated.

The fix is to propagate EXC_RETURN via register and let relocation
code to commit that value into memory.

Fixes: 72cd4064fcca ("ARM: 8830/1: NOMMU: Toggle only bits in EXC_RETURN we are really care of")
Reported-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Tested-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Vladimir Murzin
2019-10-10 10:12:20 +01:00
committed by Greg Kroah-Hartman
parent 394c90d9ce
commit ce005e5d6e
3 changed files with 7 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/kernel/head-common.S
View File

@@ -72,7 +72,7 @@ ENDPROC(__vet_atags)
* The following fragment of code is executed with the MMU on in MMU mode, * The following fragment of code is executed with the MMU on in MMU mode,
* and uses absolute addresses; this is not position independent. * and uses absolute addresses; this is not position independent.
* *
* r0 = cp#15 control register * r0 = cp#15 control register (exc_ret for M-class)
* r1 = machine ID * r1 = machine ID
* r2 = atags/dtb pointer * r2 = atags/dtb pointer
* r9 = processor ID * r9 = processor ID
@@ -141,7 +141,8 @@ __mmap_switched_data:
#ifdef CONFIG_CPU_CP15 #ifdef CONFIG_CPU_CP15
.long cr_alignment @ r3 .long cr_alignment @ r3
#else #else
.long 0 @ r3 M_CLASS(.long exc_ret) @ r3
AR_CLASS(.long 0) @ r3
#endif #endif
.size __mmap_switched_data, . - __mmap_switched_data .size __mmap_switched_data, . - __mmap_switched_data

2
arch/arm/kernel/head-nommu.S
View File

@@ -205,6 +205,8 @@ M_CLASS(streq r3, [r12, #PMSAv8_MAIR1])
bic r0, r0, #V7M_SCB_CCR_IC bic r0, r0, #V7M_SCB_CCR_IC
#endif #endif
str r0, [r12, V7M_SCB_CCR] str r0, [r12, V7M_SCB_CCR]
/* Pass exc_ret to __mmap_switched */
mov r0, r10
#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */ #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
ret lr ret lr
ENDPROC(__after_proc_init) ENDPROC(__after_proc_init)

5
arch/arm/mm/proc-v7m.S
View File

@@ -139,9 +139,8 @@ __v7m_setup_cont:
cpsie i cpsie i
svc #0 svc #0
1: cpsid i 1: cpsid i
ldr r0, =exc_ret /* Calculate exc_ret */
orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
str lr, [r0]
ldmia sp, {r0-r3, r12} ldmia sp, {r0-r3, r12}
str r5, [r12, #11 * 4] @ restore the original SVC vector entry str r5, [r12, #11 * 4] @ restore the original SVC vector entry
mov lr, r6 @ restore LR mov lr, r6 @ restore LR