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msm: kgsl: Set correct values for SMMU protect register for A3xx

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For programming the CP Protect register for SMMU in A3xx GPU, pass
correct values for SMMU registers base offset and the count of
registers to be protected.

Change-Id: I9fa809db79efc79bb7a59304fa2b4607ed1fc567
Signed-off-by: Archana Sriram <apsrir@codeaurora.org>
This commit is contained in:
Archana Sriram
2021-02-23 12:39:12 +05:30
parent d64fa8ebd1
commit c3db91f1a5
1 changed files with 9 additions and 3 deletions
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12
drivers/gpu/msm/adreno_a3xx.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2019,2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk/qcom.h>
@@ -1094,8 +1094,14 @@ struct {
{ A3XX_CP_PROTECT_REG_0 + 13, 0x0cc0, 0 },
/* VBIF */
{ A3XX_CP_PROTECT_REG_0 + 14, 0x3000, 6 },
/* SMMU */
{ A3XX_CP_PROTECT_REG_0 + 15, 0xa000, 12 },
/*
* SMMU
* For A3xx, base offset for smmu region is 0xa000 and length is
* 0x1000 bytes. Offset must be in dword and length of the block
* must be ilog2(dword length).
* 0xa000 >> 2 = 0x2800, ilog2(0x1000 >> 2) = 10.
*/
{ A3XX_CP_PROTECT_REG_0 + 15, 0x2800, 10 },
/* There are no remaining protected mode registers for a3xx */
};