From b07d219d61d7da98b45f277f3f4a0f73a903dc56 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Wed, 22 Jul 2020 12:43:30 +0530 Subject: [PATCH] i3c: i3c-master-qcom-geni: Fix wrong reset of the TX, RX engine This change corrects the wrong reset of the Primary and Secondary Engine of the QUP SE upon read, write error. Change-Id: I6d1461864745e22f10f87521947a934dcb02d161 Signed-off-by: Mukesh Kumar Savaliya --- drivers/i3c/master/i3c-master-qcom-geni.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/i3c-master-qcom-geni.c b/drivers/i3c/master/i3c-master-qcom-geni.c index b45032317d31..a716456f6fa4 100644 --- a/drivers/i3c/master/i3c-master-qcom-geni.c +++ b/drivers/i3c/master/i3c-master-qcom-geni.c @@ -806,10 +806,10 @@ static int _i3c_geni_execute_command if (gi3c->err) { if (rnw == READ_TRANSACTION) writel_relaxed(1, gi3c->se.base + - SE_DMA_TX_FSM_RST); + SE_DMA_RX_FSM_RST); else writel_relaxed(1, gi3c->se.base + - SE_DMA_RX_FSM_RST); + SE_DMA_TX_FSM_RST); wait_for_completion_timeout(&gi3c->done, XFER_TIMEOUT); } geni_se_rx_dma_unprep(gi3c->se.i3c_rsc.wrapper_dev,