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arm64: Force SSBS on context switch

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On a CPU that doesn't support SSBS, PSTATE[12] is RES0.  In a system
where only some of the CPUs implement SSBS, we end-up losing track of
the SSBS bit across task migration.

To address this issue, let's force the SSBS bit on context switch.

Change-Id: Ifb8836b7a616db5fd21f6de780693dd9f97adad9
Fixes: 8f04e8e6e29c ("arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Git-commit: 11ce805228fe1ac14225b4886fb396b485981263
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
[neeraju@codeaurora: Resolve trivial merge conflicts]
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
This commit is contained in:
Marc Zyngier
2019-06-04 17:35:18 +01:00
committed by Neeraj Upadhyay
parent 25bd7a1bd2
commit 94a498ae30
2 changed files with 27 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm64/include/asm/processor.h
View File

@@ -180,6 +180,16 @@ static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
regs->pc = pc; regs->pc = pc;
} }
static inline void set_ssbs_bit(struct pt_regs *regs)
{
regs->pstate |= PSR_SSBS_BIT;
}
static inline void set_compat_ssbs_bit(struct pt_regs *regs)
{
regs->pstate |= PSR_AA32_SSBS_BIT;
}
static inline void start_thread(struct pt_regs *regs, unsigned long pc, static inline void start_thread(struct pt_regs *regs, unsigned long pc,
unsigned long sp) unsigned long sp)
{ {
@@ -187,7 +197,7 @@ static inline void start_thread(struct pt_regs *regs, unsigned long pc,
regs->pstate = PSR_MODE_EL0t; regs->pstate = PSR_MODE_EL0t;
if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
regs->pstate |= PSR_SSBS_BIT; set_ssbs_bit(regs);
regs->sp = sp; regs->sp = sp;
} }
@@ -206,7 +216,7 @@ static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
#endif #endif
if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
regs->pstate |= PSR_AA32_SSBS_BIT; set_compat_ssbs_bit(regs);
regs->compat_sp = sp; regs->compat_sp = sp;
} }

15
arch/arm64/kernel/process.c
View File

@@ -480,6 +480,20 @@ void uao_thread_switch(struct task_struct *next)
} }
} }
static void ssbs_thread_switch(struct task_struct *next)
{
if (likely(!(next->flags & PF_KTHREAD)) &&
arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE &&
!test_tsk_thread_flag(next, TIF_SSBD)) {
struct pt_regs *regs = task_pt_regs(next);
if (compat_user_mode(regs))
set_compat_ssbs_bit(regs);
else if (user_mode(regs))
set_ssbs_bit(regs);
}
}
/* /*
* We store our current task in sp_el0, which is clobbered by userspace. Keep a * We store our current task in sp_el0, which is clobbered by userspace. Keep a
* shadow copy so that we can restore this upon entry from userspace. * shadow copy so that we can restore this upon entry from userspace.
@@ -508,6 +522,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
contextidr_thread_switch(next); contextidr_thread_switch(next);
entry_task_switch(next); entry_task_switch(next);
uao_thread_switch(next); uao_thread_switch(next);
ssbs_thread_switch(next);
/* /*
* Complete any pending TLB or cache maintenance on this CPU in case * Complete any pending TLB or cache maintenance on this CPU in case