TechPanelGM/kernel_xiaomi_sm8250
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byte-cntr: Don't write csr register when byte-cntr is disabled

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It is possible that byte-cntr release happens after byte-cntr is disabled.
Don't write csr register when byte-cntr is disabled to avoid the register
access issue.

Change-Id: Ic818107e1bcbe31e1a55cdc8c0f6ff89ff70564f
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
This commit is contained in:
Mao Jinlong
2021-09-03 23:30:30 +08:00
parent 71add66750
commit 81d63049e6
1 changed files with 2 additions and 1 deletions
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3
drivers/hwtracing/coresight/coresight-byte-cntr.c
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@@ -181,7 +181,8 @@ static int tmc_etr_byte_cntr_release(struct inode *in, struct file *fp)
mutex_lock(&byte_cntr_data->byte_cntr_lock); mutex_lock(&byte_cntr_data->byte_cntr_lock);
byte_cntr_data->read_active = false; byte_cntr_data->read_active = false;
coresight_csr_set_byte_cntr(byte_cntr_data->csr, 0); if (byte_cntr_data->enable)
coresight_csr_set_byte_cntr(byte_cntr_data->csr, 0);
mutex_unlock(&byte_cntr_data->byte_cntr_lock); mutex_unlock(&byte_cntr_data->byte_cntr_lock);
return 0; return 0;