clk: add bus voting ops for debug purposes
Add bandwidth voting for clk_summary, clk_show and clk_print_regs to allow access to the config space of certain multimedia clock controllers including display, camera, and video. Change-Id: Ia7b8820cd3fc972caf87530a3105b6c90f37e7c5 Signed-off-by: David Dai <daidavid1@codeaurora.org>
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@@ -3236,10 +3236,14 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
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if (!c)
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return;
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if (c->ops->bus_vote)
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c->ops->bus_vote(c->hw, true);
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clk_summary_show_one(s, c, level);
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hlist_for_each_entry(child, &c->children, child_node)
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clk_summary_show_subtree(s, child, level + 1);
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if (c->ops->bus_vote)
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c->ops->bus_vote(c->hw, false);
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}
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static int clk_summary_show(struct seq_file *s, void *data)
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@@ -3287,6 +3291,9 @@ static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
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if (!c)
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return;
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if (c->ops->bus_vote)
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c->ops->bus_vote(c->hw, true);
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clk_dump_one(s, c, level);
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hlist_for_each_entry(child, &c->children, child_node) {
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@@ -3295,6 +3302,9 @@ static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
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}
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seq_putc(s, '}');
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if (c->ops->bus_vote)
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c->ops->bus_vote(c->hw, false);
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}
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static int clk_dump_show(struct seq_file *s, void *data)
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@@ -3596,7 +3606,15 @@ void clk_debug_print_hw(struct clk_core *clk, struct seq_file *f)
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if (!clk->ops->list_registers)
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return;
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clk_prepare_lock();
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if (clk->ops->bus_vote)
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clk->ops->bus_vote(clk->hw, true);
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clk->ops->list_registers(f, clk->hw);
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if (clk->ops->bus_vote)
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clk->ops->bus_vote(clk->hw, false);
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clk_prepare_unlock();
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}
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EXPORT_SYMBOL(clk_debug_print_hw);
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@@ -3604,8 +3622,16 @@ static int print_hw_show(struct seq_file *m, void *unused)
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{
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struct clk_core *c = m->private;
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clk_prepare_lock();
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if (c->ops->bus_vote)
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c->ops->bus_vote(c->hw, true);
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clk_debug_print_hw(c, m);
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if (c->ops->bus_vote)
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c->ops->bus_vote(c->hw, false);
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clk_prepare_unlock();
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return 0;
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}
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@@ -219,6 +219,9 @@ struct clk_duty {
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* clock that is below rate_max. Return -ENXIO in case there is
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* no frequency table.
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*
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* @bus_vote: Votes for bandwidth on certain config slaves to connect
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* ports in order to gain access to clock controllers.
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*
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* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
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* implementations to split any work between atomic (enable) and sleepable
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* (prepare) contexts. If enabling a clock requires code that might sleep,
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@@ -267,6 +270,7 @@ struct clk_ops {
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struct clk_hw *hw);
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long (*list_rate)(struct clk_hw *hw, unsigned int n,
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unsigned long rate_max);
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void (*bus_vote)(struct clk_hw *hw, bool enable);
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};
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/**
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@@ -281,6 +285,7 @@ struct clk_ops {
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* @vdd_class: voltage scaling requirement class
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* @rate_max: maximum clock rate in Hz supported at each voltage level
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* @num_rate_max: number of maximum voltage level supported
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* @bus_cl_id: client id registered with the bus driver used for bw votes
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*/
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struct clk_init_data {
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const char *name;
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@@ -291,6 +296,7 @@ struct clk_init_data {
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struct clk_vdd_class *vdd_class;
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unsigned long *rate_max;
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int num_rate_max;
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unsigned int bus_cl_id;
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};
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struct regulator;
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