clk: Export the clock driver's voltage voting APIs
There could be special voltage requirements for a clock in addition to what the clock framework already takes care of. Export the APIs to vote on the corresponding voltage rails on behalf on these clocks for use from the individual clock-type drivers. Change-Id: I818d6f17176372791b6040bc8c5d6f7c40f697df Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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@@ -724,7 +724,7 @@ static int clk_unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
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/*
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* Vote for a voltage level corresponding to a clock's rate.
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*/
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static int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate)
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int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate)
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{
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int level;
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@@ -737,11 +737,12 @@ static int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate)
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return clk_vote_vdd_level(core->vdd_class, level);
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}
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EXPORT_SYMBOL_GPL(clk_vote_rate_vdd);
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/*
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* Remove vote for a voltage level corresponding to a clock's rate.
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*/
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static void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate)
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void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate)
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{
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int level;
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@@ -754,6 +755,7 @@ static void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate)
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clk_unvote_vdd_level(core->vdd_class, level);
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}
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EXPORT_SYMBOL_GPL(clk_unvote_rate_vdd);
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static bool clk_is_rate_level_valid(struct clk_core *core, unsigned long rate)
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{
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@@ -889,6 +889,8 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
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unsigned long clk_aggregate_rate(struct clk_hw *hw,
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const struct clk_core *parent);
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int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate);
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void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate);
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static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
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{
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