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Merge remote-tracking branch 'qcom_sm8250/lineage-20' into lineage-20

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Change-Id: Ic572f479a072cb0252d5682f6cd56c3499fe3286
This commit is contained in:
Sebastiano Barezzi
2024-02-13 00:46:27 +01:00
parent b2840744e7 bfc560ed37
commit 0c13f6583a
2707 changed files with 301644 additions and 30852 deletions
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68
include/uapi/linux/affs_hardblocks.h
View File

@@ -7,42 +7,42 @@
/* Just the needed definitions for the RDB of an Amiga HD. */
struct RigidDiskBlock {
__u32 rdb_ID;
__be32 rdb_ID;
__be32 rdb_SummedLongs;
__s32 rdb_ChkSum;
__u32 rdb_HostID;
__be32 rdb_ChkSum;
__be32 rdb_HostID;
__be32 rdb_BlockBytes;
__u32 rdb_Flags;
__u32 rdb_BadBlockList;
__be32 rdb_Flags;
__be32 rdb_BadBlockList;
__be32 rdb_PartitionList;
__u32 rdb_FileSysHeaderList;
__u32 rdb_DriveInit;
__u32 rdb_Reserved1[6];
__u32 rdb_Cylinders;
__u32 rdb_Sectors;
__u32 rdb_Heads;
__u32 rdb_Interleave;
__u32 rdb_Park;
__u32 rdb_Reserved2[3];
__u32 rdb_WritePreComp;
__u32 rdb_ReducedWrite;
__u32 rdb_StepRate;
__u32 rdb_Reserved3[5];
__u32 rdb_RDBBlocksLo;
__u32 rdb_RDBBlocksHi;
__u32 rdb_LoCylinder;
__u32 rdb_HiCylinder;
__u32 rdb_CylBlocks;
__u32 rdb_AutoParkSeconds;
__u32 rdb_HighRDSKBlock;
__u32 rdb_Reserved4;
__be32 rdb_FileSysHeaderList;
__be32 rdb_DriveInit;
__be32 rdb_Reserved1[6];
__be32 rdb_Cylinders;
__be32 rdb_Sectors;
__be32 rdb_Heads;
__be32 rdb_Interleave;
__be32 rdb_Park;
__be32 rdb_Reserved2[3];
__be32 rdb_WritePreComp;
__be32 rdb_ReducedWrite;
__be32 rdb_StepRate;
__be32 rdb_Reserved3[5];
__be32 rdb_RDBBlocksLo;
__be32 rdb_RDBBlocksHi;
__be32 rdb_LoCylinder;
__be32 rdb_HiCylinder;
__be32 rdb_CylBlocks;
__be32 rdb_AutoParkSeconds;
__be32 rdb_HighRDSKBlock;
__be32 rdb_Reserved4;
char rdb_DiskVendor[8];
char rdb_DiskProduct[16];
char rdb_DiskRevision[4];
char rdb_ControllerVendor[8];
char rdb_ControllerProduct[16];
char rdb_ControllerRevision[4];
__u32 rdb_Reserved5[10];
__be32 rdb_Reserved5[10];
};
#define IDNAME_RIGIDDISK 0x5244534B /* "RDSK" */
@@ -50,16 +50,16 @@ struct RigidDiskBlock {
struct PartitionBlock {
__be32 pb_ID;
__be32 pb_SummedLongs;
__s32 pb_ChkSum;
__u32 pb_HostID;
__be32 pb_ChkSum;
__be32 pb_HostID;
__be32 pb_Next;
__u32 pb_Flags;
__u32 pb_Reserved1[2];
__u32 pb_DevFlags;
__be32 pb_Flags;
__be32 pb_Reserved1[2];
__be32 pb_DevFlags;
__u8 pb_DriveName[32];
__u32 pb_Reserved2[15];
__be32 pb_Reserved2[15];
__be32 pb_Environment[17];
__u32 pb_EReserved[15];
__be32 pb_EReserved[15];
};
#define IDNAME_PARTITION 0x50415254 /* "PART" */

10
include/uapi/linux/blkzoned.h
View File

@@ -51,13 +51,13 @@ enum blk_zone_type {
*
* The Zone Condition state machine in the ZBC/ZAC standards maps the above
* deinitions as:
* - ZC1: Empty | BLK_ZONE_EMPTY
* - ZC1: Empty | BLK_ZONE_COND_EMPTY
* - ZC2: Implicit Open | BLK_ZONE_COND_IMP_OPEN
* - ZC3: Explicit Open | BLK_ZONE_COND_EXP_OPEN
* - ZC4: Closed | BLK_ZONE_CLOSED
* - ZC5: Full | BLK_ZONE_FULL
* - ZC6: Read Only | BLK_ZONE_READONLY
* - ZC7: Offline | BLK_ZONE_OFFLINE
* - ZC4: Closed | BLK_ZONE_COND_CLOSED
* - ZC5: Full | BLK_ZONE_COND_FULL
* - ZC6: Read Only | BLK_ZONE_COND_READONLY
* - ZC7: Offline | BLK_ZONE_COND_OFFLINE
*
* Conditions 0x5 to 0xC are reserved by the current ZBC/ZAC spec and should
* be considered invalid.

4
include/uapi/linux/bpf.h
View File

@@ -695,7 +695,9 @@ union bpf_attr {
* performed again, if the helper is used in combination with
* direct packet access.
* Return
* 0 on success, or a negative error in case of failure.
* 0 on success, or a negative error in case of failure. Positive
* error indicates a potential drop or congestion in the target
* device. The particular positive error codes are not defined.
*
* u64 bpf_get_current_pid_tgid(void)
* Return

1
include/uapi/linux/btrfs.h
View File

@@ -162,6 +162,7 @@ struct btrfs_scrub_progress {
};
#define BTRFS_SCRUB_READONLY 1
#define BTRFS_SCRUB_SUPPORTED_FLAGS (BTRFS_SCRUB_READONLY)
struct btrfs_ioctl_scrub_args {
__u64 devid; /* in */
__u64 start; /* in */

149
include/uapi/linux/dn.h
View File

@@ -1,149 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _LINUX_DN_H
#define _LINUX_DN_H
#include <linux/ioctl.h>
#include <linux/types.h>
#include <linux/if_ether.h>
/*
DECnet Data Structures and Constants
*/
/*
* DNPROTO_NSP can't be the same as SOL_SOCKET,
* so increment each by one (compared to ULTRIX)
*/
#define DNPROTO_NSP 2 /* NSP protocol number */
#define DNPROTO_ROU 3 /* Routing protocol number */
#define DNPROTO_NML 4 /* Net mgt protocol number */
#define DNPROTO_EVL 5 /* Evl protocol number (usr) */
#define DNPROTO_EVR 6 /* Evl protocol number (evl) */
#define DNPROTO_NSPT 7 /* NSP trace protocol number */
#define DN_ADDL 2
#define DN_MAXADDL 2 /* ULTRIX headers have 20 here, but pathworks has 2 */
#define DN_MAXOPTL 16
#define DN_MAXOBJL 16
#define DN_MAXACCL 40
#define DN_MAXALIASL 128
#define DN_MAXNODEL 256
#define DNBUFSIZE 65023
/*
* SET/GET Socket options - must match the DSO_ numbers below
*/
#define SO_CONDATA 1
#define SO_CONACCESS 2
#define SO_PROXYUSR 3
#define SO_LINKINFO 7
#define DSO_CONDATA 1 /* Set/Get connect data */
#define DSO_DISDATA 10 /* Set/Get disconnect data */
#define DSO_CONACCESS 2 /* Set/Get connect access data */
#define DSO_ACCEPTMODE 4 /* Set/Get accept mode */
#define DSO_CONACCEPT 5 /* Accept deferred connection */
#define DSO_CONREJECT 6 /* Reject deferred connection */
#define DSO_LINKINFO 7 /* Set/Get link information */
#define DSO_STREAM 8 /* Set socket type to stream */
#define DSO_SEQPACKET 9 /* Set socket type to sequenced packet */
#define DSO_MAXWINDOW 11 /* Maximum window size allowed */
#define DSO_NODELAY 12 /* Turn off nagle */
#define DSO_CORK 13 /* Wait for more data! */
#define DSO_SERVICES 14 /* NSP Services field */
#define DSO_INFO 15 /* NSP Info field */
#define DSO_MAX 15 /* Maximum option number */
/* LINK States */
#define LL_INACTIVE 0
#define LL_CONNECTING 1
#define LL_RUNNING 2
#define LL_DISCONNECTING 3
#define ACC_IMMED 0
#define ACC_DEFER 1
#define SDF_WILD 1 /* Wild card object */
#define SDF_PROXY 2 /* Addr eligible for proxy */
#define SDF_UICPROXY 4 /* Use uic-based proxy */
/* Structures */
struct dn_naddr {
__le16 a_len;
__u8 a_addr[DN_MAXADDL]; /* Two bytes little endian */
};
struct sockaddr_dn {
__u16 sdn_family;
__u8 sdn_flags;
__u8 sdn_objnum;
__le16 sdn_objnamel;
__u8 sdn_objname[DN_MAXOBJL];
struct dn_naddr sdn_add;
};
#define sdn_nodeaddrl sdn_add.a_len /* Node address length */
#define sdn_nodeaddr sdn_add.a_addr /* Node address */
/*
* DECnet set/get DSO_CONDATA, DSO_DISDATA (optional data) structure
*/
struct optdata_dn {
__le16 opt_status; /* Extended status return */
#define opt_sts opt_status
__le16 opt_optl; /* Length of user data */
__u8 opt_data[16]; /* User data */
};
struct accessdata_dn {
__u8 acc_accl;
__u8 acc_acc[DN_MAXACCL];
__u8 acc_passl;
__u8 acc_pass[DN_MAXACCL];
__u8 acc_userl;
__u8 acc_user[DN_MAXACCL];
};
/*
* DECnet logical link information structure
*/
struct linkinfo_dn {
__u16 idn_segsize; /* Segment size for link */
__u8 idn_linkstate; /* Logical link state */
};
/*
* Ethernet address format (for DECnet)
*/
union etheraddress {
__u8 dne_addr[ETH_ALEN]; /* Full ethernet address */
struct {
__u8 dne_hiord[4]; /* DECnet HIORD prefix */
__u8 dne_nodeaddr[2]; /* DECnet node address */
} dne_remote;
};
/*
* DECnet physical socket address format
*/
struct dn_addr {
__le16 dna_family; /* AF_DECnet */
union etheraddress dna_netaddr; /* DECnet ethernet address */
};
#define DECNET_IOCTL_BASE 0x89 /* PROTOPRIVATE range */
#define SIOCSNETADDR _IOW(DECNET_IOCTL_BASE, 0xe0, struct dn_naddr)
#define SIOCGNETADDR _IOR(DECNET_IOCTL_BASE, 0xe1, struct dn_naddr)
#define OSIOCSNETADDR _IOW(DECNET_IOCTL_BASE, 0xe0, int)
#define OSIOCGNETADDR _IOR(DECNET_IOCTL_BASE, 0xe1, int)
#endif /* _LINUX_DN_H */

9
include/uapi/linux/fuse.h
View File

@@ -274,6 +274,7 @@ struct fuse_file_lock {
#define FUSE_HANDLE_KILLPRIV (1 << 19)
#define FUSE_POSIX_ACL (1 << 20)
#define FUSE_ABORT_ERROR (1 << 21)
#define FUSE_PASSTHROUGH (1 << 31)
/**
* CUSE INIT request/reply flags
@@ -506,7 +507,7 @@ struct fuse_create_in {
struct fuse_open_out {
uint64_t fh;
uint32_t open_flags;
uint32_t padding;
uint32_t passthrough_fh;
};
struct fuse_release_in {
@@ -782,7 +783,11 @@ struct fuse_notify_retrieve_in {
};
/* Device ioctls: */
#define FUSE_DEV_IOC_CLONE _IOR(229, 0, uint32_t)
#define FUSE_DEV_IOC_MAGIC 229
#define FUSE_DEV_IOC_CLONE _IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t)
/* 127 is reserved for the V1 interface implementation in Android (deprecated) */
/* 126 is reserved for the V2 interface implementation in Android */
#define FUSE_DEV_IOC_PASSTHROUGH_OPEN _IOW(FUSE_DEV_IOC_MAGIC, 126, __u32)
struct fuse_lseek_in {
uint64_t fh;

2
include/uapi/linux/in.h
View File

@@ -154,6 +154,8 @@ struct in_addr {
#define MCAST_MSFILTER 48
#define IP_MULTICAST_ALL 49
#define IP_UNICAST_IF 50
#define IP_LOCAL_PORT_RANGE 51
#define IP_PROTOCOL 52
#define MCAST_EXCLUDE 0
#define MCAST_INCLUDE 1

8
include/uapi/linux/media-bus-format.h
View File

@@ -153,4 +153,12 @@
/* HSV - next is 0x6002 */
#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001
/*
* This format should be used when the same driver handles
* both sides of the link and the bus format is a fixed
* metadata format that is not configurable from userspace.
* Width and height will be set to 0 for this format.
*/
#define MEDIA_BUS_FMT_METADATA_FIXED 0x7001
#endif /* __LINUX_MEDIA_BUS_FORMAT_H */

7
include/uapi/linux/netfilter/xt_owner.h
View File

@@ -5,9 +5,10 @@
#include <linux/types.h>
enum {
XT_OWNER_UID = 1 << 0,
XT_OWNER_GID = 1 << 1,
XT_OWNER_SOCKET = 1 << 2,
XT_OWNER_UID = 1 << 0,
XT_OWNER_GID = 1 << 1,
XT_OWNER_SOCKET = 1 << 2,
XT_OWNER_SUPPL_GROUPS = 1 << 3,
};
struct xt_owner_match_info {

82
include/uapi/linux/netfilter_decnet.h
View File

@@ -1,82 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __LINUX_DECNET_NETFILTER_H
#define __LINUX_DECNET_NETFILTER_H
/* DECnet-specific defines for netfilter.
* This file (C) Steve Whitehouse 1999 derived from the
* ipv4 netfilter header file which is
* (C)1998 Rusty Russell -- This code is GPL.
*/
#include <linux/netfilter.h>
/* only for userspace compatibility */
#ifndef __KERNEL__
#include <limits.h> /* for INT_MIN, INT_MAX */
/* IP Cache bits. */
/* Src IP address. */
#define NFC_DN_SRC 0x0001
/* Dest IP address. */
#define NFC_DN_DST 0x0002
/* Input device. */
#define NFC_DN_IF_IN 0x0004
/* Output device. */
#define NFC_DN_IF_OUT 0x0008
/* kernel define is in netfilter_defs.h */
#define NF_DN_NUMHOOKS 7
#endif /* ! __KERNEL__ */
/* DECnet Hooks */
/* After promisc drops, checksum checks. */
#define NF_DN_PRE_ROUTING 0
/* If the packet is destined for this box. */
#define NF_DN_LOCAL_IN 1
/* If the packet is destined for another interface. */
#define NF_DN_FORWARD 2
/* Packets coming from a local process. */
#define NF_DN_LOCAL_OUT 3
/* Packets about to hit the wire. */
#define NF_DN_POST_ROUTING 4
/* Input Hello Packets */
#define NF_DN_HELLO 5
/* Input Routing Packets */
#define NF_DN_ROUTE 6
enum nf_dn_hook_priorities {
NF_DN_PRI_FIRST = INT_MIN,
NF_DN_PRI_CONNTRACK = -200,
NF_DN_PRI_MANGLE = -150,
NF_DN_PRI_NAT_DST = -100,
NF_DN_PRI_FILTER = 0,
NF_DN_PRI_NAT_SRC = 100,
NF_DN_PRI_DNRTMSG = 200,
NF_DN_PRI_LAST = INT_MAX,
};
struct nf_dn_rtmsg {
int nfdn_ifindex;
};
#define NFDN_RTMSG(r) ((unsigned char *)(r) + NLMSG_ALIGN(sizeof(struct nf_dn_rtmsg)))
#ifndef __KERNEL__
/* backwards compatibility for userspace */
#define DNRMG_L1_GROUP 0x01
#define DNRMG_L2_GROUP 0x02
#endif
enum {
DNRNG_NLGRP_NONE,
#define DNRNG_NLGRP_NONE DNRNG_NLGRP_NONE
DNRNG_NLGRP_L1,
#define DNRNG_NLGRP_L1 DNRNG_NLGRP_L1
DNRNG_NLGRP_L2,
#define DNRNG_NLGRP_L2 DNRNG_NLGRP_L2
__DNRNG_NLGRP_MAX
};
#define DNRNG_NLGRP_MAX (__DNRNG_NLGRP_MAX - 1)
#endif /*__LINUX_DECNET_NETFILTER_H*/

2
include/uapi/linux/netlink.h
View File

@@ -20,7 +20,7 @@
#define NETLINK_CONNECTOR 11
#define NETLINK_NETFILTER 12 /* netfilter subsystem */
#define NETLINK_IP6_FW 13
#define NETLINK_DNRTMSG 14 /* DECnet routing messages */
#define NETLINK_DNRTMSG 14 /* DECnet routing messages (obsolete) */
#define NETLINK_KOBJECT_UEVENT 15 /* Kernel messages to userspace */
#define NETLINK_GENERIC 16
/* leave room for NETLINK_DM (DM Events) */

139
include/uapi/linux/pci_regs.h
View File

@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* pci_regs.h
*
* PCI standard defines
* Copyright 1994, Drew Eckhardt
* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
@@ -15,7 +13,7 @@
* PCI System Design Guide
*
* For HyperTransport information, please consult the following manuals
* from http://www.hypertransport.org
* from http://www.hypertransport.org :
*
* The HyperTransport I/O Link Specification
*/
@@ -300,7 +298,7 @@
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
/* Message Signalled Interrupts registers */
/* Message Signalled Interrupt registers */
#define PCI_MSI_FLAGS 2 /* Message Control */
#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
@@ -318,7 +316,7 @@
#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
/* MSI-X registers */
/* MSI-X registers (in MSI-X capability) */
#define PCI_MSIX_FLAGS 2 /* Message Control */
#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
@@ -332,13 +330,13 @@
#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
/* MSI-X Table entry format */
/* MSI-X Table entry format (in memory mapped by a BAR) */
#define PCI_MSIX_ENTRY_SIZE 16
#define PCI_MSIX_ENTRY_LOWER_ADDR 0
#define PCI_MSIX_ENTRY_UPPER_ADDR 4
#define PCI_MSIX_ENTRY_DATA 8
#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */
#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */
#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */
#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
/* CompactPCI Hotswap Register */
@@ -464,19 +462,19 @@
/* PCI Express capability registers */
#define PCI_EXP_FLAGS 2 /* Capabilities register */
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
@@ -529,6 +527,7 @@
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
@@ -557,6 +556,7 @@
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
@@ -621,8 +621,8 @@
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
#define PCI_EXP_RTSTA 32 /* Root Status */
#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
/*
* The Device Capabilities 2, Device Status 2, Device Control 2,
* Link Capabilities 2, Link Status 2, Link Control 2,
@@ -642,13 +642,13 @@
#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
@@ -662,13 +662,17 @@
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
#define PCI_EXP_LNKCTL2_TLS 0x000f
#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS 0x000f
#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
@@ -757,18 +761,18 @@
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
#define PCI_ERR_ROOT_STATUS 48
#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
/* Virtual Channel */
@@ -879,12 +883,13 @@
/* Page Request Interface */
#define PCI_PRI_CTRL 0x04 /* PRI control register */
#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */
#define PCI_PRI_STATUS 0x06 /* PRI status register */
#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */
#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */
#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
#define PCI_EXT_CAP_PRI_SIZEOF 16
@@ -901,16 +906,16 @@
/* Single Root I/O Virtualization */
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */
#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
@@ -940,13 +945,13 @@
/* Access Control Service */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
#define PCI_ACS_SV 0x01 /* Source Validation */
#define PCI_ACS_TB 0x02 /* Translation Blocking */
#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
#define PCI_ACS_EC 0x20 /* P2P Egress Control */
#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
#define PCI_ACS_SV 0x0001 /* Source Validation */
#define PCI_ACS_TB 0x0002 /* Translation Blocking */
#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */
#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */
#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */
#define PCI_ACS_EC 0x0020 /* P2P Egress Control */
#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */
#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
@@ -996,9 +1001,9 @@
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
#define PCI_EXP_DPC_CTL 6 /* DPC control */
#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */

2
include/uapi/linux/sync_file.h
View File

@@ -52,7 +52,7 @@ struct sync_fence_info {
* @name: name of fence
* @status: status of fence. 1: signaled 0:active <0:error
* @flags: sync_file_info flags
* @num_fences number of fences in the sync_file
* @num_fences: number of fences in the sync_file
* @pad: padding for 64-bit alignment, should always be zero
* @sync_fence_info: pointer to array of structs sync_fence_info with all
* fences in the sync_file

2
include/uapi/linux/videodev2.h
View File

@@ -1635,7 +1635,7 @@ struct v4l2_input {
__u8 name[32]; /* Label */
__u32 type; /* Type of input */
__u32 audioset; /* Associated audios (bitfield) */
__u32 tuner; /* enum v4l2_tuner_type */
__u32 tuner; /* Tuner index */
v4l2_std_id std;
__u32 status;
__u32 capabilities;