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x86/speculation: Rework speculative_store_bypass_update()

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The upcoming support for the virtual SPEC_CTRL MSR on AMD needs to reuse
speculative_store_bypass_update() to avoid code duplication. Add an
argument for supplying a thread info (TIF) value and create a wrapper
speculative_store_bypass_update_current() which is used at the existing
call site.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
This commit is contained in:
Thomas Gleixner
2018-05-10 20:31:44 +02:00
parent 11fb068349
commit 0270be3e34
3 changed files with 9 additions and 4 deletions
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7
arch/x86/include/asm/spec-ctrl.h
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@@ -42,6 +42,11 @@ extern void speculative_store_bypass_ht_init(void);
static inline void speculative_store_bypass_ht_init(void) { } static inline void speculative_store_bypass_ht_init(void) { }
#endif #endif
extern void speculative_store_bypass_update(void); extern void speculative_store_bypass_update(unsigned long tif);
static inline void speculative_store_bypass_update_current(void)
{
speculative_store_bypass_update(current_thread_info()->flags);
}
#endif #endif

2
arch/x86/kernel/cpu/bugs.c
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@@ -598,7 +598,7 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
* mitigation until it is next scheduled. * mitigation until it is next scheduled.
*/ */
if (task == current && update) if (task == current && update)
speculative_store_bypass_update(); speculative_store_bypass_update_current();
return 0; return 0;
} }

4
arch/x86/kernel/process.c
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@@ -414,10 +414,10 @@ static __always_inline void __speculative_store_bypass_update(unsigned long tifn
intel_set_ssb_state(tifn); intel_set_ssb_state(tifn);
} }
void speculative_store_bypass_update(void) void speculative_store_bypass_update(unsigned long tif)
{ {
preempt_disable(); preempt_disable();
__speculative_store_bypass_update(current_thread_info()->flags); __speculative_store_bypass_update(tif);
preempt_enable(); preempt_enable();
} }